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src/opcodes ChangeLog cgen-dis.in m32r-asm.c m ...
- To: binutils-cvs at sourceware dot cygnus dot com
- Subject: src/opcodes ChangeLog cgen-dis.in m32r-asm.c m ...
- From: fche at sourceware dot cygnus dot com
- Date: 4 May 2001 17:45:20 -0000
CVSROOT: /cvs/src
Module name: src
Changes by: fche@sources.redhat.com 2001-05-04 10:45:20
Modified files:
opcodes : ChangeLog cgen-dis.in m32r-asm.c m32r-dis.c
m32r-ibld.c
Log message:
* m32r disasm bug fix
2001-05-04 Frank Ch. Eigler <fche@redhat.com>
* m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes.
2001-05-04 Frank Ch. Eigler <fche@redhat.com>
* cgen-dis.in (print_insn): Remove call to read_insn. Instead,
assume incoming buffer already has the base insn loaded. Handle
case of smaller-than-base instructions for variable-length case.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.260&r2=1.261
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/cgen-dis.in.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32r-asm.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32r-dis.c.diff?cvsroot=src&r1=1.9&r2=1.10
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32r-ibld.c.diff?cvsroot=src&r1=1.8&r2=1.9