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src cpu/ChangeLog cpu/m32c.cpu opcodes/ChangeL ...
- From: dj at sourceware dot org
- To: binutils-cvs at sourceware dot org
- Date: 29 Mar 2007 23:56:39 -0000
- Subject: src cpu/ChangeLog cpu/m32c.cpu opcodes/ChangeL ...
CVSROOT: /cvs/src
Module name: src
Changes by: dj@sourceware.org 2007-03-30 00:56:39
Modified files:
cpu : ChangeLog m32c.cpu
opcodes : ChangeLog m32c-desc.c m32c-dis.c m32c-opc.c
gas : ChangeLog
gas/config : tc-m32c.c
Log message:
* m32c.cpu (Imm-8-s4n): Fix print hook.
(Lab-24-8, Lab-32-8, Lab-40-8): Fix.
(arith-jnz-imm4-dst-defn): Make relaxable.
(arith-jnz16-imm4-dst-defn): Fix encodings.
* m32c-desc.c: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-opc.c: Regenerate.
* config/tc-m32c.c (rl_for, relaxable): Protect argument.
(md_relax_table): Add entries for ADJNZ macros.
(M32C_Macros): Add ADJNZ macros.
(subtype_mappings): Add entries for ADJNZ macros.
(insn_to_subtype): Check for adjnz and sbjnz insns.
(md_estimate_size_before_relax): Pass insn to insn_to_subtype.
(md_convert_frag): Convert adjnz and sbjnz.
Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/cpu/ChangeLog.diff?cvsroot=src&r1=1.74&r2=1.75
http://sourceware.org/cgi-bin/cvsweb.cgi/src/cpu/m32c.cpu.diff?cvsroot=src&r1=1.14&r2=1.15
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1046&r2=1.1047
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/m32c-desc.c.diff?cvsroot=src&r1=1.15&r2=1.16
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/m32c-dis.c.diff?cvsroot=src&r1=1.11&r2=1.12
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/m32c-opc.c.diff?cvsroot=src&r1=1.14&r2=1.15
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/ChangeLog.diff?cvsroot=src&r1=1.3197&r2=1.3198
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-m32c.c.diff?cvsroot=src&r1=1.12&r2=1.13