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Patch: prefix hppa float reg codes
- To: binutils@sourceware.cygnus.com
- Subject: Patch: prefix hppa float reg codes
- From: "Jerry Quinn" <jquinn@nortelnetworks.com>
- Date: Thu, 12 Aug 1999 22:54:44 +0000
This patch groups all the float register codes behind the prefix 'f'. This
should be the final prefixing we need. I think at this point there are enough
codes to finish off the PA2.0 instruction set.
Jerry
ChangeLog entry:
Thu Aug 12 18:50:51 EDT 1999
* hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args by
'f'.
* tc-hppa.c (pa_ip): Same.
* hppa-dis.c (print_insn_hppa): Same.
*** gas-src/include/opcode/hppa.h Thu Aug 12 18:32:19 1999
--- src-prev/include/opcode/hppa.h Thu Aug 12 16:29:07 1999
***************
*** 70,78 ****
In the args field, the following characters are unused:
! ' "# %& +- / :;< > @'
! ' BC LM U YZ[\] '
! ' de gh lm q {|} '
Here are all the characters:
--- 70,78 ----
In the args field, the following characters are unused:
! ' "# %& +- / 34 6789:;< > @'
! ' BC JKLM XYZ[\] '
! ' de gh lm q y {|} '
Here are all the characters:
***************
*** 85,91 ****
b integer register field at 10.
t integer register field at 31.
a integer register field at 10 and 15 (for PERMH)
- y floating point register field at 31
5 5 bit immediate at 15.
s 2 bit space specifier at 17.
S 3 bit space specifier at 18.
--- 85,90 ----
***************
*** 99,104 ****
--- 98,146 ----
W 17 bit branch displacement (PC relative)
z 17 bit branch displacement (just a number, not an address)
+ Also these:
+
+ . 2 bit shift amount at 25
+ * 4 bit shift amount at 25
+ p 5 bit shift count at 26 (to support the SHD instruction) encoded as
+ 31-p
+ ~ 6 bit shift count at 20,22:26 encoded as 63-~.
+ P 5 bit bit position at 26
+ T 5 bit field length at 31 (encoded as 32-T)
+ A 13 bit immediate at 18 (to support the BREAK instruction)
+ ^ like b, but describes a control register
+ ! sar (cr11) register
+ D 26 bit immediate at 31 (to support the DIAG instruction)
+ $ 9 bit immediate at 28 (to support POPBTS)
+
+ v 3 bit Special Function Unit identifier at 25
+ O 20 bit Special Function Unit operation split between 15 bits at 20
+ and 5 bits at 31
+ o 15 bit Special Function Unit operation at 20
+ 2 22 bit Special Function Unit operation split between 17 bits at 20
+ and 5 bits at 31
+ 1 15 bit Special Function Unit operation split between 10 bits at 20
+ and 5 bits at 31
+ 0 10 bit Special Function Unit operation split between 5 bits at 20
+ and 5 bits at 31
+ u 3 bit coprocessor unit identifier at 25
+ F Source Floating Point Operand Format Completer encoded 2 bits at 20
+ I Source Floating Point Operand Format Completer encoded 1 bits at 20
+ (for 0xe format FP instructions)
+ G Destination Floating Point Operand Format Completer encoded 2 bits at 18
+ H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
+ (very similar to 'F')
+
+ r 5 bit immediate value at 31 (for the break instruction)
+ (very similar to V above, except the value is unsigned instead of
+ low_sign_ext)
+ R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
+ (same as r above, except the value is in a different location)
+ U 10 bit immediate value at 15 (for SSM, RSM on pa2.0)
+ Q 5 bit immediate value at 10 (a bit position specified in
+ the bb instruction. It's the same as r above, except the
+ value is in a different location)
+
Completer operands all have 'c' as the prefix:
cx indexed load completer.
***************
*** 160,221 ****
?u unit conditions
?U 64 bit unit conditions
! Also these:
! p 5 bit shift count at 26 (to support the SHD instruction) encoded as
! 31-p
! ~ 6 bit shift count at 20,22:26 encoded as 63-~.
! P 5 bit bit position at 26
! T 5 bit field length at 31 (encoded as 32-T)
! A 13 bit immediate at 18 (to support the BREAK instruction)
! . 2 bit shift amount at 24:25
! * 4 bit shift amount at 25
! ^ like b, but describes a control register
! ! sar (cr11) register
! Z System Control Completer (to support LPA, LHA, etc.)
! D 26 bit immediate at 31 (to support the DIAG instruction)
! $ 9 bit immediate at 28 (to support 'popbts')
- f 3 bit Special Function Unit identifier at 25
- O 20 bit Special Function Unit operation split between 15 bits at 20
- and 5 bits at 31
- o 15 bit Special Function Unit operation at 20
- 2 22 bit Special Function Unit operation split between 17 bits at 20
- and 5 bits at 31
- 1 15 bit Special Function Unit operation split between 10 bits at 20
- and 5 bits at 31
- 0 10 bit Special Function Unit operation split between 5 bits at 20
- and 5 bits at 31
- u 3 bit coprocessor unit identifier at 25
- F Source Floating Point Operand Format Completer encoded 2 bits at 20
- I Source Floating Point Operand Format Completer encoded 1 bits at 20
- (for 0xe format FP instructions)
- G Destination Floating Point Operand Format Completer encoded 2 bits at 18
-
- r 5 bit immediate value at 31 (for the break instruction)
- (very similar to V above, except the value is unsigned instead of
- low_sign_ext)
- R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
- (same as r above, except the value is in a different location)
- U 10 bit immediate value at 15 (for SSM, RSM on pa2.0)
- Q 5 bit immediate value at 10 (a bit position specified in
- the bb instruction. It's the same as r above, except the
- value is in a different location)
-
- And these (PJH) for PA-89 F.P. registers and instructions:
-
- v a 't' operand type extended to handle L/R register halves.
- E a 'b' operand type extended to handle L/R register halves.
- X an 'x' operand type extended to handle L/R register halves.
- J a 'b' operand type further extended to handle extra 1.1 registers
- K a 'x' operand type further extended to handle extra 1.1 registers
- 4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub'
- 6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub'
- 7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub'
- 8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub')
- 9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub')
- H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
- (very similar to 'F')
*/
--- 202,225 ----
?u unit conditions
?U 64 bit unit conditions
! Floating point registers all have 'f' as a prefix:
! ft target register at 31
! fT target register with L/R halves at 31
! fa operand 1 register at 10
! fA operand 1 register with L/R halves at 10
! fb operand 2 register at 15
! fB operand 2 register with L/R halves at 15
! fC operand 3 register with L/R halves at 16:18,21:23
!
! Float registers for fmpyadd and fmpysub:
!
! fi mult operand 1 register at 10
! fj mult operand 2 register at 15
! fk mult target register at 20
! fl add/sub operand register at 25
! fm add/sub target register at 31
*/
***************
*** 532,594 ****
/* Floating Point Coprocessor Instructions */
! { "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),v", pa10},
! { "fldwx", 0x24000000, 0xfc001f80, "cxx(b),v", pa10},
! { "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),y", pa10},
! { "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),y", pa10},
! { "fstwx", 0x24000200, 0xfc001f80, "cxv,x(s,b)", pa10},
! { "fstwx", 0x24000200, 0xfc001f80, "cxv,x(b)", pa10},
! { "fstdx", 0x2c000200, 0xfc001fc0, "cxy,x(s,b)", pa10},
! { "fstdx", 0x2c000200, 0xfc001fc0, "cxy,x(b)", pa10},
! { "fstqx", 0x3c000200, 0xfc001fc0, "cxy,x(s,b)", pa10},
! { "fstqx", 0x3c000200, 0xfc001fc0, "cxy,x(b)", pa10},
! { "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),v", pa10},
! { "fldws", 0x24001000, 0xfc001f80, "cm5(b),v", pa10},
! { "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),y", pa10},
! { "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),y", pa10},
! { "fstws", 0x24001200, 0xfc001f80, "cmv,5(s,b)", pa10},
! { "fstws", 0x24001200, 0xfc001f80, "cmv,5(b)", pa10},
! { "fstds", 0x2c001200, 0xfc001fc0, "cmy,5(s,b)", pa10},
! { "fstds", 0x2c001200, 0xfc001fc0, "cmy,5(b)", pa10},
! { "fstqs", 0x3c001200, 0xfc001fc0, "cmy,5(s,b)", pa10},
! { "fstqs", 0x3c001200, 0xfc001fc0, "cmy,5(b)", pa10},
! { "fadd", 0x30000600, 0xfc00e7e0, "FE,X,v", pa10},
! { "fadd", 0x38000600, 0xfc00e720, "IJ,K,v", pa10},
! { "fsub", 0x30002600, 0xfc00e7e0, "FE,X,v", pa10},
! { "fsub", 0x38002600, 0xfc00e720, "IJ,K,v", pa10},
! { "fmpy", 0x30004600, 0xfc00e7e0, "FE,X,v", pa10},
! { "fmpy", 0x38004600, 0xfc00e720, "IJ,K,v", pa10},
! { "fdiv", 0x30006600, 0xfc00e7e0, "FE,X,v", pa10},
! { "fdiv", 0x38006600, 0xfc00e720, "IJ,K,v", pa10},
! { "fsqrt", 0x30008000, 0xfc1fe7e0, "FE,v", pa10},
! { "fsqrt", 0x38008000, 0xfc1fe720, "FJ,v", pa10},
! { "fabs", 0x30006000, 0xfc1fe7e0, "FE,v", pa10},
! { "fabs", 0x38006000, 0xfc1fe720, "FJ,v", pa10},
! { "frem", 0x30008600, 0xfc00e7e0, "FE,X,v", pa10},
! { "frem", 0x38008600, 0xfc00e720, "FJ,K,v", pa10},
! { "frnd", 0x3000a000, 0xfc1fe7e0, "FE,v", pa10},
! { "frnd", 0x3800a000, 0xfc1fe720, "FJ,v", pa10},
! { "fcpy", 0x30004000, 0xfc1fe7e0, "FE,v", pa10},
! { "fcpy", 0x38004000, 0xfc1fe720, "FJ,v", pa10},
! { "fcnvff", 0x30000200, 0xfc1f87e0, "FGE,v", pa10},
! { "fcnvff", 0x38000200, 0xfc1f8720, "FGJ,v", pa10},
! { "fcnvxf", 0x30008200, 0xfc1f87e0, "FGE,v", pa10},
! { "fcnvxf", 0x38008200, 0xfc1f8720, "FGJ,v", pa10},
! { "fcnvfx", 0x30010200, 0xfc1f87e0, "FGE,v", pa10},
! { "fcnvfx", 0x38010200, 0xfc1f8720, "FGJ,v", pa10},
! { "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGE,v", pa10},
! { "fcnvfxt", 0x38018200, 0xfc1f8720, "FGJ,v", pa10},
! { "fmpyfadd", 0xb8000000, 0xfc000020, "IJ,K,3,v", pa20, FLAG_STRICT},
! { "fmpynfadd", 0xb8000020, 0xfc000020, "IJ,K,3,v", pa20, FLAG_STRICT},
! { "fneg", 0x3000c000, 0xfc1fe7e0, "FE,v", pa20, FLAG_STRICT},
! { "fneg", 0x3800c000, 0xfc1fe720, "IJ,v", pa20, FLAG_STRICT},
! { "fnegabs", 0x3000e000, 0xfc1fe7e0, "FE,v", pa20, FLAG_STRICT},
! { "fnegabs", 0x3800e000, 0xfc1fe720, "IJ,v", pa20, FLAG_STRICT},
! { "fcmp", 0x30000400, 0xfc00e7e0, "F?fE,X", pa10},
! { "fcmp", 0x38000400, 0xfc00e720, "I?fJ,K", pa10},
! { "xmpyu", 0x38004700, 0xfc00e720, "J,K,v", pa11},
! { "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8", pa11},
! { "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8", pa11},
{ "ftest", 0x30002420, 0xffffffff, "", pa10},
{ "fid", 0x30000000, 0xffffffff, "", pa11},
--- 536,598 ----
/* Floating Point Coprocessor Instructions */
! { "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10},
! { "fldwx", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10},
! { "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10},
! { "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10},
! { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10},
! { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10},
! { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10},
! { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10},
! { "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10},
! { "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10},
! { "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10},
! { "fldws", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10},
! { "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10},
! { "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10},
! { "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10},
! { "fstws", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10},
! { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10},
! { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10},
! { "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10},
! { "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10},
! { "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
! { "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10},
! { "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
! { "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10},
! { "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
! { "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10},
! { "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
! { "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10},
! { "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10},
! { "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10},
! { "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10},
! { "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10},
! { "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
! { "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10},
! { "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10},
! { "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10},
! { "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10},
! { "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10},
! { "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10},
! { "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10},
! { "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10},
! { "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10},
! { "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10},
! { "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10},
! { "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10},
! { "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10},
! { "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
! { "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
! { "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
! { "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
! { "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
! { "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
! { "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10},
! { "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10},
! { "xmpyu", 0x38004700, 0xfc00e720, "fA,fB,fT", pa11},
! { "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11},
! { "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11},
{ "ftest", 0x30002420, 0xffffffff, "", pa10},
{ "fid", 0x30000000, 0xffffffff, "", pa11},
***************
*** 599,608 ****
/* Assist Instructions */
! { "spop0", 0x10000000, 0xfc000600, "f,ON", pa10},
! { "spop1", 0x10000200, 0xfc000600, "f,oNt", pa10},
! { "spop2", 0x10000400, 0xfc000600, "f,1Nb", pa10},
! { "spop3", 0x10000600, 0xfc000600, "f,0Nx,b", pa10},
{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10},
{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10},
{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10},
--- 603,612 ----
/* Assist Instructions */
! { "spop0", 0x10000000, 0xfc000600, "v,ON", pa10},
! { "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10},
! { "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10},
! { "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10},
{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10},
{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10},
{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10},
*** gas-src/gas/config/tc-hppa.c Thu Aug 12 18:32:21 1999
--- src-prev/gas/config/tc-hppa.c Thu Aug 12 16:02:14 1999
***************
*** 1597,1603 ****
INSERT_FIELD_AND_CONTINUE (opcode, num, 16);
/* Handle a 5 bit register field at 31. */
- case 'y':
case 't':
num = pa_parse_number (&s, 0);
CHECK_FIELD (num, 31, 0, 0);
--- 1594,1599 ----
***************
*** 2825,2831 ****
INSERT_FIELD_AND_CONTINUE (opcode, num, 0);
/* Handle a 3 bit SFU identifier at 25. */
! case 'f':
if (*s++ != ',')
as_bad (_("Invalid SFU identifier"));
num = pa_get_absolute_expression (&the_insn, &s);
--- 2817,2823 ----
INSERT_FIELD_AND_CONTINUE (opcode, num, 0);
/* Handle a 3 bit SFU identifier at 25. */
! case 'v':
if (*s++ != ',')
as_bad (_("Invalid SFU identifier"));
num = pa_get_absolute_expression (&the_insn, &s);
***************
*** 2902,3131 ****
the_insn.fpof1 = flag;
INSERT_FIELD_AND_CONTINUE (opcode, flag, 11);
! /* Handle L/R register halves like 't'. */
! case 'v':
! {
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= result.number_part;
! /* 0x30 opcodes are FP arithmetic operation opcodes
! and need to be turned into 0x38 opcodes. This
! is not necessary for loads/stores. */
! if (need_pa11_opcode (&the_insn, &result)
! && ((opcode & 0xfc000000) == 0x30000000))
! opcode |= 1 << 27;
! INSERT_FIELD_AND_CONTINUE (opcode, result.l_r_select & 1, 6);
! }
! /* Handle L/R register halves like 'b'. */
! case 'E':
! {
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= result.number_part << 21;
! if (need_pa11_opcode (&the_insn, &result))
! {
! opcode |= (result.l_r_select & 1) << 7;
! opcode |= 1 << 27;
}
- continue;
- }
-
- /* Float operand 1 similar to 'b' but with l/r registers. */
- case 'J':
- {
- struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= result.number_part << 21;
! opcode |= (result.l_r_select & 1) << 7;
! continue;
! }
! /* Handle L/R register halves like 'b'. */
! case '3':
! {
! struct pa_11_fp_reg_struct result;
! int regnum;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= (result.number_part & 0x1c) << 11;
! opcode |= (result.number_part & 0x3) << 9;
! opcode |= (result.l_r_select & 1) << 8;
! continue;
! }
! /* Handle L/R register halves like 'x'. */
! case 'e':
! {
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= (result.number_part & 0x1f) << 16;
! if (need_pa11_opcode (&the_insn, &result))
{
! opcode |= (result.l_r_select & 1) << 1;
! }
! continue;
! }
! /* Handle L/R register halves like 'x'. */
! case 'X':
! {
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= (result.number_part & 0x1f) << 16;
! if (need_pa11_opcode (&the_insn, &result))
{
opcode |= (result.l_r_select & 1) << 12;
! opcode |= 1 << 27;
}
- continue;
- }
-
- /* Float operand 2, like 'x' but with l/r register halves. */
- case 'K':
- {
- struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= (result.number_part & 0x1f) << 16;
! opcode |= (result.l_r_select & 1) << 12;
! continue;
! }
! /* Handle a 5 bit register field at 10. */
! case '4':
! {
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
{
! if (result.number_part < 16)
{
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
! }
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
}
- INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 21);
- }
! /* Handle a 5 bit register field at 15. */
! case '6':
! {
! struct pa_11_fp_reg_struct result;
!
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
{
! if (result.number_part < 16)
! {
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
}
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
}
- INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 16);
- }
-
- /* Handle a 5 bit register field at 31. */
- case '7':
- {
- struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
{
! if (result.number_part < 16)
! {
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
}
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
}
- INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 0);
- }
! /* Handle a 5 bit register field at 20. */
! case '8':
! {
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
{
! if (result.number_part < 16)
! {
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
}
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
}
- INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 11);
- }
! /* Handle a 5 bit register field at 25. */
! case '9':
{
struct pa_11_fp_reg_struct result;
pa_parse_number (&s, &result);
CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
{
! if (result.number_part < 16)
! {
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
! }
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
}
! INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 6);
}
- /* Handle a floating point operand format at 26.
- Only allows single and double precision. */
- case 'H':
- flag = pa_parse_fp_format (&s);
- switch (flag)
- {
- case SGL:
- opcode |= 0x20;
- case DBL:
- the_insn.fpof1 = flag;
- continue;
-
- case QUAD:
- case ILLEGAL_FMT:
- default:
- as_bad (_("Invalid Floating Point Operand Format."));
- }
- break;
-
default:
abort ();
}
--- 2894,3138 ----
the_insn.fpof1 = flag;
INSERT_FIELD_AND_CONTINUE (opcode, flag, 11);
! /* Handle a floating point operand format at 26.
! Only allows single and double precision. */
! case 'H':
! flag = pa_parse_fp_format (&s);
! switch (flag)
! {
! case SGL:
! opcode |= 0x20;
! case DBL:
! the_insn.fpof1 = flag;
! continue;
! case QUAD:
! case ILLEGAL_FMT:
! default:
! as_bad (_("Invalid Floating Point Operand Format."));
! }
! break;
! /* Handle all floating point registers. */
! case 'f':
! switch (*++args)
! {
! /* Float target register. */
! case 't':
! num = pa_parse_number (&s, 0);
! CHECK_FIELD (num, 31, 0, 0);
! INSERT_FIELD_AND_CONTINUE (opcode, num, 0);
! /* Float target register with L/R selection. */
! case 'T':
! {
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= result.number_part;
!
! /* 0x30 opcodes are FP arithmetic operation opcodes
! and need to be turned into 0x38 opcodes. This
! is not necessary for loads/stores. */
! if (need_pa11_opcode (&the_insn, &result)
! && ((opcode & 0xfc000000) == 0x30000000))
! opcode |= 1 << 27;
! INSERT_FIELD_AND_CONTINUE (opcode, result.l_r_select & 1, 6);
}
! /* Float operand 1. */
! case 'a':
! {
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= result.number_part << 21;
! if (need_pa11_opcode (&the_insn, &result))
! {
! opcode |= (result.l_r_select & 1) << 7;
! opcode |= 1 << 27;
! }
! continue;
! }
! /* Float operand 1 with L/R selection. */
! case 'A':
! {
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= result.number_part << 21;
! opcode |= (result.l_r_select & 1) << 7;
! continue;
! }
! /* Float operand 2. */
! case 'b':
{
! struct pa_11_fp_reg_struct result;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= (result.number_part & 0x1f) << 16;
! if (need_pa11_opcode (&the_insn, &result))
! {
! opcode |= (result.l_r_select & 1) << 12;
! opcode |= 1 << 27;
! }
! continue;
! }
! /* Float operand 2 with L/R selection. */
! case 'B':
{
+ struct pa_11_fp_reg_struct result;
+
+ pa_parse_number (&s, &result);
+ CHECK_FIELD (result.number_part, 31, 0, 0);
+ opcode |= (result.number_part & 0x1f) << 16;
opcode |= (result.l_r_select & 1) << 12;
! continue;
}
! /* Float operand 3 for fmpyfadd, fmpynfadd. */
! case 'C':
! {
! struct pa_11_fp_reg_struct result;
! int regnum;
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= (result.number_part & 0x1c) << 11;
! opcode |= (result.number_part & 0x3) << 9;
! opcode |= (result.l_r_select & 1) << 8;
! continue;
! }
! /* Float mult operand 1 for fmpyadd, fmpysub */
! case 'i':
{
! struct pa_11_fp_reg_struct result;
!
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
{
! if (result.number_part < 16)
! {
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
! }
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
! }
! INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 21);
}
! /* Float mult operand 2 for fmpyadd, fmpysub */
! case 'j':
{
! struct pa_11_fp_reg_struct result;
!
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
! {
! if (result.number_part < 16)
! {
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
! }
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
}
! INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 16);
}
! /* Float mult target for fmpyadd, fmpysub */
! case 'k':
{
! struct pa_11_fp_reg_struct result;
!
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
! {
! if (result.number_part < 16)
! {
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
! }
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
}
! INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 0);
}
! /* Float add operand 1 for fmpyadd, fmpysub */
! case 'l':
! {
! struct pa_11_fp_reg_struct result;
!
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
! {
! if (result.number_part < 16)
! {
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
! }
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
! }
! INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 6);
! }
! /* Float add target for fmpyadd, fmpysub */
! case 'm':
{
! struct pa_11_fp_reg_struct result;
!
! pa_parse_number (&s, &result);
! CHECK_FIELD (result.number_part, 31, 0, 0);
! if (the_insn.fpof1 == SGL)
! {
! if (result.number_part < 16)
! {
! as_bad (_("Invalid register for single precision fmpyadd or fmpysub"));
! break;
! }
! result.number_part &= 0xF;
! result.number_part |= (result.l_r_select & 1) << 4;
}
! INSERT_FIELD_AND_CONTINUE (opcode, result.number_part, 11);
}
! default:
! abort ();
! }
! break;
!
! /* Handle L/R register halves like 'x'. */
! case 'e':
{
struct pa_11_fp_reg_struct result;
pa_parse_number (&s, &result);
CHECK_FIELD (result.number_part, 31, 0, 0);
! opcode |= (result.number_part & 0x1f) << 16;
! if (need_pa11_opcode (&the_insn, &result))
{
! opcode |= (result.l_r_select & 1) << 1;
}
! continue;
}
default:
abort ();
}
*** gas-src/opcodes/hppa-dis.c Thu Aug 12 18:32:21 1999
--- src-prev/opcodes/hppa-dis.c Wed Aug 11 18:58:37 1999
***************
*** 356,367 ****
case 'x':
fput_reg (GET_FIELD (insn, 11, 15), info);
break;
- case 'X':
- if (GET_FIELD (insn, 25, 25))
- fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
- else
- fput_fp_reg (GET_FIELD (insn, 11, 15), info);
- break;
case 'a':
case 'b':
fput_reg (GET_FIELD (insn, 6, 10), info);
--- 356,361 ----
***************
*** 369,432 ****
case '^':
fput_creg (GET_FIELD (insn, 6, 10), info);
break;
- case '!':
- fput_creg (11, info);
- break;
- case 'E':
- fput_fp_reg (GET_FIELD (insn, 6, 10), info);
- break;
case 't':
fput_reg (GET_FIELD (insn, 27, 31), info);
break;
! case 'v':
! if (GET_FIELD (insn, 25, 25))
! fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
! else
fput_fp_reg (GET_FIELD (insn, 27, 31), info);
! break;
! case 'y':
! fput_fp_reg (GET_FIELD (insn, 27, 31), info);
! break;
! case '4':
! {
! int reg = GET_FIELD (insn, 6, 10);
! reg |= (GET_FIELD (insn, 26, 26) << 4);
! fput_fp_reg (reg, info);
! break;
! }
! case '6':
! {
! int reg = GET_FIELD (insn, 11, 15);
! reg |= (GET_FIELD (insn, 26, 26) << 4);
! fput_fp_reg (reg, info);
! break;
! }
! case '7':
! {
! int reg = GET_FIELD (insn, 27, 31);
! reg |= (GET_FIELD (insn, 26, 26) << 4);
! fput_fp_reg (reg, info);
! break;
! }
! case '8':
! {
! int reg = GET_FIELD (insn, 16, 20);
! reg |= (GET_FIELD (insn, 26, 26) << 4);
! fput_fp_reg (reg, info);
! break;
! }
! case '9':
! {
! int reg = GET_FIELD (insn, 21, 25);
- reg |= (GET_FIELD (insn, 26, 26) << 4);
- fput_fp_reg (reg, info);
- break;
- }
case '5':
fput_const (extract_5_load (insn), info);
break;
--- 363,461 ----
case '^':
fput_creg (GET_FIELD (insn, 6, 10), info);
break;
case 't':
fput_reg (GET_FIELD (insn, 27, 31), info);
break;
! /* Handle floating point registers. */
! case 'f':
! switch (*++s)
! {
! case 't':
fput_fp_reg (GET_FIELD (insn, 27, 31), info);
! break;
! case 'T':
! if (GET_FIELD (insn, 25, 25))
! fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
! else
! fput_fp_reg (GET_FIELD (insn, 27, 31), info);
! break;
! case 'a':
! if (GET_FIELD (insn, 25, 25))
! fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
! else
! fput_fp_reg (GET_FIELD (insn, 6, 10), info);
! break;
! case 'A':
! if (GET_FIELD (insn, 24, 24))
! fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
! else
! fput_fp_reg (GET_FIELD (insn, 6, 10), info);
!
! break;
! case 'b':
! if (GET_FIELD (insn, 25, 25))
! fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
! else
! fput_fp_reg (GET_FIELD (insn, 11, 15), info);
! break;
! case 'B':
! if (GET_FIELD (insn, 19, 19))
! fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
! else
! fput_fp_reg (GET_FIELD (insn, 11, 15), info);
! break;
! case 'C':
! {
! int reg = GET_FIELD (insn, 21, 22);
! reg |= GET_FIELD (insn, 16, 18) << 2;
! if (GET_FIELD (insn, 23, 23) != 0)
! fput_fp_reg_r (reg, info);
! else
! fput_fp_reg (reg, info);
! break;
! }
! case 'i':
! {
! int reg = GET_FIELD (insn, 6, 10);
! reg |= (GET_FIELD (insn, 26, 26) << 4);
! fput_fp_reg (reg, info);
! break;
! }
! case 'j':
! {
! int reg = GET_FIELD (insn, 11, 15);
! reg |= (GET_FIELD (insn, 26, 26) << 4);
! fput_fp_reg (reg, info);
! break;
! }
! case 'k':
! {
! int reg = GET_FIELD (insn, 27, 31);
! reg |= (GET_FIELD (insn, 26, 26) << 4);
! fput_fp_reg (reg, info);
! break;
! }
! case 'l':
! {
! int reg = GET_FIELD (insn, 21, 25);
! reg |= (GET_FIELD (insn, 26, 26) << 4);
! fput_fp_reg (reg, info);
! break;
! }
! case 'm':
! {
! int reg = GET_FIELD (insn, 16, 20);
!
! reg |= (GET_FIELD (insn, 26, 26) << 4);
! fput_fp_reg (reg, info);
! break;
! }
! }
case '5':
fput_const (extract_5_load (insn), info);
break;
***************
*** 564,571 ****
rather than by the 'f' bit (sigh): comb, comib,
addb, addib */
case 't':
! fputs_filtered (compare_cond_names[GET_FIELD (insn, 16,
! 18)],
info);
break;
case 'T':
--- 592,598 ----
rather than by the 'f' bit (sigh): comb, comib,
addb, addib */
case 't':
! fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)],
info);
break;
case 'T':
***************
*** 585,592 ****
info);
break;
case 'n':
! fputs_filtered (compare_cond_names[GET_FIELD (insn, 16,
! 18)
+ GET_FIELD (insn, 4, 4) * 8], info);
break;
case '@':
--- 612,618 ----
info);
break;
case 'n':
! fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)
+ GET_FIELD (insn, 4, 4) * 8], info);
break;
case '@':
***************
*** 611,634 ****
break;
case 'd':
(*info->fprintf_func) (info->stream, "%s",
! add_cond_names[GET_FIELD (insn,
! 16,
! 18)]);
break;
case 'D':
(*info->fprintf_func) (info->stream, "%s",
! add_cond_names[GET_FIELD (insn,
! 16, 18)
! + 8]);
break;
case 'w':
! (*info->fprintf_func)
(info->stream, "%s",
wide_add_cond_names[GET_FIELD (insn, 16, 18)]);
break;
case 'W':
! (*info->fprintf_func)
(info->stream, "%s",
wide_add_cond_names[GET_FIELD (insn, 16, 18) + 8]);
break;
--- 637,658 ----
break;
case 'd':
(*info->fprintf_func) (info->stream, "%s",
! add_cond_names[GET_FIELD (insn, 16, 18)]);
break;
+
case 'D':
(*info->fprintf_func) (info->stream, "%s",
! add_cond_names[GET_FIELD (insn, 16, 18)
! + 8]);
break;
case 'w':
! (*info->fprintf_func)
(info->stream, "%s",
wide_add_cond_names[GET_FIELD (insn, 16, 18)]);
break;
case 'W':
! (*info->fprintf_func)
(info->stream, "%s",
wide_add_cond_names[GET_FIELD (insn, 16, 18) + 8]);
break;
***************
*** 770,776 ****
case 'D':
fput_const (GET_FIELD (insn, 6, 31), info);
break;
! case 'f':
(*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
break;
case 'O':
--- 794,800 ----
case 'D':
fput_const (GET_FIELD (insn, 6, 31), info);
break;
! case 'v':
(*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
break;
case 'O':
***************
*** 780,796 ****
case 'o':
fput_const (GET_FIELD (insn, 6, 20), info);
break;
- case '3':
- {
- int reg = GET_FIELD (insn, 21, 22);
- reg |= GET_FIELD (insn, 16, 18) << 2;
- if (GET_FIELD (insn, 23, 23) != 0)
- fput_fp_reg_r (reg, info);
- else
- fput_fp_reg (reg, info);
- break;
- }
-
case '2':
fput_const ((GET_FIELD (insn, 6, 22) << 5 |
GET_FIELD (insn, 27, 31)), info);
--- 804,809 ----
***************
*** 840,858 ****
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[GET_FIELD
(insn, 20, 20)]);
- break;
- case 'J':
- if (GET_FIELD (insn, 24, 24))
- fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
- else
- fput_fp_reg (GET_FIELD (insn, 6, 10), info);
-
- break;
- case 'K':
- if (GET_FIELD (insn, 19, 19))
- fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
- else
- fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
default:
(*info->fprintf_func) (info->stream, "%c", *s);
--- 853,858 ----