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d10v extensions
- To: binutils@sourceware.cygnus.com
- Subject: d10v extensions
- From: Diego Novillo <dnovillo@cygnus.com>
- Date: Sat, 11 Sep 1999 12:17:30 -0600 (MDT)
This patch adds 7 new instructions to gas on the d10v: ld, ld2w,
sac, sachi, slae, st and st2w. It also includes a testsuite to
verify the assembler and a minor bug fix to restrict imm3 values
to the (-2, 3) range.
-----------------------------------------------------------------------------
gas/testsuite/ChangeLog:
Wed Sep 8 19:15:08 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* gas/d10v: New directory.
* gas/d10v/d10.exp: New file.
* gas/d10v/inst.s: New file.
* gas/d10v/inst.d: New file.
gas/ChangeLog:
Wed Sep 8 19:01:12 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* config/tc-d10v.c (check_range): Check range for RESTRICTED_NUM3
operands.
include/opcode/ChangeLog:
Wed Sep 8 19:19:56 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands.
opcodes/ChangeLog:
Wed Sep 8 19:22:14 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for
rac/rachi instructions.
(d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi,
slae, st and st2w.
-----------------------------------------------------------------------------
Index: gas/config/tc-d10v.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gas/config/tc-d10v.c,v
retrieving revision 1.60
diff -p -r1.60 tc-d10v.c
*** gas/config/tc-d10v.c 1999/07/01 00:30:27 1.60
--- gas/config/tc-d10v.c 1999/09/10 20:58:08
*************** check_range (num, bits, flags)
*** 196,205 ****
if (flags & OPERAND_SIGNED)
{
! max = (1 << (bits - 1))-1;
! min = - (1 << (bits - 1));
! if (((long)num > max) || ((long)num < min))
! retval = 1;
}
else
{
--- 196,214 ----
if (flags & OPERAND_SIGNED)
{
! /* Signed 3-bit integers are restricted to the (-2, 3) range */
! if (flags & RESTRICTED_NUM3)
! {
! if ((long) num < -2 || (long) num > 3)
! retval = 1;
! }
! else
! {
! max = (1 << (bits - 1)) - 1;
! min = - (1 << (bits - 1));
! if (((long) num > max) || ((long) num < min))
! retval = 1;
! }
}
else
{
Index: gas/testsuite/gas/d10v/d10.exp
===================================================================
RCS file: d10.exp
diff -N d10.exp
*** /dev/null Mon Dec 31 20:00:00 1979
--- gas/testsuite/gas/d10v/d10.exp Fri Sep 10 13:58:08 1999
***************
*** 0 ****
--- 1,19 ----
+ #
+ # Driver for D10V assembler testsuite
+ #
+ proc run_list_test { name opts } {
+ global srcdir subdir
+ set testname "D10V $name"
+ set file $srcdir/$subdir/$name
+ gas_run ${name}.s $opts ">&dump.out"
+ if {[regexp_diff "dump.out" "${file}.l"] } {
+ fail $testname
+ verbose "output is [file_contents "dump.out"]" 2
+ return
+ }
+ pass $testname
+ }
+
+ if {[istarget d10v-*-*]} {
+ run_dump_test "inst"
+ }
Index: gas/testsuite/gas/d10v/inst.d
===================================================================
RCS file: inst.d
diff -N inst.d
*** /dev/null Mon Dec 31 20:00:00 1979
--- gas/testsuite/gas/d10v/inst.d Fri Sep 10 13:58:08 1999
***************
*** 0 ****
--- 1,22 ----
+ #objdump: -dr
+ #name: D10V basic instruction test output
+ #as:
+
+ .*: +file format elf32-d10v
+
+ Disassembly of section .text:
+
+ 00000000 <start>:
+ 0: a9 04 c2 29 sac r0, a0 <- sachi r1, a0
+ 4: a9 06 c2 2d rac r0, a0, -0x2 <- rachi r1, a0, -0x2
+ 8: 2f 00 32 26 nop || slae a0, r3
+ c: f2 11 08 00 ld r1, @0x800
+ 10: f3 01 08 00 ld2w r0, @0x800
+ 14: f7 01 08 00 st2w r0, @0x800
+ 18: f6 11 08 00 st r1, @0x800
+ 1c: 6f 00 5e 00 nop -> nop
+ 20: 6f 00 5e 00 nop -> nop
+ 24: 2f 00 5e 00 nop || nop
+ 28: af 00 5e 00 nop <- nop
+ 2c: 23 11 de 00 not r1 || nop
+ 30: 63 21 de 00 not r2 -> nop
Index: gas/testsuite/gas/d10v/inst.s
===================================================================
RCS file: inst.s
diff -N inst.s
*** /dev/null Mon Dec 31 20:00:00 1979
--- gas/testsuite/gas/d10v/inst.s Fri Sep 10 13:58:08 1999
***************
*** 0 ****
--- 1,31 ----
+ # test all instructions. FIXME: many instructions missing.
+
+ start:
+ sachi r1, a0
+ sac r0, a0
+ #
+ # disassembler test. sachi&sac should not
+ # be confused with rachi&rac
+ #
+ rachi r1, a0, -0x2
+ rac r0, a0, -0x2
+ slae a0, r3
+ ld r1, @0x0800
+ ld2w r0, @0x0800
+ st2w r0, @0x0800
+ st r1, @0x0800
+
+ # VLIW syntax test
+ nop
+ nop
+ nop -> nop
+ nop || nop
+ nop <- nop
+
+ # try changing sections
+ not r1
+ .section .foo
+ add3 r10,r12,6
+ .text
+ not r2
+ nop
Index: include/opcode/d10v.h
===================================================================
RCS file: /cvs/cvsfiles/devo/include/opcode/d10v.h,v
retrieving revision 1.9
diff -p -r1.9 d10v.h
*** include/opcode/d10v.h 1998/11/11 05:58:08 1.9
--- include/opcode/d10v.h 1999/09/10 20:58:30
*************** extern const struct d10v_operand d10v_op
*** 176,181 ****
--- 176,185 ----
/* general purpose register */
#define OPERAND_GPR (0x40000)
+ /* special imm3 values with range restricted to -2 <= imm3 <= 3 */
+ /* needed for rac/rachi */
+ #define RESTRICTED_NUM3 (0x80000)
+
/* Structure to hold information about predefined registers. */
struct pd_reg
{
Index: opcodes/d10v-opc.c
===================================================================
RCS file: /cvs/cvsfiles/devo/opcodes/d10v-opc.c,v
retrieving revision 1.17
diff -p -r1.17 d10v-opc.c
*** opcodes/d10v-opc.c 1998/09/30 17:18:37 1.17
--- opcodes/d10v-opc.c 1999/09/10 20:58:49
*************** const struct d10v_operand d10v_operands[
*** 115,121 ****
#define NUM16 (RDSTE + 1)
{ 16, 0, OPERAND_NUM|OPERAND_SIGNED },
#define NUM3 (NUM16 + 1) /* rac, rachi */
! { 3, 1, OPERAND_NUM|OPERAND_SIGNED },
#define NUM4 (NUM3 + 1)
{ 4, 1, OPERAND_NUM|OPERAND_SIGNED },
#define UNUM4 (NUM4 + 1)
--- 115,121 ----
#define NUM16 (RDSTE + 1)
{ 16, 0, OPERAND_NUM|OPERAND_SIGNED },
#define NUM3 (NUM16 + 1) /* rac, rachi */
! { 3, 1, OPERAND_NUM|OPERAND_SIGNED|RESTRICTED_NUM3 },
#define NUM4 (NUM3 + 1)
{ 4, 1, OPERAND_NUM|OPERAND_SIGNED },
#define UNUM4 (NUM4 + 1)
*************** const struct d10v_opcode d10v_opcodes[]
*** 226,235 ****
--- 226,237 ----
{ "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } },
{ "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } },
{ "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } },
+ { "ld", LONG_L, 1, MU, SEQ, 0x32010000, 0x3f0f0000, { RDST, ATSIGN, NUM16 } },
{ "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } },
{ "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } },
{ "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } },
{ "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } },
+ { "ld2w", LONG_L, 1, MU, SEQ, 0x33010000, 0x3f1f0000, { RDSTE, ATSIGN, NUM16 } },
{ "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
{ "ldb", SHORT_2, 1, MU, PAR|RMEM, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } },
{ "ldi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
*************** const struct d10v_opcode d10v_opcodes[]
*** 276,281 ****
--- 278,289 ----
{ "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } },
{ "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } },
{ "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } },
+ /* Special case. sac&sachi must occur before rac&rachi because they have
+ intersecting masks! The masks for rac&rachi will match sac&sachi but
+ not the other way around.
+ */
+ { "sac", SHORT_2, 1, IU, PAR|RF0|WF0, 0x5209, 0x7e2f, { RDSTE, ASRC } },
+ { "sachi", SHORT_2, 1, IU, PAR|RF0|WF0, 0x4209, 0x7e0f, { RDST, ASRC } },
{ "rac", SHORT_2, 1, IU, PAR|WF0, 0x5201, 0x7e21, { RDSTE, ASRC0ONLY, NUM3 } },
{ "rachi", SHORT_2, 1, IU, PAR|WF0, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } },
{ "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } },
*************** const struct d10v_opcode d10v_opcodes[]
*** 285,290 ****
--- 293,299 ----
{ "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } },
{ "setf0f", SHORT_2, 1, MU, PAR|RF0, 0x4611, 0x7e1f, { RDST } },
{ "setf0t", SHORT_2, 1, MU, PAR|RF0, 0x4613, 0x7e1f, { RDST } },
+ { "slae", SHORT_2, 1, IU, PAR, 0x3220, 0x7ee1, { ADST, RSRC } },
{ "sleep", SHORT_2, 1, MU, PAR, 0x5fc0, 0x7fff, { 0 } },
{ "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } },
{ "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } },
*************** const struct d10v_opcode d10v_opcodes[]
*** 305,315 ****
--- 314,326 ----
{ "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC } },
{ "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } },
{ "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC, MINUS } },
+ { "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } },
{ "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } },
+ { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } },
{ "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
{ "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
{ "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } },
--
Diego Novillo
GCC Engineering, Cygnus Solutions
dnovillo@cygnus.com