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Control flow implementation in assembler
- To: gcc-local at cygnus dot com
- Subject: Control flow implementation in assembler
- From: Chandra Chavva <cchavva at cygnus dot com>
- Date: Wed, 15 Mar 2000 16:43:24 -0800 (PST)
- cc: binutils at sourceware dot cygnus dot com, sce-project at cygnus dot com
Hi,
I am working on SCEI project. As per the contract, i need to implement
warning message for some sequence of instructions taking account of
control flow. Basically taking account of control flow means taking into
account branches.
For example:
In r5900 processor here is how pipeline looks for FDIV block in which
div, sqrt operations are performed.
M -> fetch insn
T -> read registers
D1 to D6 -> self time to execute DIV/SQRT insn
F -> Write back
The div/sqrt instruction write the result of operation in Q register. Any
use of this Q register within this D1 to D6 cycles, assembler needs to
give a warning message.
nop div Q, vf10x, vf11x
nop b label
nop nop
nop nop
nop nop
nop nop
nop nop
nop nop
label:
addq.x vf13x, vf14x, Q nop
nop nop
In this example, even when addq insn is 8 insns apart from div insn,
still assembler needs to give warning message because at run time the
branch insn will make addq 1 insn apart to div insn.
Since this contract is already signed we cannot say, it is not possible
to do. So please advice me how i should proceed with implementing this.
Thanks
Chandra