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Re: patch for thumb disassembler allows conditional branch-always to be disassembled
- To: tdel at windriver dot com
- Subject: Re: patch for thumb disassembler allows conditional branch-always to be disassembled
- From: Nick Clifton <nickc at cygnus dot com>
- Date: Tue, 28 Mar 2000 12:25:12 -0800
- CC: binutils at sourceware dot cygnus dot com
Hi Tom,
: The thumb branch-always conditional branch instruction 0xde00
: was not being disassembled.
:
: This patch turns it from "undefined" into "b"...
This patch is a good start, but it has a couple of problems:
* It disassembles the branch-always instruction as "b" when the
correct mnemonic is "bAL". This is important because the "b"
opcode has a different bit pattern to the "bal" opcode.
* It does not allow the branch-always instruction to be assembled.
I propose the following alternative patch, which adds the ability to
assemble the instruction, and also adds the instruction to the test
suite so that it will be check in the future.
Unless anyone objects I willl check this patch in tomorrow.
Cheers
Nick
2000-03-28 Thomas de Lellis <tdel@windriver.com>
* arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
[branch always] instead of "undefined".
Index: opcodes/arm-opc.h
===================================================================
RCS file: /cvs/src//src/opcodes/arm-opc.h,v
retrieving revision 1.2
diff -p -r1.2 arm-opc.h
*** arm-opc.h 1999/11/16 03:37:02 1.2
--- arm-opc.h 2000/03/28 20:20:17
*************** static struct thumb_opcode thumb_opcodes
*** 265,271 ****
{0xDC00, 0xFF00, "bgt\t%0-7B"},
{0xDD00, 0xFF00, "ble\t%0-7B"},
/* format 17 */
! {0xDE00, 0xFF00, "undefined"},
{0xDF00, 0xFF00, "swi\t%0-7d"},
/* format 9 */
{0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
--- 265,271 ----
{0xDC00, 0xFF00, "bgt\t%0-7B"},
{0xDD00, 0xFF00, "ble\t%0-7B"},
/* format 17 */
! {0xDE00, 0xFF00, "bal\t%0-7B"},
{0xDF00, 0xFF00, "swi\t%0-7d"},
/* format 9 */
{0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
2000-03-28 Nick Clifton <nickc@cygnus.com
* config/tc-arm.c (tinsns): Add "bal" instruction pattern.
* testsuite/gas/arm/thumb.s: Add test of bal instruction.
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src//src/gas/config/tc-arm.c,v
retrieving revision 1.38
diff -p -r1.38 tc-arm.c
*** tc-arm.c 2000/03/19 22:09:23 1.38
--- tc-arm.c 2000/03/28 20:20:18
*************** static CONST struct thumb_opcode tinsns[
*** 808,813 ****
--- 808,814 ----
{"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
{"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
{"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
+ {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
{"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
{"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
{"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
Index: gas/testsuite/gas/arm/thumb.s
===================================================================
RCS file: /cvs/src//src/gas/testsuite/gas/arm/thumb.s,v
retrieving revision 1.1.1.1
diff -p -r1.1.1.1 thumb.s
*** thumb.s 1999/05/03 07:28:48 1.1.1.1
--- thumb.s 2000/03/28 20:20:18
*************** bar:
*** 118,123 ****
--- 118,124 ----
bhi bar
blo bar
bul bar
+ bal bar
close:
lsl r4, r5, #near - close