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[PATCH] opcode support for tic54x target (NEW)
- To: binutils at sourceware dot cygnus dot com
- Subject: [PATCH] opcode support for tic54x target (NEW)
- From: Timothy Wall <twall at cygnus dot com>
- Date: Fri, 05 May 2000 09:27:13 -0400
This patch provides opcodes support for the tic54x target.
T.
? opcodes/sw-diff.txt
? opcodes/ChangeLog.tic54x
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.121
diff -d -c -p -b -w -r1.121 ChangeLog
*** ChangeLog 2000/05/03 22:25:08 1.121
--- ChangeLog 2000/05/05 13:19:10
***************
*** 1,3 ****
--- 1,13 ----
+ 2000-05-04 Timothy Wall <twall@cygnus.com>
+
+ * tic54x-opc.c: New.
+ * tic54x-dis.c: New.
+ * disassemble.c (disassembler): Add ARCH_tic54x.
+ * configure.in: Added tic54x target.
+ * configure: Ditto.
+ * Makefile.am: Add tic54x dependencies.
+ * Makefile.in: Ditto.
+
2000-05-03 J.T. Conklin <jtc@redback.com>
* ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
Index: opcodes/Makefile.am
===================================================================
RCS file: /cvs/src/src/opcodes/Makefile.am,v
retrieving revision 1.12
diff -d -c -p -b -w -r1.12 Makefile.am
*** Makefile.am 2000/04/21 20:22:23 1.12
--- Makefile.am 2000/05/05 13:19:10
*************** CFILES = \
*** 96,101 ****
--- 96,103 ----
sparc-dis.c \
sparc-opc.c \
tic30-dis.c \
+ tic54x-dis.c \
+ tic54x-opc.c \
tic80-dis.c \
tic80-opc.c \
v850-dis.c \
*************** ALL_MACHINES = \
*** 160,165 ****
--- 162,169 ----
sparc-dis.lo \
sparc-opc.lo \
tic30-dis.lo \
+ tic54x-dis.lo \
+ tic54x-opc.lo \
tic80-dis.lo \
tic80-opc.lo \
v850-dis.lo \
*************** m10300-opc.lo: m10300-opc.c sysdep.h con
*** 399,404 ****
--- 403,415 ----
ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \
opintl.h
+ pj-dis.lo: pj-dis.c $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h
+ pj-opc.lo: pj-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/pj.h
+ ppc-dis.lo: ppc-dis.c $(INCDIR)/ansidecl.h sysdep.h \
+ config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ppc.h
+ ppc-opc.lo: ppc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/ppc.h \
+ opintl.h
pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H)
pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
*************** sparc-opc.lo: sparc-opc.c sysdep.h confi
*** 416,421 ****
--- 427,436 ----
$(INCDIR)/opcode/sparc.h
tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic30.h
+ tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic54x.h
+ tic54x-opc.lo: tic54x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/opcode/tic54x.h
tic80-dis.lo: tic80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H)
tic80-opc.lo: tic80-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
Index: opcodes/Makefile.in
===================================================================
RCS file: /cvs/src/src/opcodes/Makefile.in,v
retrieving revision 1.14
diff -d -c -p -b -w -r1.14 Makefile.in
*** Makefile.in 2000/04/21 20:22:23 1.14
--- Makefile.in 2000/05/05 13:19:10
*************** CFILES = \
*** 200,205 ****
--- 200,207 ----
sparc-dis.c \
sparc-opc.c \
tic30-dis.c \
+ tic54x-dis.c \
+ tic54x-opc.c \
tic80-dis.c \
tic80-opc.c \
v850-dis.c \
*************** ALL_MACHINES = \
*** 265,270 ****
--- 267,274 ----
sparc-dis.lo \
sparc-opc.lo \
tic30-dis.lo \
+ tic54x-dis.lo \
+ tic54x-opc.lo \
tic80-dis.lo \
tic80-opc.lo \
v850-dis.lo \
*************** m10300-opc.lo: m10300-opc.c sysdep.h con
*** 896,901 ****
--- 900,912 ----
ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \
opintl.h
+ pj-dis.lo: pj-dis.c $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h
+ pj-opc.lo: pj-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/pj.h
+ ppc-dis.lo: ppc-dis.c $(INCDIR)/ansidecl.h sysdep.h \
+ config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ppc.h
+ ppc-opc.lo: ppc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/ppc.h \
+ opintl.h
pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H)
pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
*************** sparc-opc.lo: sparc-opc.c sysdep.h confi
*** 913,918 ****
--- 924,933 ----
$(INCDIR)/opcode/sparc.h
tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic30.h
+ tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic54x.h
+ tic54x-opc.lo: tic54x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/opcode/tic54x.h
tic80-dis.lo: tic80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H)
tic80-opc.lo: tic80-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
Index: opcodes/configure
===================================================================
RCS file: /cvs/src/src/opcodes/configure,v
retrieving revision 1.9
diff -d -c -p -b -w -r1.9 configure
*** configure 2000/04/26 15:09:44 1.9
--- configure 2000/05/05 13:19:11
*************** if test x${all_targets} = xfalse ; then
*** 3963,3968 ****
--- 3963,3969 ----
bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;;
bfd_tahoe_arch) ;;
bfd_tic30_arch) ta="$ta tic30-dis.lo" ;;
+ bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;;
bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;;
bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;;
bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;;
Index: opcodes/configure.in
===================================================================
RCS file: /cvs/src/src/opcodes/configure.in,v
retrieving revision 1.8
diff -d -c -p -b -w -r1.8 configure.in
*** configure.in 2000/04/26 15:09:44 1.8
--- configure.in 2000/05/05 13:19:11
*************** if test x${all_targets} = xfalse ; then
*** 185,190 ****
--- 185,191 ----
bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;;
bfd_tahoe_arch) ;;
bfd_tic30_arch) ta="$ta tic30-dis.lo" ;;
+ bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;;
bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;;
bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;;
bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;;
Index: opcodes/disassemble.c
===================================================================
RCS file: /cvs/src/src/opcodes/disassemble.c,v
retrieving revision 1.11
diff -d -c -p -b -w -r1.11 disassemble.c
*** disassemble.c 2000/04/26 15:09:44 1.11
--- disassemble.c 2000/05/05 13:19:11
*************** Foundation, Inc., 59 Temple Place - Suit
*** 49,54 ****
--- 49,55 ----
#define ARCH_sh
#define ARCH_sparc
#define ARCH_tic30
+ #define ARCH_tic54x
#define ARCH_tic80
#define ARCH_v850
#define ARCH_vax
*************** disassembler (abfd)
*** 238,243 ****
--- 239,249 ----
#ifdef ARCH_tic30
case bfd_arch_tic30:
disassemble = print_insn_tic30;
+ break;
+ #endif
+ #ifdef ARCH_tic54x
+ case bfd_arch_tic54x:
+ disassemble = print_insn_tic54x;
break;
#endif
#ifdef ARCH_tic80
Index: opcodes/tic54x-dis.c
===================================================================
RCS file: tic54x-dis.c
diff -N tic54x-dis.c
*** /dev/null Tue May 5 13:32:27 1998
--- tic54x-dis.c Fri May 5 06:19:11 2000
***************
*** 0 ****
--- 1,615 ----
+ /* Disassembly routines for TMS320C54X architecture
+ Copyright (C) 1999,2000 Free Software Foundation, Inc.
+ Contributed by Timothy Wall (twall@cygnus.com)
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+ #include <errno.h>
+ #include <math.h>
+ #include <stdlib.h>
+ #include <string.h>
+ #include "dis-asm.h"
+ #include "opcode/tic54x.h"
+ #include "coff/tic54x.h"
+
+ typedef struct _instruction {
+ int parallel;
+ template *tm;
+ partemplate *ptm;
+ } instruction;
+
+ static int get_insn_size PARAMS ((unsigned short, instruction *));
+ static int get_instruction PARAMS ((disassemble_info *, bfd_vma,
+ unsigned short, instruction *));
+ static int print_instruction PARAMS ((disassemble_info *, bfd_vma,
+ unsigned short, char *,
+ enum optype [], int, int));
+ static int print_parallel_instruction PARAMS ((disassemble_info *, bfd_vma,
+ unsigned short, partemplate *,
+ int));
+ static int sprint_dual_address (disassemble_info *,char [],
+ unsigned short);
+ static int sprint_indirect_address (disassemble_info *,char [],
+ unsigned short);
+ static int sprint_direct_address (disassemble_info *,char [],
+ unsigned short);
+ static int sprint_mmr (disassemble_info *,char [],int);
+ static int sprint_condition (disassemble_info *,char *,unsigned short);
+ static int sprint_cc2 (disassemble_info *,char *,unsigned short);
+
+ int
+ print_insn_tic54x(memaddr, info)
+ bfd_vma memaddr;
+ disassemble_info *info;
+ {
+ bfd_byte opbuf[2];
+ unsigned short opcode;
+ int status, size;
+ instruction insn;
+
+ status = (*info->read_memory_func) (memaddr, opbuf, 2, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func)(status, memaddr, info);
+ return -1;
+ }
+
+ opcode = bfd_getl16(opbuf);
+ if (!get_instruction (info, memaddr, opcode, &insn))
+ return -1;
+
+ size = get_insn_size (opcode, &insn);
+ info->bytes_per_line = 2;
+ info->bytes_per_chunk = 2;
+ info->octets_per_byte = 2;
+ info->display_endian = BFD_ENDIAN_LITTLE;
+
+ if (insn.parallel)
+ {
+ if (!print_parallel_instruction (info, memaddr, opcode, insn.ptm, size))
+ return -1;
+ }
+ else
+ {
+ if (!print_instruction (info, memaddr, opcode,
+ (char *)insn.tm->name,
+ insn.tm->operand_types,
+ size, (insn.tm->flags & FL_EXT)))
+ return -1;
+ }
+
+ return size*2;
+ }
+
+ static int
+ has_lkaddr(opcode, tm)
+ unsigned short opcode;
+ template *tm;
+ {
+ return IS_LKADDR(opcode) &&
+ (OPTYPE(tm->operand_types[0]) == OP_Smem ||
+ OPTYPE(tm->operand_types[1]) == OP_Smem ||
+ OPTYPE(tm->operand_types[2]) == OP_Smem ||
+ OPTYPE(tm->operand_types[1]) == OP_Sind);
+ }
+
+ /* always returns 1 (whether an insn template was found) since we provide an
+ "unknown instruction" template */
+ static int
+ get_instruction (info, addr, opcode, insn)
+ disassemble_info *info;
+ bfd_vma addr;
+ unsigned short opcode;
+ instruction *insn;
+ {
+ template * tm;
+ partemplate * ptm;
+
+ insn->parallel = 0;
+ for (tm = (template *)tic54x_optab; tm->name; tm++)
+ {
+ if (tm->opcode == (opcode & tm->mask))
+ {
+ /* a few opcodes span two words */
+ if (tm->flags & FL_EXT)
+ {
+ /* if lk addressing is used, the second half of the opcode gets
+ pushed one word later */
+ bfd_byte opbuf[2];
+ bfd_vma addr2 = addr + 1 + has_lkaddr(opcode, tm);
+ int status = (*info->read_memory_func)(addr2, opbuf, 2, info);
+ if (status == 0)
+ {
+ unsigned short opcode2 = bfd_getl16(opbuf);
+ if (tm->opcode2 == (opcode2 & tm->mask2))
+ {
+ insn->tm = tm;
+ return 1;
+ }
+ }
+ }
+ else
+ {
+ insn->tm = tm;
+ return 1;
+ }
+ }
+ }
+ for (ptm = (partemplate *)tic54x_paroptab; ptm->name; ptm++)
+ {
+ if (ptm->opcode == (opcode & ptm->mask))
+ {
+ insn->parallel = 1;
+ insn->ptm = ptm;
+ return 1;
+ }
+ }
+
+ insn->tm = (template *)&tic54x_unknown_opcode;
+ return 1;
+ }
+
+ static int
+ get_insn_size (opcode, insn)
+ unsigned short opcode;
+ instruction *insn;
+ {
+ int size;
+
+ if (insn->parallel)
+ {
+ /* only non-parallel instructions support lk addressing */
+ size = insn->ptm->words;
+ }
+ else
+ {
+ size = insn->tm->words + has_lkaddr(opcode, insn->tm);
+ }
+
+ return size;
+ }
+
+ int
+ print_instruction (info, memaddr, opcode, tm_name, tm_operands, size, ext)
+ disassemble_info *info;
+ bfd_vma memaddr;
+ unsigned short opcode;
+ char *tm_name;
+ enum optype tm_operands[];
+ int size;
+ int ext;
+ {
+ static int n;
+ /* string storage for multiple operands */
+ char operand[4][64] = { {0},{0},{0},{0}, };
+ bfd_byte buf[2];
+ unsigned long opcode2, lkaddr;
+ enum optype src = OP_None;
+ enum optype dst = OP_None;
+ int i, shift;
+ char *comma = "";
+
+ info->fprintf_func (info->stream, "%-7s", tm_name);
+
+ if (size > 1)
+ {
+ int status = (*info->read_memory_func) (memaddr+1, buf, 2, info);
+ if (status != 0)
+ return 0;
+ lkaddr = opcode2 = bfd_getl16(buf);
+ if (size > 2)
+ {
+ status = (*info->read_memory_func) (memaddr+2, buf, 2, info);
+ if (status != 0)
+ return 0;
+ opcode2 = bfd_getl16(buf);
+ }
+ }
+
+ for (i=0;i < MAX_OPERANDS && OPTYPE(tm_operands[i]) != OP_None;i++)
+ {
+ char *next_comma = ",";
+ int optional = (tm_operands[i] & OPT) != 0;
+
+ switch (OPTYPE(tm_operands[i]))
+ {
+ case OP_Xmem:
+ sprint_dual_address (info, operand[i], XMEM(opcode));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_Ymem:
+ sprint_dual_address (info, operand[i], YMEM(opcode));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_Smem:
+ case OP_Sind:
+ case OP_Lmem:
+ info->fprintf_func (info->stream, "%s", comma);
+ if (INDIRECT(opcode))
+ {
+ if (MOD(opcode) >= 12)
+ {
+ bfd_vma addr = lkaddr;
+ int arf = ARF(opcode);
+ int mod = MOD(opcode);
+ if (mod == 15)
+ info->fprintf_func (info->stream, "*(");
+ else
+ info->fprintf_func (info->stream, "*%sar%d(",
+ (mod == 13 || mod == 14 ? "+" : ""),
+ arf);
+ (*(info->print_address_func))((bfd_vma)addr, info);
+ info->fprintf_func (info->stream, ")%s",
+ mod == 14 ? "%" : "");
+ }
+ else
+ {
+ sprint_indirect_address (info, operand[i], opcode);
+ info->fprintf_func (info->stream, "%s", operand[i]);
+ }
+ }
+ else
+ {
+ /* FIXME -- use labels (print_address_func) */
+ /* in order to do this, we need to guess what DP is */
+ sprint_direct_address (info, operand[i], opcode);
+ info->fprintf_func (info->stream, "%s", operand[i]);
+ }
+ break;
+ case OP_dmad:
+ info->fprintf_func (info->stream, "%s", comma);
+ (*(info->print_address_func))((bfd_vma)opcode2, info);
+ break;
+ case OP_xpmad:
+ /* upper 7 bits of address are in the opcode */
+ opcode2 += ((unsigned long)opcode & 0x7F) << 16;
+ /* fall through */
+ case OP_pmad:
+ info->fprintf_func (info->stream, "%s", comma);
+ (*(info->print_address_func))((bfd_vma)opcode2, info);
+ break;
+ case OP_MMRX:
+ sprint_mmr (info, operand[i], MMRX(opcode));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_MMRY:
+ sprint_mmr (info, operand[i], MMRY(opcode));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_MMR:
+ sprint_mmr (info, operand[i], MMR(opcode));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_PA:
+ sprintf (operand[i], "pa%d", (unsigned)opcode2);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_SRC:
+ src = SRC(ext ? opcode2 : opcode) ? OP_B : OP_A;
+ sprintf (operand[i], (src == OP_B) ? "b" : "a");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_SRC1:
+ src = SRC1(ext ? opcode2 : opcode) ? OP_B : OP_A;
+ sprintf (operand[i], (src == OP_B) ? "b" : "a");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_RND:
+ dst = DST(opcode) ? OP_B : OP_A;
+ sprintf (operand[i], (dst == OP_B) ? "a" : "b");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_DST:
+ dst = DST(ext ? opcode2 : opcode) ? OP_B : OP_A;
+ if (!optional || dst != src)
+ {
+ sprintf (operand[i], (dst == OP_B) ? "b" : "a");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ }
+ else
+ next_comma = comma;
+ break;
+ case OP_B:
+ sprintf (operand[i], "b");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_A:
+ sprintf (operand[i], "a");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_ARX:
+ sprintf (operand[i],"ar%d", (int)ARX(opcode));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_SHIFT:
+ shift = SHIFT(ext ? opcode2 : opcode);
+ if (!optional || shift != 0)
+ {
+ sprintf (operand[i],"%d", shift);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ }
+ else
+ next_comma = comma;
+ break;
+ case OP_SHFT:
+ shift = SHFT(opcode);
+ if (!optional || shift != 0)
+ {
+ sprintf (operand[i],"%d", (unsigned)shift);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ }
+ else
+ next_comma = comma;
+ break;
+ case OP_lk:
+ sprintf (operand[i],"#%d", (int)(short)opcode2);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_T:
+ sprintf (operand[i], "t");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_TS:
+ sprintf (operand[i], "ts");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_k8:
+ sprintf (operand[i], "%d", (int)((signed char)(opcode & 0xFF)));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_16:
+ sprintf (operand[i], "16");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_ASM:
+ sprintf (operand[i], "asm");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_BITC:
+ sprintf (operand[i], "%d", (int)(opcode & 0xF));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_CC:
+ /* put all CC operands in the same operand */
+ sprint_condition (info, operand[i], opcode);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ i = MAX_OPERANDS;
+ break;
+ case OP_CC2:
+ sprint_cc2 (info, operand[i], opcode);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_CC3:
+ {
+ const char *code[] = { "eq", "lt", "gt", "neq" };
+ sprintf (operand[i], code[CC3(opcode)]);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ }
+ case OP_123:
+ {
+ int code = (opcode>>8) & 0x3;
+ sprintf (operand[i], "%d", (code == 0) ? 1 : (code == 2) ? 2 : 3);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ }
+ case OP_k5:
+ sprintf (operand[i], "#%d",
+ (int)(((signed char)opcode & 0x1F) << 3)>>3);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_k8u:
+ sprintf (operand[i], "#%d", (unsigned)(opcode & 0xFF));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_k3:
+ sprintf (operand[i], "#%d", (int)(opcode & 0x7));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_lku:
+ sprintf (operand[i], "#%d", (unsigned)opcode2);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_N:
+ n = (opcode >> 9) & 0x1;
+ sprintf (operand[i], "st%d", n);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_SBIT:
+ {
+ const char *status0[] = {
+ "0", "1", "2", "3", "4", "5", "6", "7", "8",
+ "ovb", "ova", "c", "tc", "13", "14", "15"
+ };
+ const char *status1[] = {
+ "0", "1", "2", "3", "4",
+ "cmpt", "frct", "c16", "sxm", "ovm", "10",
+ "intm", "hm", "xf", "cpl", "braf"
+ };
+ sprintf (operand[i], "%s",
+ n ? status1[SBIT(opcode)] : status0[SBIT(opcode)]);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ }
+ case OP_12:
+ sprintf (operand[i], "%d", (int)((opcode >> 9)&1) + 1);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_TRN:
+ sprintf (operand[i], "trn");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_DP:
+ sprintf (operand[i], "dp");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_k9:
+ /* FIXME-- this is DP, print the original address? */
+ sprintf (operand[i], "#%d", (int)(opcode & 0x1FF));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_ARP:
+ sprintf (operand[i], "arp");
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ case OP_031:
+ sprintf (operand[i], "%d", (int)(opcode & 0x1F));
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ default:
+ sprintf (operand[i], "??? (0x%x)", tm_operands[i]);
+ info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
+ break;
+ }
+ comma = next_comma;
+ }
+ return 1;
+ }
+
+ static int
+ print_parallel_instruction (info, memaddr, opcode, ptm, size)
+ disassemble_info *info;
+ bfd_vma memaddr;
+ unsigned short opcode;
+ partemplate *ptm;
+ int size;
+ {
+ print_instruction (info, memaddr, opcode,
+ ptm->name, ptm->operand_types, size, 0);
+ info->fprintf_func (info->stream, " || ");
+ return print_instruction (info, memaddr, opcode,
+ ptm->parname, ptm->paroperand_types, size, 0);
+ }
+
+ static int
+ sprint_dual_address (info, buf, code)
+ disassemble_info *info;
+ char buf[];
+ unsigned short code;
+ {
+ const char *formats[] = {
+ "*ar%d",
+ "*ar%d-",
+ "*ar%d+",
+ "*ar%d+0%%",
+ };
+ return sprintf (buf, formats[XMOD(code)], XARX(code));
+ }
+
+ static int
+ sprint_indirect_address (info, buf, opcode)
+ disassemble_info *info;
+ char buf[];
+ unsigned short opcode;
+ {
+ const char *formats[] = {
+ "*ar%d",
+ "*ar%d-",
+ "*ar%d+",
+ "*+ar%d",
+ "*ar%d-0B",
+ "*ar%d-0",
+ "*ar%d+0",
+ "*ar%d+0B",
+ "*ar%d-%%",
+ "*ar%d-0%%",
+ "*ar%d+%%",
+ "*ar%d+0%%",
+ };
+ return sprintf (buf, formats[MOD(opcode)], ARF(opcode));
+ }
+
+ static int
+ sprint_direct_address (info, buf, opcode)
+ disassemble_info *info;
+ char buf[];
+ unsigned short opcode;
+ {
+ /* FIXME -- look up relocation if available */
+ return sprintf (buf, "0x??%02x", (int)(opcode & 0x7F));
+ }
+
+ static int
+ sprint_mmr (info, buf, mmr)
+ disassemble_info *info;
+ char buf[];
+ int mmr;
+ {
+ symbol *reg = (symbol *)mmregs;
+ while (reg->name != NULL)
+ {
+ if (mmr == reg->value)
+ {
+ sprintf (buf, "%s", (reg+1)->name);
+ return 1;
+ }
+ ++reg;
+ }
+ sprintf (buf, "MMR(%d)", mmr); // FIXME -- different targets
+ return 0;
+ }
+
+ static int
+ sprint_cc2 (info, buf, opcode)
+ disassemble_info *info;
+ char *buf;
+ unsigned short opcode;
+ {
+ const char *cc2[] = {
+ "??", "??", "ageq", "alt", "aneq", "aeq", "agt", "aleq",
+ "??", "??", "bgeq", "blt", "bneq", "beq", "bgt", "bleq",
+ };
+ return sprintf (buf, "%s", cc2[opcode & 0xF]);
+ }
+
+ static int
+ sprint_condition (info, buf, opcode)
+ disassemble_info *info;
+ char *buf;
+ unsigned short opcode;
+ {
+ char *start = buf;
+ const char *cmp[] = {
+ "??", "??", "geq", "lt", "neq", "eq", "gt", "leq"
+ };
+ if (opcode & 0x40)
+ {
+ char acc = (opcode & 0x8) ? 'b' : 'a';
+ if (opcode & 0x7)
+ buf += sprintf (buf, "%c%s%s", acc, cmp[(opcode&0x7)],
+ (opcode&0x20) ? ", " : "");
+ if (opcode & 0x20)
+ buf += sprintf (buf, "%c%s", acc, (opcode&0x10) ? "ov" : "nov");
+ }
+ else if (opcode & 0x3F)
+ {
+ if (opcode & 0x30)
+ buf += sprintf (buf, "%s%s",
+ ((opcode & 0x30) == 0x30) ? "tc" : "ntc",
+ (opcode & 0x0F) ? ", " : "");
+ if (opcode & 0x0C)
+ buf += sprintf (buf, "%s%s",
+ ((opcode & 0x0C) == 0x0C) ? "c" : "nc",
+ (opcode & 0x03) ? ", " : "");
+ if (opcode & 0x03)
+ buf += sprintf (buf, "%s",
+ ((opcode & 0x03) == 0x03) ? "bio" : "nbio");
+ }
+ else
+ buf += sprintf (buf, "unc");
+
+ return buf - start;
+ }
Index: opcodes/tic54x-opc.c
===================================================================
RCS file: tic54x-opc.c
diff -N tic54x-opc.c
*** /dev/null Tue May 5 13:32:27 1998
--- tic54x-opc.c Fri May 5 06:19:11 2000
***************
*** 0 ****
--- 1,477 ----
+ /* Table of opcodes for the Texas Instruments TMS320C54X
+ Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+ Contributed by Timothy Wall (twall@cygnus.com)
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+ #include <stdio.h>
+ #include "ansidecl.h"
+ #include "opcode/tic54x.h"
+
+ /* these are the only register names not found in mmregs */
+ const symbol regs[] = {
+ { "AR0", 16 }, { "ar0", 16 },
+ { "AR1", 17 }, { "ar1", 17 },
+ { "AR2", 18 }, { "ar2", 18 },
+ { "AR3", 19 }, { "ar3", 19 },
+ { "AR4", 20 }, { "ar4", 20 },
+ { "AR5", 21 }, { "ar5", 21 },
+ { "AR6", 22 }, { "ar6", 22 },
+ { "AR7", 23 }, { "ar7", 23 },
+ { NULL, }
+ };
+
+ /* status bits, MM registers, condition codes, etc */
+ /* some symbols are only valid for certain chips... */
+ const symbol mmregs[] = {
+ { "IMR", 0 }, { "imr", 0 },
+ { "IFR", 1 }, { "ifr", 1 },
+ { "ST0", 6 }, { "st0", 6 },
+ { "ST1", 7 }, { "st1", 7 },
+ { "AL", 8 }, { "al", 8 },
+ { "AH", 9 }, { "ah", 9 },
+ { "AG", 10 }, { "ag", 10 },
+ { "BL", 11 }, { "bl", 11 },
+ { "BH", 12 }, { "bh", 12 },
+ { "BG", 13 }, { "bg", 13 },
+ { "T", 14 }, { "t", 14 },
+ { "TRN", 15 }, { "trn", 15 },
+ { "AR0", 16 }, { "ar0", 16 },
+ { "AR1", 17 }, { "ar1", 17 },
+ { "AR2", 18 }, { "ar2", 18 },
+ { "AR3", 19 }, { "ar3", 19 },
+ { "AR4", 20 }, { "ar4", 20 },
+ { "AR5", 21 }, { "ar5", 21 },
+ { "AR6", 22 }, { "ar6", 22 },
+ { "AR7", 23 }, { "ar7", 23 },
+ { "SP", 24 }, { "sp", 24 },
+ { "BK", 25 }, { "bk", 25 },
+ { "BRC", 26 }, { "brc", 26 },
+ { "RSA", 27 }, { "rsa", 27 },
+ { "REA", 28 }, { "rea", 28 },
+ { "PMST",29 }, { "pmst",29 },
+ { "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */
+ /* optional peripherals */ /* optional peripherals */
+ { "M1F", 31 }, { "m1f", 31 },
+ { "DRR0",0x20 }, { "drr0",0x20 },
+ { "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */
+ { "DXR0",0x21 }, { "dxr0",0x21 },
+ { "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */
+ { "SPC0",0x22 }, { "spc0",0x22 },
+ { "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */
+ { "SPCE0",0x23 }, { "spce0",0x23 },
+ { "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */
+ { "TIM", 0x24 }, { "tim", 0x24 },
+ { "PRD", 0x25 }, { "prd", 0x25 },
+ { "TCR", 0x26 }, { "tcr", 0x26 },
+ { "SWWSR",0x28 }, { "swwsr",0x28 },
+ { "BSCR",0x29 }, { "bscr",0x29 },
+ { "HPIC",0x2C }, { "hpic",0x2c },
+ /* 'c541, 'c545 */ /* 'c541, 'c545 */
+ { "DRR1",0x30 }, { "drr1",0x30 },
+ { "DXR1",0x31 }, { "dxr1",0x31 },
+ { "SPC1",0x32 }, { "spc1",0x32 },
+ /* 'c542, 'c543 */ /* 'c542, 'c543 */
+ { "TRCV",0x30 }, { "trcv",0x30 },
+ { "TDXR",0x31 }, { "tdxr",0x31 },
+ { "TSPC",0x32 }, { "tspc",0x32 },
+ { "TCSR",0x33 }, { "tcsr",0x33 },
+ { "TRTA",0x34 }, { "trta",0x34 },
+ { "TRAD",0x35 }, { "trad",0x35 },
+ { "AXR0",0x38 }, { "axr0",0x38 },
+ { "BKX0",0x39 }, { "bkx0",0x39 },
+ { "ARR0",0x3A }, { "arr0",0x3a },
+ { "BKR0",0x3B }, { "bkr0",0x3b },
+ /* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */
+ { "CLKMD",0x58 }, { "clkmd",0x58 },
+ /* 'c548 */ /* 'c548 */
+ { "AXR1",0x3C }, { "axr1",0x3c },
+ { "BKX1",0x3D }, { "bkx1",0x3d },
+ { "ARR1",0x3E }, { "arr1",0x3e },
+ { "BKR1",0x3F }, { "bkr1",0x3f },
+ { "BDRR1",0x40 }, { "bdrr1",0x40 },
+ { "BDXR1",0x41 }, { "bdxr1",0x41 },
+ { "BSPC1",0x42 }, { "bspc1",0x42 },
+ { "BSPCE1",0x43 }, { "bspce1",0x43 },
+ { NULL },
+ };
+
+ const symbol condition_codes[] = {
+ /* condition codes */
+ { "UNC", 0 }, { "unc", 0 },
+ #define CC1 0x40
+ #define CCB 0x08
+ #define CCEQ 0x05
+ #define CCNEQ 0x04
+ #define CCLT 0x03
+ #define CCLEQ 0x07
+ #define CCGT 0x06
+ #define CCGEQ 0x02
+ #define CCOV 0x70
+ #define CCNOV 0x60
+ #define CCBIO 0x03
+ #define CCNBIO 0x02
+ #define CCTC 0x30
+ #define CCNTC 0x20
+ #define CCC 0x0C
+ #define CCNC 0x08
+ { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ },
+ { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ },
+ { "alt", CC1|CCLT }, { "ALT", CC1|CCLT },
+ { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ },
+ { "agt", CC1|CCGT }, { "AGT", CC1|CCGT },
+ { "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ },
+ { "aov", CC1|CCOV }, { "AOV", CC1|CCOV },
+ { "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV },
+ { "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ },
+ { "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ },
+ { "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT },
+ { "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ },
+ { "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT },
+ { "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ },
+ { "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV },
+ { "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV },
+ { "tc", CCTC }, { "TC", CCTC },
+ { "ntc", CCNTC }, { "NTC", CCNTC },
+ { "c", CCC }, { "C", CCC },
+ { "nc", CCNC }, { "NC", CCNC },
+ { "bio", CCBIO }, { "BIO", CCBIO },
+ { "nbio", CCNBIO }, { "NBIO", CCNBIO },
+ { NULL, }
+ };
+
+ const symbol cc2_codes[] = {
+ { "UNC", 0 }, { "unc", 0 },
+ { "AEQ", 5 }, { "aeq", 5 },
+ { "ANEQ", 4 }, { "aneq", 4 },
+ { "AGT", 6 }, { "agt", 6 },
+ { "ALT", 3 }, { "alt", 3 },
+ { "ALEQ", 7 }, { "aleq", 7 },
+ { "AGEQ", 2 }, { "ageq", 2 },
+ { "BEQ", 13 }, { "beq", 13 },
+ { "BNEQ", 12 },{ "bneq", 12 },
+ { "BGT", 14 }, { "bgt", 14 },
+ { "BLT", 11 }, { "blt", 11 },
+ { "BLEQ", 15 },{ "bleq", 15 },
+ { "BGEQ", 10 },{ "bgeq", 10 },
+ { NULL },
+ };
+
+ const symbol cc3_codes[] = {
+ { "EQ", 0x0000 }, { "eq", 0x0000 },
+ { "LT", 0x0100 }, { "lt", 0x0100 },
+ { "GT", 0x0200 }, { "gt", 0x0200 },
+ { "NEQ", 0x0300 }, { "neq", 0x0300 },
+ { "0", 0x0000 },
+ { "1", 0x0100 },
+ { "2", 0x0200 },
+ { "3", 0x0300 },
+ { "00", 0x0000 },
+ { "01", 0x0100 },
+ { "10", 0x0200 },
+ { "11", 0x0300 },
+ { NULL },
+ };
+
+ /* FIXME -- also allow decimal digits */
+ const symbol status_bits[] = {
+ /* status register 0 */
+ { "TC", 12 }, { "tc", 12 },
+ { "C", 11 }, { "c", 11 },
+ { "OVA", 10 }, { "ova", 10 },
+ { "OVB", 9 }, { "ovb", 9 },
+ /* status register 1 */
+ { "BRAF",15 }, { "braf",15 },
+ { "CPL", 14 }, { "cpl", 14 },
+ { "XF", 13 }, { "xf", 13 },
+ { "HM", 12 }, { "hm", 12 },
+ { "INTM",11 }, { "intm",11 },
+ { "OVM", 9 }, { "ovm", 9 },
+ { "SXM", 8 }, { "sxm", 8 },
+ { "C16", 7 }, { "c16", 7 },
+ { "FRCT", 6 }, { "frct", 6 },
+ { "CMPT", 5 }, { "cmpt", 5 },
+ { NULL },
+ };
+
+ const char *misc_symbols[] = {
+ "ARP", "arp",
+ "DP", "dp",
+ "ASM", "asm",
+ "TS", "ts",
+ NULL
+ };
+
+ /* Due to the way instructions are hashed and scanned in
+ gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively
+ placed
+
+ Items marked with "PREFER" have been moved prior to a more costly
+ instruction with a similar operand format.
+
+ Mnemonics which can take either a predefined symbol or a memory reference
+ as an argument are arranged so that the more restrictive (predefined
+ symbol) version is checked first (marked "SRC").
+ */
+ const template tic54x_unknown_opcode =
+ { "???", 1,0,0,0x0000, 0x0000, {0}, };
+ const template tic54x_optab[] = {
+ /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */
+ { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, },
+ { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, },
+ { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, },
+ { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, },
+
+ { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, },
+ { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, },
+ { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/
+ { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/
+ { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR },
+ { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR},
+ { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, },/*PREFER*/
+ { "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
+ FL_EXT|FL_SMR, 0x0C00, 0xFCE0},
+ { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, },
+ { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, },
+ { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, },
+ { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, },
+ { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },
+ { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, },
+ { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, },
+ { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, },
+ { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, },
+ { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, },
+ { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, },
+ { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, },
+ { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, },
+ { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, },
+ { "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
+ B_BRANCH|FL_NR, },
+ { "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
+ B_BRANCH|FL_DELAY|FL_NR, },
+ { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, },
+ { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR },
+ { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR },
+ { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, },
+ { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, },
+ { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, },
+ { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, },
+ { "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
+ B_BRANCH|FL_NR, },
+ { "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
+ B_BRANCH|FL_DELAY|FL_NR, },
+ { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, },
+ { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR },
+ { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, },
+ { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, },
+ { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, },
+ { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, },
+ { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR },
+ { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, },
+ { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, },
+ { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, },
+ { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, },
+ { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, },
+ { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, },
+ { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, },
+ { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, },
+ { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, },
+ { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, },
+ { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, },
+ { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, },
+ { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, },
+ { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, },
+ { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, },
+ { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, },
+ { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, },
+ { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, },
+ { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, },
+ { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/
+ { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, },/*SRC*/
+ /* alternate syntax */
+ { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, },/*SRC*/
+ { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, },/*SRC*/
+ { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, },/*SRC*/
+ { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, },/*SRC*/
+ { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, },/*PREFER */
+ { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR },/*SRC*/
+ { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR },/*SRC*/
+ { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR },/*SRC*/
+ { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR },
+ { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR },
+ { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR },
+ { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, },/*PREFER*/
+ { "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST},
+ FL_EXT|FL_SMR, 0x0C40, 0xFEE0 },
+ { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, },
+ { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, },
+ { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, },
+ { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR },
+ { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR },
+ { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR},/*pseudo-op*/
+ { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, },
+ { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR },
+ { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, },
+ { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, },
+ { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR },
+ { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR},
+ { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR },/*SRC*/
+ { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR },
+ { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR },/*SRC*/
+ { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR },
+ { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR },
+ { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR },
+ { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, },
+ { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, },
+ { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, },
+ { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, },
+ { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, },/*SRC*/
+ { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR },
+ { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, },
+ { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, },
+ { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, },
+ { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR },
+ { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, },
+ { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR },
+ { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, },
+ { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR },
+ { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, }, /*SRC*/
+ { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR },
+ { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR },
+ { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, },
+ { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR },
+ { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, },
+ { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR },
+ { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, },
+ { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, },
+ { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, },
+ { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, },
+ { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, },
+ { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, },
+ { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, },
+ { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/
+ { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, },
+ { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, },
+ { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, },
+ { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR },
+ { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, },
+ { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, },
+ { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, },
+ { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR },
+ { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR },
+ { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, },
+ { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, },
+ { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, },
+ { "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
+ B_RET|FL_NR, },
+ { "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
+ B_RET|FL_DELAY|FL_NR, },
+ { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, },
+ { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, },
+ { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, },
+ { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, },
+ { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, },
+ { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, },
+ { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR },
+ { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, },
+ { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, },
+ { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, },
+ { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, },
+ { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, },
+ { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, },
+ { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, },
+ { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, },
+ { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, },
+ { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, },
+ { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, },
+ { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, },
+ { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, },
+ { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, },
+ { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, },
+ { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, },
+ { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, },/*SRC*/
+ { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR },
+ { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, },
+ { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, },
+ { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, },
+ { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, },
+ { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, },
+ { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, },
+ { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, },
+ { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, },
+ { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
+ FL_EXT, 0x0C60, 0xFEE0 },
+ { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, },
+ { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, },
+ { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, },
+ { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
+ FL_EXT, 0x0C80, 0xFEE0 },
+ { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, },
+ { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, },
+ { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, },
+ { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/
+ { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/
+ { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR },
+ { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR },
+ { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, }, /*PREFER*/
+ { "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
+ FL_EXT|FL_SMR, 0x0C20, 0xFCE0 },
+ { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, },
+ { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, },
+ { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, },
+ { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, },
+ { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR },
+ { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, },
+ { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/
+ { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR },
+ { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, },
+ { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, },
+ { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, },
+ { NULL, },
+ };
+
+ /* assume all parallel instructions have at least three operands */
+ const partemplate tic54x_paroptab[] = {
+ { "ld","mac", 1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},},
+ { "ld","macr",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},},
+ { "ld","mas", 1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},},
+ { "ld","masr",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},},
+ { "st","add", 1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
+ { "st","ld", 1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
+ { "st","ld", 1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_T}, },
+ { "st","mac", 1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
+ { "st","macr",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
+ { "st","mas", 1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
+ { "st","masr",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
+ { "st","mpy", 1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
+ { "st","sub", 1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
+ { NULL,NULL },
+ };
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.74
diff -d -c -p -b -w -r1.74 ChangeLog
*** ChangeLog 2000/05/03 22:19:45 1.74
--- ChangeLog 2000/05/05 13:19:12
***************
*** 1,3 ****
--- 1,7 ----
+ 2000-05-04 Timothy Wall <twall@cygnus.com>
+
+ * tic54x.h: New.
+
2000-05-03 J.T. Conklin <jtc@redback.com>
* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
Index: include/opcode/tic54x.h
===================================================================
RCS file: tic54x.h
diff -N tic54x.h
*** /dev/null Tue May 5 13:32:27 1998
--- tic54x.h Fri May 5 06:19:12 2000
***************
*** 0 ****
--- 1,167 ----
+ /* tic54x.h -- Header file for TI TMS320C54X opcode table
+ Copyright 1999, 2000 Free Software Foundation, Inc.
+ Written by Timothy Wall (twall@cygnus.com)
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 1, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the Free
+ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+ #ifndef _TIC54X_H_
+ #define _TIC54X_H_
+
+ typedef struct _symbol
+ {
+ const char *name;
+ unsigned short value;
+ } symbol;
+
+ enum optype {
+ OPT = 0x8000,
+ OP_None = 0x0,
+
+ OP_Xmem, /* AR3 or AR4, indirect */
+ OP_Ymem, /* AR3 or AR4, indirect */
+ OP_pmad, /* PROG mem, direct */
+ OP_dmad, /* DATA mem, direct */
+ OP_Smem,
+ OP_Lmem, /* 32-bit single-addressed (direct/indirect) */
+ OP_MMR,
+ OP_PA,
+ OP_Sind,
+ OP_xpmad,
+ OP_xpmad_ms7,
+ OP_MMRX,
+ OP_MMRY,
+
+ OP_SRC1, /* src accumulator in bit 8 */
+ OP_SRC, /* src accumulator in bit 9 */
+ OP_RND, /* rounded result dst accumulator, opposite of bit 8 */
+ OP_DST, /* dst accumulator in bit 8 */
+ OP_ARX, /* arX in bits 0-3 */
+ OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */
+ OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */
+ OP_B, /* ACC B only */
+ OP_A, /* ACC A only */
+
+ OP_lk, /* 16-bit immediate, '#' optional */
+ OP_TS,
+ OP_k8, /* -128 <= k <= 128 */
+ OP_16, /* literal "16" */
+ OP_BITC, /* 0 to 16 */
+ OP_CC, /* condition code */
+ OP_CC2, /* 4-bit condition code */
+ OP_CC3, /* 2-bit condition code */
+ OP_123, /* 1, 2, or 3 */
+ OP_031, /* 0-31, numeric */
+ OP_k5, /* 0 to 31 */
+ OP_k8u, /* 0 to 255 */
+ OP_ASM, /* "ASM" */
+ OP_T, /* "T" */
+ OP_DP, /* "DP" */
+ OP_ARP, /* "ARP" */
+ OP_k3, /* 0-7 */
+ OP_lku, /* 0 to 65535 */
+ OP_N, /* 0/1 or ST0/ST1 */
+ OP_SBIT, /* status bit or 0-15 */
+ OP_12, /* one or two */
+ OP_k9, /* 9 bits of data page (DP) address */
+ OP_TRN, /* "TRN" */
+
+ };
+
+ typedef struct _template
+ {
+ /* The opcode mnemonic */
+ const char *name;
+
+ unsigned int words; /* insn size in words */
+ int minops, maxops; /* min/max operand count */
+ /* The significant bits in the opcode. Other bits are zero.
+ Instructions with more than 16 bits of opcode store the rest in the upper
+ 16 bits.
+ */
+ unsigned short opcode;
+ #define INDIRECT(OP) ((OP)&0x80)
+ #define MOD(OP) (((OP)>>3)&0xF)
+ #define ARF(OP) ((OP)&0x7)
+ #define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12)
+ #define SRC(OP) ((OP)&0x200)
+ #define DST(OP) ((OP)&0x100)
+ #define SRC1(OP) ((OP)&0x100)
+ #define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F))
+ #define SHFT(OP) ((OP)&0xF)
+ #define ARX(OP) ((OP)&0x7)
+ #define XMEM(OP) (((OP)&0x00F0)>>4)
+ #define YMEM(OP) ((OP)&0x000F)
+ #define XMOD(C) (((C)&0xC)>>2)
+ #define XARX(C) (((C)&0x3)+2)
+ #define CC3(OP) (((OP)>>8)&0x3)
+ #define SBIT(OP) ((OP)&0xF)
+ #define MMR(OP) ((OP)&0x7F)
+ #define MMRX(OP) ((((OP)>>4)&0xF)+16)
+ #define MMRY(OP) (((OP)&0xF)+16)
+
+ #define OPTYPE(X) ((X)&~OPT)
+
+ /* Ones in this mask indicate which bits must match the opcode field.
+ Zeroes indicate don't care bits (operands and/or opcode options) */
+ unsigned short mask;
+
+ /* An array of operand codes (at most 4 operands) */
+ #define MAX_OPERANDS 4
+ enum optype operand_types[MAX_OPERANDS];
+
+ /* Special purpose flags (e.g. branch type, parallel, delay, etc)
+ */
+ unsigned short flags;
+ #define B_NEXT 0 /* normal execution, next insn is next address */
+ #define B_BRANCH 1 /* next insn is in opcode */
+ #define B_RET 2 /* next insn is on stack */
+ #define B_BACC 3 /* next insn is in acc */
+ #define B_REPEAT 4 /* next insn repeats */
+ #define FL_BMASK 0x07
+
+ #define FL_DELAY 0x10 /* instruction uses delay slots */
+ #define FL_EXT 0x20 /* instruction takes two words */
+ #define FL_FAR 0x40 /* far mode addressing */
+ #define FL_LP 0x80 /* LP-only instruction */
+ #define FL_NR 0x100 /* no repeat allowed */
+ #define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */
+
+ unsigned short opcode2, mask2; /* some insns have an extended opcode */
+
+ } template;
+
+ typedef struct _partemplate {
+ char *name;
+ char *parname;
+ unsigned int words; /* length in words */
+ int minops, maxops; /* min/max operand count for 2nd part of insn */
+ unsigned short opcode;
+ unsigned short mask;
+ enum optype operand_types[MAX_OPERANDS];
+ enum optype paroperand_types[MAX_OPERANDS];
+ } partemplate;
+
+ extern const template tic54x_unknown_opcode;
+ extern const template tic54x_optab[];
+ extern const partemplate tic54x_paroptab[];
+ extern const symbol mmregs[], regs[];
+ extern const symbol condition_codes[], cc2_codes[], status_bits[];
+ extern const symbol cc3_codes[];
+ extern const char *misc_symbols[];
+
+ #endif /* TIC54X_H */