[patch] prelim gas/doc for i860

[Jason Eckhardt <jle at cygnus dot com>]

This adds i860 specific info to the as docs as requested by Nick. This is
preliminary because the assembler is still to be written (I'm just now
starting this, and will continue as weekends permit).
The i860 assembler that existed previously was never finished
and doesn't even build. Further, its not BFD_ASSEMBLER and it doesn't
do ELF (it doesn't do anything, but you get the point).


2000-07-30  Jason Eckhardt  <jle@cygnus.com>

	* c-i860.texi: New file. 
	* Makefile.am (CPU_DOCS): Add c-i860.texi.
	* Makefile.in: Regenerate.
	* all.texi: Add I860 as relevant architecture.
	* as.texinfo: Include i860 dependent file c-i860.texi.


Index: Makefile.am
===================================================================
RCS file: /cvs/src/src/gas/doc/Makefile.am,v
retrieving revision 1.6
diff -c -3 -p -r1.6 Makefile.am
*** Makefile.am	2000/06/20 13:52:29	1.6
--- Makefile.am	2000/07/30 15:26:54
*************** CPU_DOCS = \
*** 24,29 ****
--- 24,30 ----
  	c-hppa.texi \
  	c-i370.texi \
  	c-i386.texi \
+ 	c-i860.texi \
  	c-i960.texi \
  	c-m32r.texi \
  	c-m68hc11.texi \

Index: all.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/all.texi,v
retrieving revision 1.5
diff -c -3 -p -r1.5 all.texi
*** all.texi	2000/06/20 13:52:29	1.5
--- all.texi	2000/07/30 15:26:55
***************
*** 35,40 ****
--- 35,41 ----
  @set HPPA
  @set I370
  @set I80386
+ @set I860
  @set I960
  @set M32R
  @set M68HC11

Index: as.texinfo
===================================================================
RCS file: /cvs/src/src/gas/doc/as.texinfo,v
retrieving revision 1.15
diff -c -3 -p -r1.15 as.texinfo
*** as.texinfo	2000/06/20 13:52:29	1.15
--- as.texinfo	2000/07/30 15:27:10
*************** subject, see the hardware manufacturer's
*** 5027,5032 ****
--- 5027,5035 ----
  @ifset I80386
  * i386-Dependent::              Intel 80386 Dependent Features
  @end ifset
+ @ifset I860
+ * i860-Dependent::              Intel 80860 Dependent Features
+ @end ifset
  @ifset I960
  * i960-Dependent::              Intel 80960 Dependent Features
  @end ifset
*************** family.
*** 5206,5211 ****
--- 5209,5218 ----
  
  @ifset I80386
  @include c-i386.texi
+ @end ifset
+ 
+ @ifset I860
+ @include c-i860.texi
  @end ifset
  
  @ifset I960


NEW FILE:

*** /dev/null	Tue May  5 15:32:27 1998
--- c-i860.texi	Sun Jul 30 10:31:13 2000
***************
*** 0 ****
--- 1,90 ----
+ @c Copyright (C) 2000 Free Software Foundation, Inc.
+ @c This is part of the GAS manual.
+ @c For copying conditions, see the file as.texinfo.
+ @ifset GENERIC
+ @page
+ @node i860-Dependent
+ @chapter Intel i860 Dependent Features
+ @end ifset
+ @ifclear GENERIC
+ @node Machine Dependencies
+ @chapter Intel i860 Dependent Features
+ @end ifclear
+ 
+ @ignore
+ @c FIXME: This is basically a stub for i860. There is tons more information
+ that I will add later (jle@cygnus.com). The assembler is still being
+ written. The i860 assembler that existed previously was never finished
+ and doesn't even build. Further, its not BFD_ASSEMBLER and it doesn't
+ do ELF (it doesn't do anything, but you get the point).
+ @end ignore
+ 
+ @cindex i860 support
+ @menu
+ * Options-i860::                i860 Command-line Options
+ * Directives-i860::             i860 Machine Directives
+ * Opcodes for i860::            i860 Opcodes
+ @end menu
+ 
+ @node Options-i860
+ 
+ @section i860 Command-line Options
+ @subsection SVR4 compatibility options 
+ @table @code
+ @item -V
+ Print assembler version.
+ @item -Qy
+ Ignored.
+ @item -Qn
+ Ignored.
+ @end table
+ @subsection Other options 
+ @table @code
+ @item -EL
+ Select little endian output (this is the default).
+ @item -EB
+ Select big endian output. Note that the i860 always reads instructions
+ as little endian data, so this option only effects data and not
+ instructions.
+ @end table
+ 
+ @node Directives-i860
+ @section i860 Machine Directives
+ 
+ @cindex machine directives, i860
+ @cindex i860 machine directives
+ 
+ @table @code
+ @cindex @code{dual} directive, i860
+ @item .dual
+ Enter dual instruction mode. While this directive is supported, the
+ preferred way to use dual instruction mode is to explicitly code
+ the dual bit with the @code{d.} prefix.
+ @end table
+ 
+ @table @code
+ @cindex @code{enddual} directive, i860
+ @item .enddual
+ Exit dual instruction mode. While this directive is supported, the
+ preferred way to use dual instruction mode is to explicitly code
+ the dual bit with the @code{d.} prefix.
+ @end table
+ 
+ @table @code
+ @cindex @code{atmp} directive, i860
+ @item .atmp
+ Change the temporary register used when expanding pseudo operations. The
+ default register is @code{r31}.
+ @end table
+ 
+ @node Opcodes for i860
+ @section i860 Opcodes
+ 
+ @cindex opcodes, i860
+ @cindex i860 opcodes
+ All of the Intel i860 machine instructions are supported.
+ 
+ Some opcodes are processed beyond simply emitting a single corresponding
+ instruction. For example, @samp{mov} and other instructions with larg
+ displacements may be expanded into 2 or 3 instructions (FIXME: add details).
+