GAS doc bug

[Andreas Schwab <schwab at suse dot de>]

Current makeinfo chokes on the GAS documentation: @item does not take a
brace delimited argument.  I have also fixed a warning due to use of [] in
@var.

2000-08-11  Andreas Schwab  <schwab@suse.de>

	* doc/c-arm.texi (ARM Directives): Fix warnings from makeinfo.

	* doc/c-i860.texi (Opcodes for i860): Remove braces from @item
	argument.

Index: gas/doc/c-arm.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-arm.texi,v
retrieving revision 1.7
diff -u -a -u -r1.7 gas/doc/c-arm.texi
--- gas/doc/c-arm.texi	2000/06/25 17:59:22	1.7
+++ gas/doc/c-arm.texi	2000/08/11 12:31:37
@@ -51,7 +51,7 @@
 This option specifies that any Arm or Thumb instruction should be assembled.
 
 @cindex @code{-mfpa} command line option, ARM
-@item -mfpa @var{[10|11]}
+@item -mfpa @code{[10|11]}
 This option specifies the floating point architecture in use on the
 target processor. 
 
@@ -69,7 +69,7 @@
 be marked as supporting interworking.
 
 @cindex @code{-mapcs} command line option, ARM
-@item -mapcs @var{[26|32]}
+@item -mapcs @code{[26|32]}
 This option specifies that the output generated by the assembler should
 be marked as supporting the indicated version of the Arm Procedure.
 Calling Standard.
@@ -180,7 +180,7 @@
 @end smallexample
 
 @cindex @code{code} directive, ARM
-@item .code @var{[16|32]}
+@item .code @code{[16|32]}
 This directive selects the instruction set being generated. The value 16
 selects Thumb, with the value 32 selecting ARM.
 
Index: gas/doc/c-i860.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-i860.texi,v
retrieving revision 1.2
diff -u -a -u -r1.2 gas/doc/c-i860.texi
--- gas/doc/c-i860.texi	2000/08/10 23:23:23	1.2
+++ gas/doc/c-i860.texi	2000/08/11 12:34:46
@@ -107,7 +107,7 @@
 they result in an expansion to multiple actual i860 instructions. Below
 are the pseudo-instructions that result in expansions.
 @itemize @bullet
-@item {Load large immediate into general register:}
+@item Load large immediate into general register:
 
 The pseudo-instruction @code{mov imm,%rn} (where the immediate does
 not fit within a signed 16-bit field) will be expanded into:
@@ -115,7 +115,7 @@
 orh large_imm@@h,%r0,%rn
 or large_imm@@l,%rn,%rn
 @end smallexample
-@item {Load/store with relocatable address expression:}
+@item Load/store with relocatable address expression:
 
 For example, the pseudo-instruction @code{ld.b addr,%rn} 
 will be expanded into:
@@ -125,7 +125,7 @@
 @end smallexample
 
 The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well.
-@item {Signed large immediate with add/subtract:}
+@item Signed large immediate with add/subtract:
 If any of the arithmetic operations @code{adds, addu, subs, subu} are used
 with an immediate larger than 16-bits (signed), then they will be expanded.
 For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
@@ -134,7 +134,7 @@
 or large_imm@@l,%r31,%r31
 adds %r31,%rx,%rn
 @end smallexample
-@item {Unsigned large immediate with logical operations:}
+@item Unsigned large immediate with logical operations:
 Logical operations (@code{or, andnot, or, xor}) also result in expansions.
 The pseudo-instruction @code{or large_imm,%rx,%rn} results in:
 @smallexample

-- 
Andreas Schwab                                  "And now for something
SuSE Labs                                        completely different."
Andreas.Schwab@suse.de
SuSE GmbH, Schanzäckerstr. 10, D-90443 Nürnberg