Re: RFC: PowerPC GAS changes

[Mark Hatle <fray at mvista dot com>]

Geoff Keating wrote:
> If you think there will be too many categories of instructions to have
> one bit per category fit into 32 bits, one technique is to change the
> flag word into a plain integer to hold a category number, so that the
> test for whether an opcode is valid for an ISA looks like
> 
> #define OPCODE_VALID_FOR_ISA (opcode, isa) \
>   ((powerpc_isa_table[isa][opcode->category / 32]  \
>     & (1 << opcode->category % 32)) != 0)
> 
> where 'category' is the new name for 'flags' in the current opcode
> structure.  This can easily handle 100 or more categories with
> no significant cost for the ISA table.

I think I see where you are heading with this.  In my opinion this would
work.  However we will have a ton of categories....

> The important thing is that the opcode table, which is big, doesn't
> - use much more memory

You solution would definatly use less memory.  My method would add
approx
8k to the table.  (Thats adding an additional field.)

> - become unreadable or difficult to change

I believe currently it is very unreadable/difficult to understand.
Unfortunatly the category method will probably make it worse.

> - become more expensive to parse, particularly in the disassembler

I don't believe either method will make it more difficult to parse.
The dissasembler can ignore the CPU type, or if one is picked then
act on it.  (ARM does this.)

This leads me then to the question, which is more important?
8k of memory which makes it more readable/changable, or less readable
but also less memory?

I'm willing to make either change, but I don't know what the priority
is for the PPC section?

(Again my personal feeling is to make it more readable, and use the 8k
of memory... but I'm definatly open if that isn't what is desirable.)

--Mark