This is the mail archive of the
binutils@sources.redhat.com
mailing list for the binutils project.
[patch] fix most MIPS32 assembly issues.
- To: binutils at sourceware dot cygnus dot com
- Subject: [patch] fix most MIPS32 assembly issues.
- From: cgd at sibyte dot com (Chris G. Demetriou)
- Date: 10 Oct 2000 18:16:16 -0700
This patch cleans up the MIPS32 issues i mentioned in the previous
mail which proposed a MIPS32 instruction testsuite entry.
In a nutshell, it:
* adds a new instruction operand format 'U' which is used by clo and
clz. Some mips processors use the rd slot to encode the result,
others use the rt slot to encode the result, and to be compatible you
have to put the result register in both. ("yes, really.")
* adds a new instruction operand format 'J', which is a 19 bit code in
the same place as the low 19 bits of syscall codes. It's used
e.g. for 'wait' codes.
* renames the OP_*_SYSCALL macros to be OP_*_CODE20, and shares them
between syscall ('B' format) and 20-bit-code break format (formerly
'm' format, now gone). (Note that config/tc-mips.c:macro_build()
didn't seem to do anything with 'm' presumably because it was not yet
used in any instructions expanded from macros ... but that seems bad
style. All of the new operand specifiers that I added, I added
wherever they might eventually be used)
* tweaks the opcode table slightly: moves pref and ssnop to the top,
so they get decoded correctly. makes ssnop available on mips32 (since
it is -- it's just implemented the same as nop in the MIPS32 4K
family, according to those docs). adds a 20-bit-code break
instruction for MIPS32. add 'sel' operands for m[tf]c[1-3] for
MIPS32. update for other changes above.
The information used to formulate this patch came from the MIPS32 4Kc
manual and the IDT RC32364 manuals. The latter isn't Really a MIPS32
part but for the purposes of the encodings and semantics of the
instructions added as part of the recent MIPS32 patch, upon quick
examination, it is close enough. 8-)
Apply patch in src. ChangeLogs for different dirs broken out below.
chris
===================================================================
for gas/Changelog:
2000-10-10 Chris Demetriou <cgd@sibyte.com>
* config/tc-mips.c (macro_build): Add new 'U' and 'J' operand
specifiers.
(validate_mips_insn): Likewise. Also, update 'B' operand
specifier to use OP_*_CODE20 constants and delete 'm' operand
specifier.
(mips_ip): Remove 'm' operand specifier, add 'U' and 'J'
operand specifiers. Change warning generated by 'B' operand
specifier to reflect its new multi-purpose usage.
for include/opcode/ChangeLog:
2000-10-10 Chris Demetriou <cgd@sibyte.com>
mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
(OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
OP_*_SYSCALL definitions.
(OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
19 bit wait codes.
(MIPS operand specifier comments): Remove 'm', add 'U' and
'J', and update the meaning of 'B' so that it's more general.
for opcodes/ChangeLog:
2000-10-10 Chris Demetriou <cgd@sibyte.com>
mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument
specifiers. Update 'B' for new constant names, and remove
'm'.
mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
near the top of the array, so they are disassembled properly.
Enable "ssnop" for MIPS32. Add "break" variant with 20 bit
code for MIPS32. Update "clo" and "clz" to use 'U' operand
specifier. Add 'H' format specifier variants for "mfc1,"
"mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update
MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32
"wait" variant which uses 'J' operand specifier.
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.26
diff -c -r1.26 tc-mips.c
*** tc-mips.c 2000/09/20 22:05:08 1.26
--- tc-mips.c 2000/10/10 23:24:37
***************
*** 2597,2602 ****
--- 2597,2610 ----
insn.insn_opcode |= va_arg (args, int) << 11;
continue;
+ case 'U':
+ {
+ int tmp = va_arg (args, int);
+ insn.insn_opcode |= tmp << 16;
+ insn.insn_opcode |= tmp << 11;
+ continue;
+ }
+
case 'V':
case 'S':
insn.insn_opcode |= va_arg (args, int) << 11;
***************
*** 2617,2622 ****
--- 2625,2634 ----
insn.insn_opcode |= va_arg (args, int) << 6;
continue;
+ case 'J':
+ insn.insn_opcode |= va_arg (args, int) << 6;
+ continue;
+
case 'q':
insn.insn_opcode |= va_arg (args, int) << 6;
continue;
***************
*** 6976,6982 ****
case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case 'A': break;
! case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break;
case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
--- 6988,6994 ----
case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case 'A': break;
! case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
***************
*** 6984,6989 ****
--- 6996,7002 ----
case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
case 'I': break;
+ case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
case 'L': break;
case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
***************
*** 7002,7008 ****
case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
case 'l': break;
- case 'm': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
--- 7015,7020 ----
***************
*** 7015,7020 ****
--- 7027,7035 ----
case 'x': break;
case 'z': break;
case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
+ case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
+ USE_BITS (OP_MASK_RT, OP_SH_RT);
+ break;
default:
as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
c, opc->name, opc->args);
***************
*** 7268,7296 ****
s = expr_end;
continue;
! case 'm': /* Full 20 bit break code. */
my_getExpression (&imm_expr, s);
-
check_absolute_expr (ip, &imm_expr);
-
if ((unsigned) imm_expr.X_add_number > 0xfffff)
! {
! as_warn (_("Illegal break code (%ld)"),
! (long) imm_expr.X_add_number);
! imm_expr.X_add_number &= 0xfffff;
! }
!
! ip->insn_opcode |= imm_expr.X_add_number << 6;
! imm_expr.X_op = O_absent;
! s = expr_end;
!
! continue;
!
! case 'B': /* syscall code */
! my_getExpression (&imm_expr, s);
! check_absolute_expr (ip, &imm_expr);
! if ((unsigned) imm_expr.X_add_number > 0xfffff)
! as_warn (_("Illegal syscall code (%ld)"),
(long) imm_expr.X_add_number);
ip->insn_opcode |= imm_expr.X_add_number << 6;
imm_expr.X_op = O_absent;
--- 7283,7293 ----
s = expr_end;
continue;
! case 'B': /* 20-bit syscall/break code */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned) imm_expr.X_add_number > 0xfffff)
! as_warn (_("Illegal 20-bit code (%ld)"),
(long) imm_expr.X_add_number);
ip->insn_opcode |= imm_expr.X_add_number << 6;
imm_expr.X_op = O_absent;
***************
*** 7311,7316 ****
--- 7308,7324 ----
s = expr_end;
continue;
+ case 'J': /* 19-bit wait code */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned) imm_expr.X_add_number > 0x7ffff)
+ as_warn (_("Illegal 19-bit code (%ld)"),
+ (long) imm_expr.X_add_number);
+ ip->insn_opcode |= imm_expr.X_add_number << 6;
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
case 'P': /* Performance register */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
***************
*** 7336,7341 ****
--- 7344,7350 ----
case 'G': /* coprocessor destination register */
case 'x': /* ignore register name */
case 'z': /* must be zero register */
+ case 'U': /* destination register (clo/clz) */
s_reset = s;
if (s[0] == '$')
{
***************
*** 7450,7455 ****
--- 7459,7468 ----
case 'G':
ip->insn_opcode |= regno << 11;
break;
+ case 'U':
+ ip->insn_opcode |= regno << 11;
+ ip->insn_opcode |= regno << 16;
+ break;
case 'w':
case 't':
case 'E':
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.6
diff -c -r1.6 mips.h
*** mips.h 2000/09/14 01:47:37 1.6
--- mips.h 2000/10/10 23:24:37
***************
*** 48,56 ****
breakpoint instruction are not defined; Kane says the breakpoint
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
only use ten bits). An optional two-operand form of break/sdbbp
! allows the lower ten bits to be set too.
! The syscall instruction uses SYSCALL.
The general coprocessor instructions use COPZ. */
--- 48,58 ----
breakpoint instruction are not defined; Kane says the breakpoint
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
only use ten bits). An optional two-operand form of break/sdbbp
! allows the lower ten bits to be set too, and MIPS32 and later
! architectures allow 20 bits to be set with a signal operand
! (using CODE20).
! The syscall instruction uses CODE20.
The general coprocessor instructions use COPZ. */
***************
*** 82,89 ****
#define OP_SH_PREFX 11
#define OP_MASK_CCC 0x7
#define OP_SH_CCC 8
! #define OP_MASK_SYSCALL 0xfffff
! #define OP_SH_SYSCALL 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
#define OP_MASK_FD 0x1f
--- 84,91 ----
#define OP_SH_PREFX 11
#define OP_MASK_CCC 0x7
#define OP_SH_CCC 8
! #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code */
! #define OP_SH_CODE20 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
#define OP_MASK_FD 0x1f
***************
*** 128,135 ****
#define OP_SH_PERFREG 1
#define OP_SH_SEL 0 /* Coprocessor select field */
#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
! #define OP_SH_CODE20 6 /* 20 bit breakpoint code */
! #define OP_MASK_CODE20 0xfffff
/* This structure holds information for a particular instruction. */
--- 130,137 ----
#define OP_SH_PERFREG 1
#define OP_SH_SEL 0 /* Coprocessor select field */
#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
! #define OP_SH_CODE19 6 /* 19 bit wait code */
! #define OP_MASK_CODE19 0x7ffff
/* This structure holds information for a particular instruction. */
***************
*** 176,182 ****
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
- "m" 20 bit breakpoint code (OP_*_CODE20)
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
"q" 10 bit extra breakpoint code (OP_*_CODE2)
--- 178,183 ----
***************
*** 186,193 ****
"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
"v" 5 bit same register used as both source and destination (OP_*_RS)
"w" 5 bit same register used as both target and destination (OP_*_RT)
"C" 25 bit coprocessor function code (OP_*_COPZ)
! "B" 20 bit syscall function code (OP_*_SYSCALL)
"x" accept and ignore register name
"z" must be zero register
--- 187,197 ----
"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
"v" 5 bit same register used as both source and destination (OP_*_RS)
"w" 5 bit same register used as both target and destination (OP_*_RT)
+ "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
+ (used by clo and clz)
"C" 25 bit coprocessor function code (OP_*_COPZ)
! "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
! "J" 19 bit wait function code (OP_*_CODE19)
"x" accept and ignore register name
"z" must be zero register
***************
*** 221,228 ****
Characters used so far, for quick reference when adding more:
"<>(),"
! "ABCDEFGHILMNPSTRVW"
! "abcdfhijklmopqrstuvwxz"
*/
/* These are the bits which may be set in the pinfo field of an
--- 225,232 ----
Characters used so far, for quick reference when adding more:
"<>(),"
! "ABCDEFGHIJLMNPRSTUVW"
! "abcdfhijklopqrstuvwxz"
*/
/* These are the bits which may be set in the pinfo field of an
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.7
diff -c -r1.7 mips-dis.c
*** mips-dis.c 2000/09/14 01:47:38 1.7
--- mips-dis.c 2000/10/10 23:24:38
***************
*** 157,162 ****
--- 157,186 ----
reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
break;
+ case 'U':
+ {
+ /* First check for both rd and rt being equal. */
+ int reg = (l >> OP_SH_RD) & OP_MASK_RD;
+ if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
+ (*info->fprintf_func) (info->stream, "$%s",
+ reg_names[reg]);
+ else
+ {
+ /* If one is zero use the other. */
+ if (reg == 0)
+ (*info->fprintf_func) (info->stream, "$%s",
+ reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
+ (*info->fprintf_func) (info->stream, "$%s",
+ reg_names[reg]);
+ else /* Bogus, result depends on processor. */
+ (*info->fprintf_func) (info->stream, "$%s or $%s",
+ reg_names[reg],
+ reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ }
+ }
+ break;
+
case 'z':
(*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
break;
***************
*** 177,195 ****
(l >> OP_SH_CODE2) & OP_MASK_CODE2);
break;
- case 'm':
- (*info->fprintf_func) (info->stream, "0x%x",
- (l >> OP_SH_CODE20) & OP_MASK_CODE20);
- break;
-
case 'C':
(*info->fprintf_func) (info->stream, "0x%x",
(l >> OP_SH_COPZ) & OP_MASK_COPZ);
break;
case 'B':
(*info->fprintf_func) (info->stream, "0x%x",
! (l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL);
break;
case 'S':
--- 201,219 ----
(l >> OP_SH_CODE2) & OP_MASK_CODE2);
break;
case 'C':
(*info->fprintf_func) (info->stream, "0x%x",
(l >> OP_SH_COPZ) & OP_MASK_COPZ);
break;
case 'B':
+ (*info->fprintf_func) (info->stream, "0x%x",
+ (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+ break;
+
+ case 'J':
(*info->fprintf_func) (info->stream, "0x%x",
! (l >> OP_SH_CODE19) & OP_MASK_CODE19);
break;
case 'S':
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.10
diff -c -r1.10 mips-opc.c
*** mips-opc.c 2000/09/14 01:47:38 1.10
--- mips-opc.c 2000/10/10 23:24:38
***************
*** 112,118 ****
--- 112,120 ----
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, membership */
+ {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4 },
{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
+ {"ssnop", "", 0x00000040, 0xffffffff, 0, M1|P4 },
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
***************
*** 220,225 ****
--- 222,228 ----
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 },
{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
+ {"break", "B", 0x0000000d, 0xfc00003f, TRAP, P4 },
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
***************
*** 328,335 ****
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
! {"clo", "d,s", 0x70000021, 0xfc1f07ff, WR_d|RD_s, P4 },
! {"clz", "d,s", 0x70000020, 0xfc1f07ff, WR_d|RD_s, P4 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
--- 331,338 ----
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
! {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|RD_s, P4 },
! {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|RD_s, P4 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
***************
*** 545,552 ****
--- 548,558 ----
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, P4 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
+ {"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, P4},
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
+ {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, P4 },
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
+ {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, P4 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
***************
*** 580,587 ****
--- 586,596 ----
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, P4 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
+ {"mtc1", "t,G,H", 0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S, P4 },
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
+ {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, P4 },
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
+ {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, P4 },
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
***************
*** 620,626 ****
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
! {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
--- 629,635 ----
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
! /* pref is at the start of the table. */
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
***************
*** 657,663 ****
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 },
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
! {"sdbbp", "m", 0x7000003f, 0xfc00003f, TRAP, P4 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
--- 666,672 ----
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 },
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
! {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, P4 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
***************
*** 711,717 ****
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
! {"ssnop", "", 0x00000040, 0xffffffff, 0, M1 },
{"standby", "", 0x42000021, 0xffffffff, 0, V1 },
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
--- 720,726 ----
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
! /* ssnop is at the start of the table. */
{"standby", "", 0x42000021, 0xffffffff, 0, V1 },
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
***************
*** 810,815 ****
--- 819,825 ----
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1|P4 },
+ {"wait", "J", 0x42000020, 0xfe00003f, TRAP, P4 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
/* No hazard protection on coprocessor instructions--they shouldn't