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[patch] MIPS opcodes P4 -> I32 cleanup.


This is a bit of cleanup on top of the previous patches, in which I
left the 'P4' opcode membership specifier (added in the MIPS32
changes) pretty much as-is in the opcode table.  It really should be
I32, and this does that.


Applies from src, on top of all of the rest, verified as with the
rest.  8-)



chris
=============================================================================

ChangeLog for opcodes:

2000-10-13  Chris Demetriou  <cgd@sibyte.com>

	* mips-opc.c (P4): Delete.
	(mips_builtin_opcodes): Replace all uses of P4 with I32.


diff -rc ../src.P7_REDO_2/opcodes/mips-opc.c ./opcodes/mips-opc.c
*** ../src.P7_REDO_2/opcodes/mips-opc.c	Fri Oct 13 15:02:26 2000
--- ./opcodes/mips-opc.c	Fri Oct 13 17:24:46 2000
***************
*** 80,87 ****
  #define I32	INSN_ISA32
  #define I64	INSN_ISA64
  
- #define P4	I32			/* XXX temporary */
- 
  #define P3	INSN_4650
  #define L1	INSN_4010
  #define V1      INSN_4100
--- 80,85 ----
***************
*** 116,124 ****
     them first.  The assemblers uses a hash table based on the
     instruction name anyhow.  */
  /* name,    args,	match,	    mask,	pinfo,          membership */
! {"pref",    "k,o(b)",	0xcc000000, 0xfc000000, RD_b,		G3|M1|P4	},
  {"nop",     "",		0x00000000, 0xffffffff,	0,		I1	},
! {"ssnop",   "",		0x00000040, 0xffffffff,	0,		M1|P4	},
  {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,		I1	}, /* addiu */
  {"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,		I1	}, /* ori */
  {"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,	I1	},
--- 114,122 ----
     them first.  The assemblers uses a hash table based on the
     instruction name anyhow.  */
  /* name,    args,	match,	    mask,	pinfo,          membership */
! {"pref",    "k,o(b)",	0xcc000000, 0xfc000000, RD_b,		G3|M1|I32	},
  {"nop",     "",		0x00000000, 0xffffffff,	0,		I1	},
! {"ssnop",   "",		0x00000040, 0xffffffff,	0,		M1|I32	},
  {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,		I1	}, /* addiu */
  {"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,		I1	}, /* ori */
  {"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,	I1	},
***************
*** 226,232 ****
  {"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 	I2|T3	},
  {"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,	I2	},
  {"break",   "",		0x0000000d, 0xffffffff,	TRAP,		I1	},
! {"break",   "B",	0x0000000d, 0xfc00003f,	TRAP,		P4	},
  {"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,		I1	},
  {"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,		I1	},
  {"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
--- 224,230 ----
  {"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 	I2|T3	},
  {"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,	I2	},
  {"break",   "",		0x0000000d, 0xffffffff,	TRAP,		I1	},
! {"break",   "B",	0x0000000d, 0xfc00003f,	TRAP,		I32	},
  {"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,		I1	},
  {"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,		I1	},
  {"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
***************
*** 325,331 ****
  {"c.ngt.s", "M,S,T",	0x4600003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4|M1	},
  {"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
  {"c.ngt.ps","M,S,T",	0x46c0003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
! {"cache",   "k,o(b)",	0xbc000000, 0xfc000000, RD_b,		I3|T3|M1|P4	},
  {"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
  {"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
  {"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
--- 323,329 ----
  {"c.ngt.s", "M,S,T",	0x4600003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4|M1	},
  {"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
  {"c.ngt.ps","M,S,T",	0x46c0003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
! {"cache",   "k,o(b)",	0xbc000000, 0xfc000000, RD_b,		I3|T3|M1|I32	},
  {"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
  {"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
  {"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
***************
*** 335,342 ****
  {"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	I1	},
  {"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
  {"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,	I1	},
! {"clo",     "U,s",	0x70000021, 0xfc0007ff, WR_d|RD_s,	P4	},
! {"clz",     "U,s",	0x70000020, 0xfc0007ff, WR_d|RD_s,	P4	},
  {"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC,	I1	},
  {"ctc1",    "t,G",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
  {"ctc1",    "t,S",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
--- 333,340 ----
  {"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	I1	},
  {"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
  {"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,	I1	},
! {"clo",     "U,s",	0x70000021, 0xfc0007ff, WR_d|RD_s,	I32	},
! {"clz",     "U,s",	0x70000020, 0xfc0007ff, WR_d|RD_s,	I32	},
  {"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC,	I1	},
  {"ctc1",    "t,G",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
  {"ctc1",    "t,S",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
***************
*** 365,371 ****
  /* dctr and dctw are used on the r5000.  */
  {"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,	I3	},
  {"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,	I3	},
! {"deret",   "",         0x4200001f, 0xffffffff,    0,	G2|M1|P4	},
  /* For ddiv, see the comments about div.  */
  {"ddiv",    "z,s,t",	0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,	I3	},
  {"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,	I3	},
--- 363,369 ----
  /* dctr and dctw are used on the r5000.  */
  {"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,	I3	},
  {"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,	I3	},
! {"deret",   "",         0x4200001f, 0xffffffff,    0,	G2|M1|I32	},
  /* For ddiv, see the comments about div.  */
  {"ddiv",    "z,s,t",	0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,	I3	},
  {"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,	I3	},
***************
*** 437,443 ****
  {"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,	I3	},
  {"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,	I3	},
  {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,	I3	},
! {"eret",    "",		0x42000018, 0xffffffff,	0,	I3|M1|P4	},
  {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
  {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
  {"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
--- 435,441 ----
  {"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,	I3	},
  {"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,	I3	},
  {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,	I3	},
! {"eret",    "",		0x42000018, 0xffffffff,	0,	I3|M1|I32	},
  {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
  {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
  {"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
***************
*** 534,562 ****
  {"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,	I3	},
  {"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,	I3	},
  {"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,	I4	},
! {"mad",	    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3|P4	},
! {"madu",    "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3|P4	},
  {"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I4	},
  {"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
  {"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
  {"madd",    "s,t",	0x0000001c, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
! {"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
  {"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	        G1|M1	},
  {"madd",    "d,s,t",	0x70000000, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1	},
  {"maddu",   "s,t",	0x0000001d, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
! {"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
  {"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	G1|M1},
  {"maddu",   "d,s,t",	0x70000001, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1},
  {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	V1	},
  {"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,	I1	},
! {"mfc0",    "t,G,H",	0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,	P4	},
  {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
  {"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
! {"mfc1",    "t,G,H",	0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S,	P4},
  {"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
! {"mfc2",    "t,G,H",	0x48000000, 0xffe007f8,	LCD|WR_t|RD_C2,	P4	},
  {"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,	I1	},
! {"mfc3",    "t,G,H",	0x4c000000, 0xffe007f8,	LCD|WR_t|RD_C3,	P4	},
  {"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,	I1	},
  {"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,	I1	},
  {"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,	I1	},
--- 532,560 ----
  {"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,	I3	},
  {"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,	I3	},
  {"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,	I4	},
! {"mad",	    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3|I32	},
! {"madu",    "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3|I32	},
  {"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I4	},
  {"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
  {"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
  {"madd",    "s,t",	0x0000001c, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
! {"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	I32	},
  {"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	        G1|M1	},
  {"madd",    "d,s,t",	0x70000000, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1	},
  {"maddu",   "s,t",	0x0000001d, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
! {"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	I32	},
  {"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	G1|M1},
  {"maddu",   "d,s,t",	0x70000001, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1},
  {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	V1	},
  {"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,	I1	},
! {"mfc0",    "t,G,H",	0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,	I32	},
  {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
  {"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
! {"mfc1",    "t,G,H",	0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S,	I32},
  {"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
! {"mfc2",    "t,G,H",	0x48000000, 0xffe007f8,	LCD|WR_t|RD_C2,	I32	},
  {"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,	I1	},
! {"mfc3",    "t,G,H",	0x4c000000, 0xffe007f8,	LCD|WR_t|RD_C3,	I32	},
  {"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,	I1	},
  {"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,	I1	},
  {"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,	I1	},
***************
*** 566,572 ****
  {"movf.d",  "D,S,N",	0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
  {"movf.s",  "D,S,N",	0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
  {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5	},
! {"movn",    "d,v,t",	0x0000000b, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1|P4	},
  {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,L1	},
  {"movn.d",  "D,S,t",	0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
  {"movn.s",  "D,S,t",	0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
--- 564,570 ----
  {"movf.d",  "D,S,N",	0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
  {"movf.s",  "D,S,N",	0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
  {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5	},
! {"movn",    "d,v,t",	0x0000000b, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1|I32	},
  {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,L1	},
  {"movn.d",  "D,S,t",	0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
  {"movn.s",  "D,S,t",	0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
***************
*** 574,580 ****
  {"movt.d",  "D,S,N",	0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
  {"movt.s",  "D,S,N",	0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
  {"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5},
! {"movz",    "d,v,t",	0x0000000a, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1|P4	},
  {"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,L1	},
  {"movz.d",  "D,S,t",	0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
  {"movz.s",  "D,S,t",	0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
--- 572,578 ----
  {"movt.d",  "D,S,N",	0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
  {"movt.s",  "D,S,N",	0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
  {"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5},
! {"movz",    "d,v,t",	0x0000000a, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1|I32	},
  {"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,L1	},
  {"movz.d",  "D,S,t",	0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
  {"movz.s",  "D,S,t",	0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
***************
*** 583,606 ****
  {"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
  {"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
  {"msub",    "s,t",	0x0000001e, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
! {"msub",    "s,t",	0x70000004, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
  {"msubu",   "s,t",	0x0000001f, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
! {"msubu",   "s,t",	0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
  {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	I1	},
! {"mtc0",    "t,G,H",	0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,	P4	},
  {"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
  {"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
! {"mtc1",    "t,G,H",	0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S,	P4	},
  {"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	I1	},
! {"mtc2",    "t,G,H",	0x48800000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,	P4	},
  {"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	I1	},
! {"mtc3",    "t,G,H",	0x4c800000, 0xffe007f8,	COD|RD_t|WR_C3|WR_CC,	P4	},
  {"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,	I1	},
  {"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,	I1	},
  {"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},
  {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
  {"mul.ps",  "D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
! {"mul",     "d,v,t",	0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,	P3|P4	},
  {"mul",     "d,v,t",	0,    (int) M_MUL,	INSN_MACRO,	I1	},
  {"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,	I1	},
  {"mulo",    "d,v,t",	0,    (int) M_MULO,	INSN_MACRO,	I1	},
--- 581,604 ----
  {"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
  {"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
  {"msub",    "s,t",	0x0000001e, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
! {"msub",    "s,t",	0x70000004, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	I32	},
  {"msubu",   "s,t",	0x0000001f, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
! {"msubu",   "s,t",	0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	I32	},
  {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	I1	},
! {"mtc0",    "t,G,H",	0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,	I32	},
  {"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
  {"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
! {"mtc1",    "t,G,H",	0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S,	I32	},
  {"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	I1	},
! {"mtc2",    "t,G,H",	0x48800000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,	I32	},
  {"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	I1	},
! {"mtc3",    "t,G,H",	0x4c800000, 0xffe007f8,	COD|RD_t|WR_C3|WR_CC,	I32	},
  {"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,	I1	},
  {"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,	I1	},
  {"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},
  {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
  {"mul.ps",  "D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
! {"mul",     "d,v,t",	0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,	P3|I32	},
  {"mul",     "d,v,t",	0,    (int) M_MUL,	INSN_MACRO,	I1	},
  {"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,	I1	},
  {"mulo",    "d,v,t",	0,    (int) M_MULO,	INSN_MACRO,	I1	},
***************
*** 670,676 ****
  {"sdbbp",   "",		0x0000000e, 0xffffffff,	TRAP,           G2|M1	},
  {"sdbbp",   "c",	0x0000000e, 0xfc00ffff,	TRAP,		G2|M1	},
  {"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,		G2|M1	},
! {"sdbbp",   "B",	0x7000003f, 0xfc00003f, TRAP,		P4	},
  {"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
  {"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
  {"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,	I2	},
--- 668,674 ----
  {"sdbbp",   "",		0x0000000e, 0xffffffff,	TRAP,           G2|M1	},
  {"sdbbp",   "c",	0x0000000e, 0xfc00ffff,	TRAP,		G2|M1	},
  {"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,		G2|M1	},
! {"sdbbp",   "B",	0x7000003f, 0xfc00003f, TRAP,		I32	},
  {"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
  {"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
  {"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,	I2	},
***************
*** 778,787 ****
  {"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
  {"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,	I2		}, /* tgeiu */
  {"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,	I2	},
! {"tlbp",    "",		0x42000008, 0xffffffff,	INSN_TLB,	I1|M1|P4	},
! {"tlbr",    "",		0x42000001, 0xffffffff,	INSN_TLB,	I1|M1|P4	},
! {"tlbwi",   "",		0x42000002, 0xffffffff,	INSN_TLB,	I1|M1|P4	},
! {"tlbwr",   "",		0x42000006, 0xffffffff,	INSN_TLB,	I1|M1|P4	},
  {"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,	I2		},
  {"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	 },
  {"tlt",     "s,t,q",	0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
--- 776,785 ----
  {"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
  {"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,	I2		}, /* tgeiu */
  {"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,	I2	},
! {"tlbp",    "",		0x42000008, 0xffffffff,	INSN_TLB,	I1|M1|I32	},
! {"tlbr",    "",		0x42000001, 0xffffffff,	INSN_TLB,	I1|M1|I32	},
! {"tlbwi",   "",		0x42000002, 0xffffffff,	INSN_TLB,	I1|M1|I32	},
! {"tlbwr",   "",		0x42000006, 0xffffffff,	INSN_TLB,	I1|M1|I32	},
  {"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,	I2		},
  {"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	 },
  {"tlt",     "s,t,q",	0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
***************
*** 822,829 ****
  {"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
  {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,	I1	},
  {"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,	I1	},
! {"wait",    "",		0x42000020, 0xffffffff,	TRAP,	I3|M1|P4	},
! {"wait",    "J",	0x42000020, 0xfe00003f,	TRAP,	P4	},
  {"waiti",   "",		0x42000020, 0xffffffff,	TRAP,	L1	},
  {"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,	L1	},
  /* No hazard protection on coprocessor instructions--they shouldn't
--- 820,827 ----
  {"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
  {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,	I1	},
  {"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,	I1	},
! {"wait",    "",		0x42000020, 0xffffffff,	TRAP,	I3|M1|I32	},
! {"wait",    "J",	0x42000020, 0xfe00003f,	TRAP,	I32	},
  {"waiti",   "",		0x42000020, 0xffffffff,	TRAP,	L1	},
  {"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,	L1	},
  /* No hazard protection on coprocessor instructions--they shouldn't



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