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[updated patch] adding MIPS5 and MIPS64 ISA recognition support


This is a rework of the patches submitted with subject:

    [patch] addition of MIPS V and MIPS64 option recognition support

As with the previous patch reworking my MIPS32 ISA support
(http://sources.redhat.com/ml/binutils/2000-10/msg00191.html), i've
gone from expressing a generic CPU in the ELF headers to specifying
just the ISA in the ELF headers, and using a dummy CPU only
internally.


Patch below applies in src, changelogs broken out by directories.

tested on sparc-solaris host, targets mips-elf, mip64-elf, and
mips-linux.  No new failures.


chris
=============================================================================

ChangeLog for bfd:

2000-10-16  Chris Demetriou  <cgd@sibyte.com>

	* aoutx.h (NAME(aout,machine_type)): Add cases for
	bfd_mach_mips5 and bfd_mach_mips64.
	* archures.c (bfd_mach_mips5, bfd_mach_mips64): New constants.
	* bfd-in2.h (bfd_mach_mips5, bfd_mach_mips64): Likewise.
        * cpu_mips.c (I_mips5, I_mips64): New definitions.
        (arch_info_struct): Add entries for bfd_mach_mips5 and
        bfd_mach_mips64.
        * elf32-mips.c (elf_mips_isa, elf_mips_mach,
	_bfd_mips_elf_print_private_bfd_data): Add cases for
	E_MIPS_ARCH_5 and E_MIPS_ARCH_64.
        (_bfd_mips_elf_final_write_processing): Add cases for
        bfd_mach_mips5 and bfd_mach_mips64.


ChangeLog for binutils:

2000-10-16  Chris Demetriou  <cgd@sibyte.com>

        * readelf.c (get_machine_flags): Add cases for E_MIPS_ARCH_5,
	and E_MIPS_ARCH_64.


ChangeLog for gas:

2000-10-16  Chris Demetriou  <cgd@sibyte.com>

        * tc-mips.c (ISA_HAS_64BIT_REGS): Add checks for ISA_MIPS5 and
        ISA_MIPS64.
        (md_longopts, OPTION_MIPS5, OPTION_MIPS64): Add options for
        -mips5 and -mips64.
        (md_parse_option): Add cases for OPTION_MIPS5 and
        OPTION_MIPS64.
        (md_show_usage): Mention -mips5 and -mips64 arguments.
        (s_mipsset): Add cases for MIPS5 and MIPS64.
        (mips_cpu_info_table): Add entries for MIPS5 and MIPS64 ISAs
	and pseudo-CPUs.
        * doc/as.texinfo: Mention -mips5 and -mips64 options
        and their meanings.
        * doc/c-mips.texi: Likewise.  Also update introduction
        and ".set" usage information.


ChangeLog for include/elf:

2000-10-16  Chris Demetriou  <cgd@sibyte.com>

        * mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions.


ChangeLog for include/opcode:

2000-10-16  Chris Demetriou  <cgd@sibyte.com>

        * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
	definitions. 


ChangeLog for opcodes:

2000-10-16  Chris Demetriou  <cgd@sibyte.com>

        * mips-dis.c (set_mips_isa_type): Add cases for
        bfd_mach_mips5 and bfd_mach_mips64.
        * mips-opc.c (I64): New definitions.



diff -rcp ../src.P07/bfd/aoutx.h ./bfd/aoutx.h
*** ../src.P07/bfd/aoutx.h	Mon Oct 16 16:01:28 2000
--- ./bfd/aoutx.h	Mon Oct 16 16:27:11 2000
*************** NAME(aout,machine_type) (arch, machine, 
*** 780,785 ****
--- 780,787 ----
      case bfd_mach_mips16:
      case bfd_mach_mips32:
      case bfd_mach_mips32_4k:
+     case bfd_mach_mips5:
+     case bfd_mach_mips64:
        /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc.  */
        arch_flags = M_MIPS2;
        break;
diff -rcp ../src.P07/bfd/archures.c ./bfd/archures.c
*** ../src.P07/bfd/archures.c	Mon Oct 16 16:01:31 2000
--- ./bfd/archures.c	Mon Oct 16 16:27:32 2000
*************** DESCRIPTION
*** 130,135 ****
--- 130,137 ----
  .#define bfd_mach_mips16		16
  .#define bfd_mach_mips32		32
  .#define bfd_mach_mips32_4k		3204113	{* 32, 04, octal 'K' *}
+ .#define bfd_mach_mips5			5
+ .#define bfd_mach_mips64		64
  .  bfd_arch_i386,      {* Intel 386 *}
  .#define bfd_mach_i386_i386 0
  .#define bfd_mach_i386_i8086 1
diff -rcp ../src.P07/bfd/bfd-in2.h ./bfd/bfd-in2.h
*** ../src.P07/bfd/bfd-in2.h	Mon Oct 16 16:01:33 2000
--- ./bfd/bfd-in2.h	Mon Oct 16 16:27:59 2000
*************** enum bfd_architecture 
*** 1400,1405 ****
--- 1400,1407 ----
  #define bfd_mach_mips16                16
  #define bfd_mach_mips32		       32
  #define bfd_mach_mips32_4k	       3204113	/* 32, 04, octal 'K' */
+ #define bfd_mach_mips5		       5
+ #define bfd_mach_mips64		       64
    bfd_arch_i386,      /* Intel 386 */
  #define bfd_mach_i386_i386 0
  #define bfd_mach_i386_i8086 1
diff -rcp ../src.P07/bfd/cpu-mips.c ./bfd/cpu-mips.c
*** ../src.P07/bfd/cpu-mips.c	Mon Oct 16 16:01:34 2000
--- ./bfd/cpu-mips.c	Mon Oct 16 16:29:10 2000
*************** I_mips10000,
*** 56,61 ****
--- 56,63 ----
  I_mips16,
  I_mips32,
  I_mips32_4k,
+ I_mips5,
+ I_mips64,
  };
  
  
*************** static const bfd_arch_info_type arch_inf
*** 79,85 ****
    N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
    N (64, 64, bfd_mach_mips16,   "mips:16",   false, NN(I_mips16)),
    N (32, 32, bfd_mach_mips32,   "mips:mips32",   false, NN(I_mips32)),
!   N (32, 32, bfd_mach_mips32_4k, "mips:mips32-4k", false, 0),
  };
  
  /* The default architecture is mips:3000, but with a machine number of
--- 81,89 ----
    N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
    N (64, 64, bfd_mach_mips16,   "mips:16",   false, NN(I_mips16)),
    N (32, 32, bfd_mach_mips32,   "mips:mips32",   false, NN(I_mips32)),
!   N (32, 32, bfd_mach_mips32_4k, "mips:mips32-4k", false, NN(I_mips32_4k)),
!   N (64, 64, bfd_mach_mips5,    "mips:mips5", false, NN(I_mips5)),
!   N (64, 64, bfd_mach_mips64,   "mips:mips64", false, 0),
  };
  
  /* The default architecture is mips:3000, but with a machine number of
diff -rcp ../src.P07/bfd/elf32-mips.c ./bfd/elf32-mips.c
*** ../src.P07/bfd/elf32-mips.c	Mon Oct 16 16:01:36 2000
--- ./bfd/elf32-mips.c	Mon Oct 16 16:31:41 2000
*************** elf_mips_isa (flags)
*** 1821,1828 ****
--- 1821,1832 ----
        return 3;
      case E_MIPS_ARCH_4:
        return 4;
+     case E_MIPS_ARCH_5:
+       return 5;
      case E_MIPS_ARCH_32:
        return 32;
+     case E_MIPS_ARCH_64:
+       return 64;
      }
    return 4;
  }
*************** elf_mips_mach (flags)
*** 1873,1881 ****
--- 1877,1893 ----
  	  return bfd_mach_mips8000;
  	  break;
  
+ 	case E_MIPS_ARCH_5:
+ 	  return bfd_mach_mips5;
+ 	  break;
+ 
  	case E_MIPS_ARCH_32:
  	  return bfd_mach_mips32;
  	  break;
+ 
+ 	case E_MIPS_ARCH_64:
+ 	  return bfd_mach_mips64;
+ 	  break;
  	}
      }
  
*************** _bfd_mips_elf_final_write_processing (ab
*** 2364,2369 ****
--- 2376,2389 ----
      case bfd_mach_mips32_4k:
        val = E_MIPS_ARCH_32 | E_MIPS_MACH_MIPS32_4K;
        break;
+ 
+     case bfd_mach_mips5:
+       val = E_MIPS_ARCH_5;
+       break;
+ 
+     case bfd_mach_mips64:
+       val = E_MIPS_ARCH_64;
+       break;
      }
  
    elf_elfheader (abfd)->e_flags &= ~ (EF_MIPS_ARCH | EF_MIPS_MACH);
*************** _bfd_mips_elf_print_private_bfd_data (ab
*** 2671,2678 ****
--- 2691,2702 ----
      fprintf (file, _ (" [mips3]"));
    else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
      fprintf (file, _ (" [mips4]"));
+   else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_5)
+     fprintf (file, _ (" [mips5]"));
    else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
      fprintf (file, _ (" [mips32]"));
+   else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
+     fprintf (file, _ (" [mips64]"));
    else
      fprintf (file, _ (" [unknown ISA]"));
  
diff -rcp ../src.P07/binutils/readelf.c ./binutils/readelf.c
*** ../src.P07/binutils/readelf.c	Mon Oct 16 16:01:38 2000
--- ./binutils/readelf.c	Mon Oct 16 16:32:04 2000
*************** get_machine_flags (e_flags, e_machine)
*** 1462,1469 ****
--- 1462,1475 ----
  	  if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
  	    strcat (buf, ", mips4");
  
+ 	  if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_5)
+ 	    strcat (buf, ", mips5");
+ 
  	  if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
  	    strcat (buf, ", mips32");
+ 
+ 	  if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
+ 	    strcat (buf, ", mips64");
  
  	  switch ((e_flags & EF_MIPS_MACH))
  	    {
diff -rcp ../src.P07/gas/config/tc-mips.c ./gas/config/tc-mips.c
*** ../src.P07/gas/config/tc-mips.c	Mon Oct 16 16:01:40 2000
--- ./gas/config/tc-mips.c	Mon Oct 16 16:35:44 2000
*************** static int mips_gp32 = 0;
*** 238,243 ****
--- 238,245 ----
  #define ISA_HAS_64BIT_REGS(ISA) (    \
     (ISA) == ISA_MIPS3                \
     || (ISA) == ISA_MIPS4             \
+    || (ISA) == ISA_MIPS5             \
+    || (ISA) == ISA_MIPS32            \
     )
  
  /* Whether the processor uses hardware interlocks to protect
*************** struct option md_longopts[] =
*** 8884,8889 ****
--- 8886,8895 ----
    {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
  #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
    {"mips32", no_argument, NULL, OPTION_MIPS32},
+ #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
+   {"mips5", no_argument, NULL, OPTION_MIPS5},
+ #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
+   {"mips64", no_argument, NULL, OPTION_MIPS64},
  #ifdef OBJ_ELF
  #define OPTION_ELF_BASE    (OPTION_MD_BASE + 35)
  #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
*************** md_parse_option (c, arg)
*** 8969,8978 ****
--- 8975,8992 ----
        mips_opts.isa = ISA_MIPS4;
        break;
  
+     case OPTION_MIPS5:
+       mips_opts.isa = ISA_MIPS5;
+       break;
+ 
      case OPTION_MIPS32:
        mips_opts.isa = ISA_MIPS32;
        break;
  
+     case OPTION_MIPS64:
+       mips_opts.isa = ISA_MIPS64;
+       break;
+ 
      case OPTION_MCPU:
        {
  
*************** MIPS options:\n\
*** 9207,9213 ****
--- 9221,9229 ----
  -mips2			generate MIPS ISA II instructions\n\
  -mips3			generate MIPS ISA III instructions\n\
  -mips4			generate MIPS ISA IV instructions\n\
+ -mips5			generate MIPS ISA V instructions\n\
  -mips32			generate MIPS32 ISA instructions\n\
+ -mips64			generate MIPS64 ISA instructions\n\
  -mcpu=CPU		generate code for CPU, where CPU is one of:\n"));
  
    first = 1;
*************** s_mipsset (x)
*** 10250,10258 ****
--- 10266,10280 ----
  	case 4:
  	  mips_opts.isa = ISA_MIPS4;
  	  break;
+ 	case 5:
+ 	  mips_opts.isa = ISA_MIPS5;
+ 	  break;
  	case 32:
  	  mips_opts.isa = ISA_MIPS32;
  	  break;
+ 	case 64:
+ 	  mips_opts.isa = ISA_MIPS64;
+ 	  break;
  	default:
  	  as_bad (_("unknown ISA level"));
  	  break;
*************** static const struct mips_cpu_info mips_c
*** 11927,11938 ****
--- 11949,11971 ----
    /* MIPS4 ISA */
    { "MIPS4",		1,	ISA_MIPS4,	CPU_R8000, },
  
+   /* MIPS5 ISA */
+   { "MIPS5",		1,	ISA_MIPS5,	CPU_MIPS5, },
+   { "Generic-MIPS5",	0,	ISA_MIPS5,	CPU_MIPS5, },
+ 
    /* MIPS32 ISA */
    { "MIPS32",		1,	ISA_MIPS32,	CPU_MIPS32, },
    { "Generic-MIPS32",	0,	ISA_MIPS32,	CPU_MIPS32, },
  
+ #if 1
    /* XXX for now, MIPS64 -> MIPS3 because of history */
    { "MIPS64",		1,	ISA_MIPS3,	CPU_R4000 }, /* XXX! */
+ #else
+   /* MIPS64 ISA */
+   { "MIPS64",		1,	ISA_MIPS64,	CPU_MIPS64 },
+ #endif
+   { "mips64isa",	1,	ISA_MIPS64,	CPU_MIPS64 },
+   { "Generic-MIPS64",	0,	ISA_MIPS64,	CPU_MIPS64, },
  
    /* R2000 CPU */
    { "R2000",		0,	ISA_MIPS1,	CPU_R2000, },
diff -rcp ../src.P07/gas/doc/as.texinfo ./gas/doc/as.texinfo
*** ../src.P07/gas/doc/as.texinfo	Mon Oct 16 16:01:42 2000
--- ./gas/doc/as.texinfo	Mon Oct 16 16:37:01 2000
*************** Here is a brief summary of how to invoke
*** 278,284 ****
  @end ifset
  @ifset MIPS
   [ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
!  [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips32 ]
   [ -m4650 ] [ -no-m4650 ]
   [ --trap ] [ --break ]
   [ --emulation=@var{name} ]
--- 278,285 ----
  @end ifset
  @ifset MIPS
   [ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
!  [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips5 ]
!  [ -mips32 ] [ -mips64 ]
   [ -m4650 ] [ -no-m4650 ]
   [ --trap ] [ --break ]
   [ --emulation=@var{name} ]
*************** Generate ``little endian'' format output
*** 672,679 ****
  @itemx -mips32
  Generate code for a particular MIPS Instruction Set Architecture level.
  @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
! @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000}
! processor, @samp{-mips32} to a generic @sc{MIPS32} processor.
  
  @item -m4650
  @itemx -no-m4650
--- 673,683 ----
  @itemx -mips32
  Generate code for a particular MIPS Instruction Set Architecture level.
  @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
! @samp{-mips2} to the @sc{r6000} processor, and @samp{-mips3} to the @sc{r4000}
! processor.
! @samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
! to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
! processors, respectively.
  
  @item -m4650
  @itemx -no-m4650
diff -rcp ../src.P07/gas/doc/c-mips.texi ./gas/doc/c-mips.texi
*** ../src.P07/gas/doc/c-mips.texi	Mon Oct 16 16:01:44 2000
--- ./gas/doc/c-mips.texi	Mon Oct 16 16:38:42 2000
***************
*** 13,19 ****
  
  @cindex MIPS processor
  @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
! different @sc{mips} processors, and MIPS ISA levels I through IV.  For
  information about the @sc{mips} instruction set, see @cite{MIPS RISC
  Architecture}, by Kane and Heindrich (Prentice-Hall).  For an overview
  of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
--- 13,20 ----
  
  @cindex MIPS processor
  @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
! different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
! and MIPS64.  For
  information about the @sc{mips} instruction set, see @cite{MIPS RISC
  Architecture}, by Kane and Heindrich (Prentice-Hall).  For an overview
  of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
*************** to select big-endian output, and @samp{-
*** 60,72 ****
  @itemx -mips2
  @itemx -mips3
  @itemx -mips4
  @itemx -mips32
  Generate code for a particular MIPS Instruction Set Architecture level.
  @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
  @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
! @sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and
! @sc{r10000} processors, and @samp{-mips32} to a generic @sc(MIPS32)
! processor.  You can also switch instruction sets during the
  assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
  
  @item -mgp32
--- 61,78 ----
  @itemx -mips2
  @itemx -mips3
  @itemx -mips4
+ @itemx -mips5
  @itemx -mips32
+ @itemx -mips64
  Generate code for a particular MIPS Instruction Set Architecture level.
  @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
  @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
! @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
! @sc{r10000} processors.
! @samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
! to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
! processors, respectively.
! You can also switch instruction sets during the
  assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
  
  @item -mgp32
*************** assembly language programmers!
*** 239,246 ****
  @kindex @code{.set mips@var{n}}
  @sc{gnu} @code{@value{AS}} supports an additional directive to change
  the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
! mips@var{n}}.  @var{n} should be a number from 0 to 4, or 32.  The values 1
! to 4 and 32 make the assembler accept instructions for the corresponding
  @sc{isa} level, from that point on in the assembly.  @code{.set
  mips@var{n}} affects not only which instructions are permitted, but also
  how certain macros are expanded.  @code{.set mips0} restores the
--- 245,253 ----
  @kindex @code{.set mips@var{n}}
  @sc{gnu} @code{@value{AS}} supports an additional directive to change
  the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
! mips@var{n}}.  @var{n} should be a number from 0 to 5, or 32 or 64.
! The values 1 to 5, 32, and 64 make the assembler accept instructions
! for the corresponding
  @sc{isa} level, from that point on in the assembly.  @code{.set
  mips@var{n}} affects not only which instructions are permitted, but also
  how certain macros are expanded.  @code{.set mips0} restores the
diff -rcp ../src.P07/include/elf/mips.h ./include/elf/mips.h
*** ../src.P07/include/elf/mips.h	Mon Oct 16 16:01:46 2000
--- ./include/elf/mips.h	Mon Oct 16 16:39:28 2000
*************** END_RELOC_NUMBERS (R_MIPS_maxext)
*** 121,128 ****
--- 121,134 ----
  /* -mips4 code.  */
  #define E_MIPS_ARCH_4		0x30000000
  
+ /* -mips5 code.  */
+ #define E_MIPS_ARCH_5		0x40000000
+ 
  /* -mips32 code.  */
  #define E_MIPS_ARCH_32		0x50000000
+ 
+ /* -mips64 code.  */
+ #define E_MIPS_ARCH_64		0x60000000
  
  /* The ABI of the file.  Also see EF_MIPS_ABI2 above. */
  #define EF_MIPS_ABI		0x0000F000
diff -rcp ../src.P07/include/opcode/mips.h ./include/opcode/mips.h
*** ../src.P07/include/opcode/mips.h	Mon Oct 16 16:01:48 2000
--- ./include/opcode/mips.h	Mon Oct 16 16:40:24 2000
*************** struct mips_opcode
*** 314,319 ****
--- 314,320 ----
  #define INSN_ISA4		    0x00000080
  #define INSN_ISA5		    0x00000100
  #define INSN_ISA32		    0x00000200
+ #define INSN_ISA64		    0x00000400
  
  /* Chip specific instructions.  These are bitmasks.  */
  /* MIPS R4650 instruction.  */
*************** struct mips_opcode
*** 333,339 ****
--- 334,342 ----
  #define	ISA_MIPS2	(ISA_MIPS1 | INSN_ISA2)
  #define	ISA_MIPS3	(ISA_MIPS2 | INSN_ISA3)
  #define	ISA_MIPS4	(ISA_MIPS3 | INSN_ISA4)
+ #define	ISA_MIPS5	(ISA_MIPS4 | INSN_ISA5)
  #define	ISA_MIPS32	(ISA_MIPS2 | INSN_ISA32)
+ #define	ISA_MIPS64	(ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
  
  
  /* CPU defines, use instead of hardcoding processor number. Keep this
*************** struct mips_opcode
*** 357,362 ****
--- 360,367 ----
  #define CPU_MIPS16	16
  #define CPU_MIPS32	32
  #define CPU_MIPS32_4K	3204113		/* 32, 04, octal 'K' */
+ #define CPU_MIPS5	5
+ #define CPU_MIPS64	64
  
  /* Test for membership in an ISA including chip specific ISAs.
     INSN is pointer to an element of the opcode table; ISA is the
diff -rcp ../src.P07/opcodes/mips-dis.c ./opcodes/mips-dis.c
*** ../src.P07/opcodes/mips-dis.c	Mon Oct 16 16:01:49 2000
--- ./opcodes/mips-dis.c	Mon Oct 16 16:40:57 2000
*************** set_mips_isa_type (mach, isa, cputype)
*** 365,370 ****
--- 365,378 ----
        target_processor = CPU_MIPS32_4K;
        mips_isa = ISA_MIPS32;
        break;
+     case bfd_mach_mips5:
+       target_processor = CPU_MIPS5;
+       mips_isa = ISA_MIPS5;
+       break;
+     case bfd_mach_mips64:
+       target_processor = CPU_MIPS64;
+       mips_isa = ISA_MIPS64;
+       break;
      default:
        target_processor = CPU_R3000;
        mips_isa = ISA_MIPS3;
diff -rcp ../src.P07/opcodes/mips-opc.c ./opcodes/mips-opc.c
*** ../src.P07/opcodes/mips-opc.c	Mon Oct 16 16:01:51 2000
--- ./opcodes/mips-opc.c	Mon Oct 16 16:41:13 2000
*************** Software Foundation, 59 Temple Place - S
*** 78,83 ****
--- 78,84 ----
  #define I4	INSN_ISA4
  #define I5	INSN_ISA5
  #define I32	INSN_ISA32
+ #define I64	INSN_ISA64
  
  #define P3	INSN_4650
  #define L1	INSN_4010

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