This is the mail archive of the
binutils@sources.redhat.com
mailing list for the binutils project.
mips instructions
- To: binutils at sources dot redhat dot com
- Subject: mips instructions
- From: Eric Christopher <echristo at redhat dot com>
- Date: Mon, 18 Dec 2000 23:45:28 -0800
Okay, I've been looking through the new mips32 and 64 isas. I've found
a few instructions in opcodes/mips-opc.c that I can't find a description
for anywhere:
mfc2
mfc3
mtc2
mtc3
These are part of the original mips1 spec, but I can't find them in the
new spec anywhere. Did I just miss the part where it said that all
original mips1 instructions were supported?
I also noticed that the mul instruction was using a v as the second
arg. From what I can see in include/opcodes/mips.h that is for an arg
that is both source and dest. I think it is merely a source register.
I made a patch just in case. :)
-eric
2000-12-18 Eric Christopher <echristo@redhat.com>
* mips-opc.c: Second arg for mul instruction should be s for I32.
Index: mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.19
diff -u -p -w -r1.19 mips-opc.c
--- mips-opc.c 2000/12/12 19:19:57 1.19
+++ mips-opc.c 2000/12/19 08:31:31
@@ -607,7 +607,7 @@ const struct mips_opcode mips_builtin_op
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
-{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3 },
+{"mul", "d,s,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3 },
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
@@ -863,4 +863,3 @@ struct mips_opcode *mips_opcodes =
(struct mips_opcode *) mips_builtin_opcodes;
int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
#undef MIPS_NUM_OPCODES
-