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Re: mips instructions
- To: echristo at redhat dot com
- Subject: Re: mips instructions
- From: Ian Lance Taylor <ian at zembu dot com>
- Date: 19 Dec 2000 09:29:38 -0800
- CC: binutils at sources dot redhat dot com
- References: <3A3F1218.FE219171@redhat.com>
Date: Mon, 18 Dec 2000 23:45:28 -0800
From: Eric Christopher <echristo@redhat.com>
Okay, I've been looking through the new mips32 and 64 isas. I've found
a few instructions in opcodes/mips-opc.c that I can't find a description
for anywhere:
mfc2
mfc3
mtc2
mtc3
These are part of the original mips1 spec, but I can't find them in the
new spec anywhere. Did I just miss the part where it said that all
original mips1 instructions were supported?
I have a vague recollection that MIPS took the bit definitions for
these coprocessor instructions and defined them as new instructions.
Take a look at the bit patterns for the new instructions, and see if
they overlap with these.
I also noticed that the mul instruction was using a v as the second
arg. From what I can see in include/opcodes/mips.h that is for an arg
that is both source and dest. I think it is merely a source register.
Your patch is wrong. The comment in mips.h may be misleading. A `v'
means that if the instruction is used with only two registers, the
source register operand should be used as the destination register.
That is, it permits writing `mul $2,$4'; this is equivalent to `mul
$2,$2,$4'. The `r', `w', `V', and `W' operand specifiers are
similar.
Ian