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Re: binutils patch
Daniel Egger <egger@suse.de> writes:
|> Am 17 Aug 2001 10:26:32 +0200 schrieb Andreas Schwab:
|>
|> > The comment before the table says:
|> >
|> > The disassembler reads the table in order and prints the first
|> > instruction which matches, so this table is sorted to put more
|> > specific instructions before more general instructions. It is also
|> > sorted by major opcode.
|>
|> DOH! Thanks for pointing that out.
|>
|> > Try to swap the lines in the pairs with X_MASK vs XT_MASK, so that the
|> > disassembler matches the transparent form before the non-transparent form.
|>
|> However it still doesn't work.
|>
|> The dissabled code reads:
|> fe8: 7c 04 02 ec dststt r4,r0,0
|> fec: 3d 20 01 08 lis r9,264
|> ff0: 61 29 00 10 ori r9,r9,16
|> ff4: 7c 23 4a ac dstt r3,r9,1
|> Unfortunately it's wrong:
|> fe8 should be: 7e 04 02 ec
|> and the opcode of ff4 is correct but the mnemonic should read dst.
I think you want an XT macro that lets you specify the T bit in the
opcode:
#define XT(op, xop, t) (X (op, xop) | (((unsigned long)(t) & 1) << 25))
#define T_MASK ((unsigned long)1 << 25)
#define XT_MASK (X_MASK | T_MASK)
{ "dss", XT(31,822,0), XT_MASK, PPCVEC, { STRM } },
{ "dssall", XT(31,822,1), XT_MASK, PPCVEC, { STRM } },
{ "dst", XT(31,342,0), XT_MASK, PPCVEC, { RA, RB, STRM } },
{ "dstt", XT(31,342,1), XT_MASK, PPCVEC, { RA, RB, STRM } },
{ "dstst", XT(31,374,0), XT_MASK, PPCVEC, { RA, RB, STRM } },
{ "dststt", XT(31,374,1), XT_MASK, PPCVEC, { RA, RB, STRM } },
Andreas.
--
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