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[PATCH]: Fix 68HC11/68HC12 assembler relocation across frags


Hi!

I found a nasty problem with HC11 assembler and variable frags.  A jump instruction
uses a variable frag for the relaxation to use 1 byte or 2 byte branch.
When the 2 byte branch is chosen, a 16-bit offset can be padded by md_apply_fix.  
This 16-bit offset can come accross two frags and thus the two bytes are not
contiguous.  This results in a truncation.

I've changed the frag_var() to use frag_variant() and make sure the frag
is large enough when the jump instruction is created.

I've committed on mainline and branch.

	Stephane

2001-11-01  Stephane Carrez  <Stephane.Carrez@worldnet.fr>

	* config/tc-m68hc11.c (build_jump_insn): Allocate worst case storage
	for bra/bsr and use frag_variant(), this ensure that the possible
	16-bit BFD_RELOC_16 will be in the same frag.
Index: config/tc-m68hc11.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-m68hc11.c,v
retrieving revision 1.21
diff -u -p -r1.21 tc-m68hc11.c
--- tc-m68hc11.c	2001/09/30 09:20:55	1.21
+++ tc-m68hc11.c	2001/11/01 09:54:19
@@ -1519,12 +1519,14 @@ build_jump_insn (opcode, operands, nb_op
       /* bra/bsr made be changed into jmp/jsr.  */
       else if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
 	{
-	  opcode = m68hc11_new_insn (2);
+          /* Allocate worst case storage.  */
+	  opcode = m68hc11_new_insn (3);
 	  number_to_chars_bigendian (opcode, code, 1);
 	  number_to_chars_bigendian (opcode + 1, 0, 1);
-	  frag_var (rs_machine_dependent, 2, 1,
-		    ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF),
-		    operands[0].exp.X_add_symbol, (offsetT) n, opcode);
+	  frag_variant (rs_machine_dependent, 1, 1,
+                        ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF),
+                        operands[0].exp.X_add_symbol, (offsetT) n,
+                        opcode);
 	}
       else if (current_architecture & cpu6812)
 	{

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