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Re: Alpha and "unop" pseudo-insn
- From: Richard Henderson <rth at redhat dot com>
- To: Jason R Thorpe <thorpej at wasabisystems dot com>, binutils at sources dot redhat dot com
- Date: Mon, 17 Dec 2001 16:04:23 -0800
- Subject: Re: Alpha and "unop" pseudo-insn
- References: <20011217155332.V9607@dr-evil.shagadelic.org>
On Mon, Dec 17, 2001 at 03:53:32PM -0800, Jason R Thorpe wrote:
> GAS currently generates the following for the Alpha "unop" pseudo:
>
> ldq_u zero, 0(v0)
>
> DEC document AA-PS31D-TET1, section C.7, describes "unop" as:
>
> ldq_u zero, 0(sp)
>
> ...which is also how the Tru64 (5.0) assembler assembles it.
It's a mistake due to wanting the disassembler to match any RB,
which is how it's described in the EV5 hardware manuals.
Fixed thus.
r~
* alpha-opc.c (unop): Encode with RB as $sp.
Index: alpha-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/alpha-opc.c,v
retrieving revision 1.6
diff -c -p -d -u -r1.6 alpha-opc.c
--- alpha-opc.c 2001/12/06 18:29:22 1.6
+++ alpha-opc.c 2001/12/18 00:02:09
@@ -542,7 +542,7 @@ const struct alpha_opcode alpha_opcodes[
{ "lda", MEM(0x08), BASE, ARG_MEM },
{ "ldah", MEM(0x09), BASE, ARG_MEM },
{ "ldbu", MEM(0x0A), BWX, ARG_MEM },
- { "unop", MEM(0x0B), BASE, { ZA } }, /* pseudo */
+ { "unop", MEM(0x0B) | 30 << 16, BASE, { ZA } }, /* pseudo */
{ "ldq_u", MEM(0x0B), BASE, ARG_MEM },
{ "ldwu", MEM(0x0C), BWX, ARG_MEM },
{ "stw", MEM(0x0D), BWX, ARG_MEM },