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Re: [PATCH] : SH Assembler generates incorrect opcode for PCMP instructions
- From: Joern Rennecke <joern dot rennecke at superh dot com>
- To: Nick Clifton <nickc at cambridge dot redhat dot com>
- Cc: AratiD at kpit dot com, amylaar at onetel dot net dot uk, hp at bitrange dot com, binutils at sources dot redhat dot com
- Date: Fri, 14 Jun 2002 16:06:36 +0100
- Subject: Re: [PATCH] : SH Assembler generates incorrect opcode for PCMP instructions
- Organization: SuperH UK Ltd.
- References: <97AA06615400F34AB695F23CE3D42E9150B72D@sohm.kpit.com> <m3g04murnk.fsf@north-pole.nickc.cambridge.redhat.com>
Nick Clifton wrote:
>
> Hi Arati,
>
> > The SH assembler generates incorrect opcodes for the parallel PCMP
> > instruction. Basically, its last nibble is a copy of the previous
> > instruction's second nibble when working in Big Endian format.
That's not exactly incorrect, since the reg_n field for pcmp is
ignored by the CPU.
> Your patch does work, but I do not like the way it makes a special
> case out of the opcode's name. In fact I think that it may not be
> just the PCMP instruction that has this problem, since a perusal of
> the sh-opc.h file indicates that the PABS and PRND instructions may
> also have similar difficulties.
No, PCMP is indeed special, since it is the only PPI3 instuction that
ignores REG_N.
Moreover, REG_X and REG_Y are initialized at the start of assemble_ppi.
To get non-varying opcodes for pcmp, you can clear reg_n at that point, too.
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