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[patch] Namespace cleanup
- From: "Svein E. Seldal" <Svein dot Seldal at solidas dot com>
- To: binutils at sources dot redhat dot com
- Date: Wed, 02 Apr 2003 18:37:45 +0200
- Subject: [patch] Namespace cleanup
Hi,
I've done a major namespace cleanup in the tic4x target. Mainly it is
about replacing 'c4x' with 'tic4x' in the sources. Any objections before
I commit? [I mean, can this have sideeffects I haven't thought about?]
Svein
gas/ChangeLog:
2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
* config/obj-coff.h (TARGET_FORMAT): Namespace cleanup, changed
default tic4x target format to 'coff2-tic4x'.
* config/tc-tic4x.c: Namespace cleanup. Replace s/c4x/tic4x/ and
s/c3x/tic3x/
* config/tc-tic4x.h: Ditto
bfd/ChangeLog:
2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
* archures.c: Namespace cleanup. Rename bfd_mach_c3x to
bfd_mach_tic3x and bfd_mach_c4x to bfd_mach_tic4x
* bfd-in2.h: Regenerate
* coff-tic4x.c: Namespace cleanup. Replace s/c4x/tic4x/
* cpu-tic4x.c: Ditto
include/ChangeLog:
2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
* coff/tic4x.h: Namespace cleanup. Replace s/c4x/tic4x
and s/c3x/tic3x/
* coff/tc-tic4x.h: Ditto
* opcode/tic4x.h: Ditto
opcodes/ChangeLog:
2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
* tic4x-dis.c: Namespace cleanup. Replace s/c4x/tic4x and
s/c3x/tic3x/
ld/ChangeLog:
2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
* emulparams/tic3xcoff.sh (SCRIPT_NAME): Namespace
cleanup. Replace s/c4x/tic4x and s/c3x/tic3x/
* emulparams/tic3xcoff_onchip.sh: Ditto
* emulparams/tic4xcoff.sh: Ditto
* scripttempl/tic4xcoff.sc: Ditto
? build.c4x
? build.inst.tic4x
? build.tic4x
? gas/doc/all.texi.new
? gas/doc/as.texinfo.new
? gas/doc/c-tic4x.texi
? gas/doc/Makefile.am.new
? gas/doc/Makefile.in.new
? ld/ldlang.c.new
Index: bfd/ChangeLog
===================================================================
RCS file: /cvs/src/src/bfd/ChangeLog,v
retrieving revision 1.1983
diff -c -3 -p -r1.1983 ChangeLog
*** bfd/ChangeLog 1 Apr 2003 23:44:45 -0000 1.1983
--- bfd/ChangeLog 2 Apr 2003 16:31:49 -0000
***************
*** 1,3 ****
--- 1,11 ----
+ 2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
+
+ * archures.c: Namespace cleanup. Rename bfd_mach_c3x to
+ bfd_mach_tic3x and bfd_mach_c4x to bfd_mach_tic4x
+ * bfd-in2.h: Regenerate
+ * coff-tic4x.c: Namespace cleanup. Replace s/c4x/tic4x/
+ * cpu-tic4x.c: Ditto
+
2003-04-02 Alan Modra <amodra at bigpond dot net dot au>
* elfxx-mips.c (_bfd_mips_elf_hide_symbol): Test for NULL dynobj.
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.69
diff -c -3 -p -r1.69 archures.c
*** bfd/archures.c 1 Apr 2003 15:50:27 -0000 1.69
--- bfd/archures.c 2 Apr 2003 16:31:49 -0000
*************** DESCRIPTION
*** 241,248 ****
. bfd_arch_w65, {* WDC 65816 *}
. bfd_arch_tic30, {* Texas Instruments TMS320C30 *}
. bfd_arch_tic4x, {* Texas Instruments TMS320C3X/4X *}
! .#define bfd_mach_c3x 30
! .#define bfd_mach_c4x 40
. bfd_arch_tic54x, {* Texas Instruments TMS320C54X *}
. bfd_arch_tic80, {* TI TMS320c80 (MVP) *}
. bfd_arch_v850, {* NEC V850 *}
--- 241,248 ----
. bfd_arch_w65, {* WDC 65816 *}
. bfd_arch_tic30, {* Texas Instruments TMS320C30 *}
. bfd_arch_tic4x, {* Texas Instruments TMS320C3X/4X *}
! .#define bfd_mach_tic3x 30
! .#define bfd_mach_tic4x 40
. bfd_arch_tic54x, {* Texas Instruments TMS320C54X *}
. bfd_arch_tic80, {* TI TMS320c80 (MVP) *}
. bfd_arch_v850, {* NEC V850 *}
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.208
diff -c -3 -p -r1.208 bfd-in2.h
*** bfd/bfd-in2.h 1 Apr 2003 15:50:27 -0000 1.208
--- bfd/bfd-in2.h 2 Apr 2003 16:31:49 -0000
*************** enum bfd_architecture
*** 1707,1714 ****
bfd_arch_w65, /* WDC 65816 */
bfd_arch_tic30, /* Texas Instruments TMS320C30 */
bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */
! #define bfd_mach_c3x 30
! #define bfd_mach_c4x 40
bfd_arch_tic54x, /* Texas Instruments TMS320C54X */
bfd_arch_tic80, /* TI TMS320c80 (MVP) */
bfd_arch_v850, /* NEC V850 */
--- 1707,1714 ----
bfd_arch_w65, /* WDC 65816 */
bfd_arch_tic30, /* Texas Instruments TMS320C30 */
bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */
! #define bfd_mach_tic3x 30
! #define bfd_mach_tic4x 40
bfd_arch_tic54x, /* Texas Instruments TMS320C54X */
bfd_arch_tic80, /* TI TMS320c80 (MVP) */
bfd_arch_v850, /* NEC V850 */
Index: bfd/coff-tic4x.c
===================================================================
RCS file: /cvs/src/src/bfd/coff-tic4x.c,v
retrieving revision 1.4
diff -c -3 -p -r1.4 coff-tic4x.c
*** bfd/coff-tic4x.c 30 Nov 2002 08:39:36 -0000 1.4
--- bfd/coff-tic4x.c 2 Apr 2003 16:31:49 -0000
*************** static const bfd_coff_backend_data ticof
*** 365,371 ****
/* TI COFF v0, DOS tools (little-endian headers). */
const bfd_target tic4x_coff0_vec =
{
! "coff0-c4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
--- 365,371 ----
/* TI COFF v0, DOS tools (little-endian headers). */
const bfd_target tic4x_coff0_vec =
{
! "coff0-tic4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
*************** const bfd_target tic4x_coff0_vec =
*** 409,415 ****
/* TI COFF v0, SPARC tools (big-endian headers). */
const bfd_target tic4x_coff0_beh_vec =
{
! "coff0-beh-c4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_BIG, /* Header byte order is big. */
--- 409,415 ----
/* TI COFF v0, SPARC tools (big-endian headers). */
const bfd_target tic4x_coff0_beh_vec =
{
! "coff0-beh-tic4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_BIG, /* Header byte order is big. */
*************** const bfd_target tic4x_coff0_beh_vec =
*** 454,460 ****
/* TI COFF v1, DOS tools (little-endian headers). */
const bfd_target tic4x_coff1_vec =
{
! "coff1-c4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
--- 454,460 ----
/* TI COFF v1, DOS tools (little-endian headers). */
const bfd_target tic4x_coff1_vec =
{
! "coff1-tic4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
*************** const bfd_target tic4x_coff1_vec =
*** 499,505 ****
/* TI COFF v1, SPARC tools (big-endian headers). */
const bfd_target tic4x_coff1_beh_vec =
{
! "coff1-beh-c4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_BIG, /* Header byte order is big. */
--- 499,505 ----
/* TI COFF v1, SPARC tools (big-endian headers). */
const bfd_target tic4x_coff1_beh_vec =
{
! "coff1-beh-tic4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_BIG, /* Header byte order is big. */
*************** const bfd_target tic4x_coff1_beh_vec =
*** 544,550 ****
/* TI COFF v2, TI DOS tools output (little-endian headers). */
const bfd_target tic4x_coff2_vec =
{
! "coff2-c4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
--- 544,550 ----
/* TI COFF v2, TI DOS tools output (little-endian headers). */
const bfd_target tic4x_coff2_vec =
{
! "coff2-tic4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
*************** const bfd_target tic4x_coff2_vec =
*** 589,595 ****
/* TI COFF v2, TI SPARC tools output (big-endian headers). */
const bfd_target tic4x_coff2_beh_vec =
{
! "coff2-beh-c4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_BIG, /* Header byte order is big. */
--- 589,595 ----
/* TI COFF v2, TI SPARC tools output (big-endian headers). */
const bfd_target tic4x_coff2_beh_vec =
{
! "coff2-beh-tic4x", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_BIG, /* Header byte order is big. */
Index: bfd/cpu-tic4x.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-tic4x.c,v
retrieving revision 1.3
diff -c -3 -p -r1.3 cpu-tic4x.c
*** bfd/cpu-tic4x.c 30 Nov 2002 08:39:36 -0000 1.3
--- bfd/cpu-tic4x.c 2 Apr 2003 16:31:49 -0000
***************
*** 23,34 ****
#include "sysdep.h"
#include "libbfd.h"
! static bfd_boolean c4x_scan
PARAMS ((const struct bfd_arch_info *, const char * ));
static bfd_boolean
! c4x_scan (info, string)
const struct bfd_arch_info *info;
const char *string;
{
--- 23,34 ----
#include "sysdep.h"
#include "libbfd.h"
! static bfd_boolean tic4x_scan
PARAMS ((const struct bfd_arch_info *, const char * ));
static bfd_boolean
! tic4x_scan (info, string)
const struct bfd_arch_info *info;
const char *string;
{
*************** c4x_scan (info, string)
*** 42,50 ****
return FALSE;
if (*string == '3')
! return (info->mach == bfd_mach_c3x);
else if (*string == '4')
! return info->mach == bfd_mach_c4x;
return FALSE;
}
--- 42,50 ----
return FALSE;
if (*string == '3')
! return (info->mach == bfd_mach_tic3x);
else if (*string == '4')
! return info->mach == bfd_mach_tic4x;
return FALSE;
}
*************** const bfd_arch_info_type bfd_tic3x_arch
*** 56,68 ****
32, /* 32 bits in an address. */
32, /* 32 bits in a byte. */
bfd_arch_tic4x,
! bfd_mach_c3x, /* Machine number. */
! "c3x", /* Architecture name. */
"tms320c3x", /* Printable name. */
0, /* Alignment power. */
FALSE, /* Not the default architecture. */
bfd_default_compatible,
! c4x_scan,
0
};
--- 56,68 ----
32, /* 32 bits in an address. */
32, /* 32 bits in a byte. */
bfd_arch_tic4x,
! bfd_mach_tic3x, /* Machine number. */
! "tic3x", /* Architecture name. */
"tms320c3x", /* Printable name. */
0, /* Alignment power. */
FALSE, /* Not the default architecture. */
bfd_default_compatible,
! tic4x_scan,
0
};
*************** const bfd_arch_info_type bfd_tic4x_arch
*** 72,84 ****
32, /* 32 bits in an address. */
32, /* 32 bits in a byte. */
bfd_arch_tic4x,
! bfd_mach_c4x, /* Machine number. */
! "c4x", /* Architecture name. */
"tms320c4x", /* Printable name. */
0, /* Alignment power. */
TRUE, /* The default architecture. */
bfd_default_compatible,
! c4x_scan,
&bfd_tic3x_arch,
};
--- 72,84 ----
32, /* 32 bits in an address. */
32, /* 32 bits in a byte. */
bfd_arch_tic4x,
! bfd_mach_tic4x, /* Machine number. */
! "tic4x", /* Architecture name. */
"tms320c4x", /* Printable name. */
0, /* Alignment power. */
TRUE, /* The default architecture. */
bfd_default_compatible,
! tic4x_scan,
&bfd_tic3x_arch,
};
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1693
diff -c -3 -p -r1.1693 ChangeLog
*** gas/ChangeLog 1 Apr 2003 15:50:28 -0000 1.1693
--- gas/ChangeLog 2 Apr 2003 16:31:51 -0000
***************
*** 1,3 ****
--- 1,11 ----
+ 2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
+
+ * config/obj-coff.h (TARGET_FORMAT): Namespace cleanup, changed
+ default tic4x target format to 'coff2-tic4x'.
+ * config/tc-tic4x.c: Namespace cleanup. Replace s/c4x/tic4x/ and
+ s/c3x/tic3x/
+ * config/tc-tic4x.h: Ditto
+
2003-04-01 Bob Wilson <bob dot wilson at acm dot org>
* Makefile.am (CPU_TYPES): Add xtensa.
Index: gas/config/obj-coff.h
===================================================================
RCS file: /cvs/src/src/gas/config/obj-coff.h,v
retrieving revision 1.18
diff -c -3 -p -r1.18 obj-coff.h
*** gas/config/obj-coff.h 23 Jan 2003 12:51:04 -0000 1.18
--- gas/config/obj-coff.h 2 Apr 2003 16:31:51 -0000
***************
*** 159,165 ****
#ifdef TC_TIC4X
#include "coff/tic4x.h"
! #define TARGET_FORMAT "coff2-c4x"
#endif
#ifdef TC_TIC54X
--- 159,165 ----
#ifdef TC_TIC4X
#include "coff/tic4x.h"
! #define TARGET_FORMAT "coff2-tic4x"
#endif
#ifdef TC_TIC54X
Index: gas/config/tc-tic4x.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-tic4x.c,v
retrieving revision 1.6
diff -c -3 -p -r1.6 tc-tic4x.c
*** gas/config/tc-tic4x.c 25 Nov 2002 09:01:30 -0000 1.6
--- gas/config/tc-tic4x.c 2 Apr 2003 16:31:51 -0000
***************
*** 1,4 ****
! /* tc-c4x.c -- Assemble for the Texas Instruments TMS320C[34]x.
Copyright (C) 1997,1998, 2002 Free Software Foundation.
Contributed by Michael P. Hayes (m dot hayes at elec dot canterbury dot ac dot nz)
--- 1,4 ----
! /* tc-tic4x.c -- Assemble for the Texas Instruments TMS320C[34]x.
Copyright (C) 1997,1998, 2002 Free Software Foundation.
Contributed by Michael P. Hayes (m dot hayes at elec dot canterbury dot ac dot nz)
***************
*** 56,85 ****
#include "listing.h"
/* OK, we accept a syntax similar to the other well known C30
! assembly tools. With C4X_ALT_SYNTAX defined we are more
flexible, allowing a more Unix-like syntax: `%' in front of
register names, `#' in front of immediate constants, and
not requiring `@' in front of direct addresses. */
! #define C4X_ALT_SYNTAX
/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6 /* (12 bytes) */
/* Handle of the inst mnemonic hash table. */
! static struct hash_control *c4x_op_hash = NULL;
/* Handle asg pseudo. */
! static struct hash_control *c4x_asg_hash = NULL;
! static unsigned int c4x_cpu = 0; /* Default to TMS320C40. */
! static unsigned int c4x_revision = 0; /* CPU revision */
! static unsigned int c4x_idle2 = 0; /* Idle2 support */
! static unsigned int c4x_lowpower = 0; /* Lowpower support */
! static unsigned int c4x_enhanced = 0; /* Enhanced opcode support */
! static unsigned int c4x_big_model = 0; /* Default to small memory model. */
! static unsigned int c4x_reg_args = 0; /* Default to args passed on stack. */
! static unsigned long c4x_oplevel = 0; /* Opcode level */
#define OPTION_CPU 'm'
#define OPTION_BIG (OPTION_MD_BASE + 1)
--- 56,85 ----
#include "listing.h"
/* OK, we accept a syntax similar to the other well known C30
! assembly tools. With TIC4X_ALT_SYNTAX defined we are more
flexible, allowing a more Unix-like syntax: `%' in front of
register names, `#' in front of immediate constants, and
not requiring `@' in front of direct addresses. */
! #define TIC4X_ALT_SYNTAX
/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6 /* (12 bytes) */
/* Handle of the inst mnemonic hash table. */
! static struct hash_control *tic4x_op_hash = NULL;
/* Handle asg pseudo. */
! static struct hash_control *tic4x_asg_hash = NULL;
! static unsigned int tic4x_cpu = 0; /* Default to TMS320C40. */
! static unsigned int tic4x_revision = 0; /* CPU revision */
! static unsigned int tic4x_idle2 = 0; /* Idle2 support */
! static unsigned int tic4x_lowpower = 0; /* Lowpower support */
! static unsigned int tic4x_enhanced = 0; /* Enhanced opcode support */
! static unsigned int tic4x_big_model = 0; /* Default to small memory model. */
! static unsigned int tic4x_reg_args = 0; /* Default to args passed on stack. */
! static unsigned long tic4x_oplevel = 0; /* Opcode level */
#define OPTION_CPU 'm'
#define OPTION_BIG (OPTION_MD_BASE + 1)
*************** typedef enum
*** 115,135 ****
M_UNKNOWN, M_IMMED, M_DIRECT, M_REGISTER, M_INDIRECT,
M_IMMED_F, M_PARALLEL, M_HI
}
! c4x_addr_mode_t;
! typedef struct c4x_operand
{
! c4x_addr_mode_t mode; /* Addressing mode. */
expressionS expr; /* Expression. */
int disp; /* Displacement for indirect addressing. */
int aregno; /* Aux. register number. */
LITTLENUM_TYPE fwords[MAX_LITTLENUMS]; /* Float immed. number. */
}
! c4x_operand_t;
! typedef struct c4x_insn
{
! char name[C4X_NAME_MAX]; /* Mnemonic of instruction. */
unsigned int in_use; /* True if in_use. */
unsigned int parallel; /* True if parallel instruction. */
unsigned int nchars; /* This is always 4 for the C30. */
--- 115,135 ----
M_UNKNOWN, M_IMMED, M_DIRECT, M_REGISTER, M_INDIRECT,
M_IMMED_F, M_PARALLEL, M_HI
}
! tic4x_addr_mode_t;
! typedef struct tic4x_operand
{
! tic4x_addr_mode_t mode; /* Addressing mode. */
expressionS expr; /* Expression. */
int disp; /* Displacement for indirect addressing. */
int aregno; /* Aux. register number. */
LITTLENUM_TYPE fwords[MAX_LITTLENUMS]; /* Float immed. number. */
}
! tic4x_operand_t;
! typedef struct tic4x_insn
{
! char name[TIC4X_NAME_MAX]; /* Mnemonic of instruction. */
unsigned int in_use; /* True if in_use. */
unsigned int parallel; /* True if parallel instruction. */
unsigned int nchars; /* This is always 4 for the C30. */
*************** typedef struct c4x_insn
*** 139,219 ****
int pcrel; /* True if relocation PC relative. */
char *pname; /* Name of instruction in parallel. */
unsigned int num_operands; /* Number of operands in total. */
! c4x_inst_t *inst; /* Pointer to first template. */
! c4x_operand_t operands[C4X_OPERANDS_MAX];
}
! c4x_insn_t;
! static c4x_insn_t the_insn; /* Info about our instruction. */
! static c4x_insn_t *insn = &the_insn;
! static int c4x_gen_to_words
PARAMS ((FLONUM_TYPE, LITTLENUM_TYPE *, int ));
! static char *c4x_atof
PARAMS ((char *, char, LITTLENUM_TYPE * ));
! static void c4x_insert_reg
PARAMS ((char *, int ));
! static void c4x_insert_sym
PARAMS ((char *, int ));
! static char *c4x_expression
PARAMS ((char *, expressionS *));
! static char *c4x_expression_abs
PARAMS ((char *, int *));
! static void c4x_emit_char
PARAMS ((char, int));
! static void c4x_seg_alloc
PARAMS ((char *, segT, int, symbolS *));
! static void c4x_asg
PARAMS ((int));
! static void c4x_bss
PARAMS ((int));
! static void c4x_globl
PARAMS ((int));
! static void c4x_cons
PARAMS ((int));
! static void c4x_stringer
PARAMS ((int));
! static void c4x_eval
PARAMS ((int));
! static void c4x_newblock
PARAMS ((int));
! static void c4x_sect
PARAMS ((int));
! static void c4x_set
PARAMS ((int));
! static void c4x_usect
PARAMS ((int));
! static void c4x_version
PARAMS ((int));
! static void c4x_init_regtable
PARAMS ((void));
! static void c4x_init_symbols
PARAMS ((void));
! static int c4x_inst_insert
! PARAMS ((c4x_inst_t *));
! static c4x_inst_t *c4x_inst_make
PARAMS ((char *, unsigned long, char *));
! static int c4x_inst_add
! PARAMS ((c4x_inst_t *));
void md_begin
PARAMS ((void));
! void c4x_end
PARAMS ((void));
! static int c4x_indirect_parse
! PARAMS ((c4x_operand_t *, const c4x_indirect_t *));
! static char *c4x_operand_parse
! PARAMS ((char *, c4x_operand_t *));
! static int c4x_operands_match
! PARAMS ((c4x_inst_t *, c4x_insn_t *, int));
! static void c4x_insn_check
! PARAMS ((c4x_insn_t *));
! static void c4x_insn_output
! PARAMS ((c4x_insn_t *));
! static int c4x_operands_parse
! PARAMS ((char *, c4x_operand_t *, int ));
void md_assemble
PARAMS ((char *));
! void c4x_cleanup
PARAMS ((void));
char *md_atof
PARAMS ((int, char *, int *));
--- 139,219 ----
int pcrel; /* True if relocation PC relative. */
char *pname; /* Name of instruction in parallel. */
unsigned int num_operands; /* Number of operands in total. */
! tic4x_inst_t *inst; /* Pointer to first template. */
! tic4x_operand_t operands[TIC4X_OPERANDS_MAX];
}
! tic4x_insn_t;
! static tic4x_insn_t the_insn; /* Info about our instruction. */
! static tic4x_insn_t *insn = &the_insn;
! static int tic4x_gen_to_words
PARAMS ((FLONUM_TYPE, LITTLENUM_TYPE *, int ));
! static char *tic4x_atof
PARAMS ((char *, char, LITTLENUM_TYPE * ));
! static void tic4x_insert_reg
PARAMS ((char *, int ));
! static void tic4x_insert_sym
PARAMS ((char *, int ));
! static char *tic4x_expression
PARAMS ((char *, expressionS *));
! static char *tic4x_expression_abs
PARAMS ((char *, int *));
! static void tic4x_emit_char
PARAMS ((char, int));
! static void tic4x_seg_alloc
PARAMS ((char *, segT, int, symbolS *));
! static void tic4x_asg
PARAMS ((int));
! static void tic4x_bss
PARAMS ((int));
! static void tic4x_globl
PARAMS ((int));
! static void tic4x_cons
PARAMS ((int));
! static void tic4x_stringer
PARAMS ((int));
! static void tic4x_eval
PARAMS ((int));
! static void tic4x_newblock
PARAMS ((int));
! static void tic4x_sect
PARAMS ((int));
! static void tic4x_set
PARAMS ((int));
! static void tic4x_usect
PARAMS ((int));
! static void tic4x_version
PARAMS ((int));
! static void tic4x_init_regtable
PARAMS ((void));
! static void tic4x_init_symbols
PARAMS ((void));
! static int tic4x_inst_insert
! PARAMS ((tic4x_inst_t *));
! static tic4x_inst_t *tic4x_inst_make
PARAMS ((char *, unsigned long, char *));
! static int tic4x_inst_add
! PARAMS ((tic4x_inst_t *));
void md_begin
PARAMS ((void));
! void tic4x_end
PARAMS ((void));
! static int tic4x_indirect_parse
! PARAMS ((tic4x_operand_t *, const tic4x_indirect_t *));
! static char *tic4x_operand_parse
! PARAMS ((char *, tic4x_operand_t *));
! static int tic4x_operands_match
! PARAMS ((tic4x_inst_t *, tic4x_insn_t *, int));
! static void tic4x_insn_check
! PARAMS ((tic4x_insn_t *));
! static void tic4x_insn_output
! PARAMS ((tic4x_insn_t *));
! static int tic4x_operands_parse
! PARAMS ((char *, tic4x_operand_t *, int ));
void md_assemble
PARAMS ((char *));
! void tic4x_cleanup
PARAMS ((void));
char *md_atof
PARAMS ((int, char *, int *));
*************** int md_parse_option
*** 231,237 ****
PARAMS ((int, char *));
void md_show_usage
PARAMS ((FILE *));
! int c4x_unrecognized_line
PARAMS ((int));
symbolS *md_undefined_symbol
PARAMS ((char *));
--- 231,237 ----
PARAMS ((int, char *));
void md_show_usage
PARAMS ((FILE *));
! int tic4x_unrecognized_line
PARAMS ((int));
symbolS *md_undefined_symbol
PARAMS ((char *));
*************** void md_operand
*** 239,251 ****
PARAMS ((expressionS *));
valueT md_section_align
PARAMS ((segT, valueT));
! static int c4x_pc_offset
PARAMS ((unsigned int));
long md_pcrel_from
PARAMS ((fixS *));
! int c4x_do_align
PARAMS ((int, const char *, int, int));
! void c4x_start_line
PARAMS ((void));
arelent *tc_gen_reloc
PARAMS ((asection *, fixS *));
--- 239,251 ----
PARAMS ((expressionS *));
valueT md_section_align
PARAMS ((segT, valueT));
! static int tic4x_pc_offset
PARAMS ((unsigned int));
long md_pcrel_from
PARAMS ((fixS *));
! int tic4x_do_align
PARAMS ((int, const char *, int, int));
! void tic4x_start_line
PARAMS ((void));
arelent *tc_gen_reloc
PARAMS ((asection *, fixS *));
*************** const pseudo_typeS
*** 255,286 ****
md_pseudo_table[] =
{
{"align", s_align_bytes, 32},
! {"ascii", c4x_stringer, 1},
! {"asciz", c4x_stringer, 0},
! {"asg", c4x_asg, 0},
{"block", s_space, 4},
! {"byte", c4x_cons, 1},
! {"bss", c4x_bss, 0},
{"copy", s_include, 0},
! {"def", c4x_globl, 0},
! {"equ", c4x_set, 0},
! {"eval", c4x_eval, 0},
! {"global", c4x_globl, 0},
! {"globl", c4x_globl, 0},
! {"hword", c4x_cons, 2},
{"ieee", float_cons, 'i'},
! {"int", c4x_cons, 4}, /* .int allocates 4 bytes. */
{"ldouble", float_cons, 'e'},
! {"newblock", c4x_newblock, 0},
{"ref", s_ignore, 0}, /* All undefined treated as external. */
! {"set", c4x_set, 0},
! {"sect", c4x_sect, 1}, /* Define named section. */
{"space", s_space, 4},
! {"string", c4x_stringer, 0},
! {"usect", c4x_usect, 0}, /* Reserve space in uninit. named sect. */
! {"version", c4x_version, 0},
! {"word", c4x_cons, 4}, /* .word allocates 4 bytes. */
! {"xdef", c4x_globl, 0},
{NULL, 0, 0},
};
--- 255,286 ----
md_pseudo_table[] =
{
{"align", s_align_bytes, 32},
! {"ascii", tic4x_stringer, 1},
! {"asciz", tic4x_stringer, 0},
! {"asg", tic4x_asg, 0},
{"block", s_space, 4},
! {"byte", tic4x_cons, 1},
! {"bss", tic4x_bss, 0},
{"copy", s_include, 0},
! {"def", tic4x_globl, 0},
! {"equ", tic4x_set, 0},
! {"eval", tic4x_eval, 0},
! {"global", tic4x_globl, 0},
! {"globl", tic4x_globl, 0},
! {"hword", tic4x_cons, 2},
{"ieee", float_cons, 'i'},
! {"int", tic4x_cons, 4}, /* .int allocates 4 bytes. */
{"ldouble", float_cons, 'e'},
! {"newblock", tic4x_newblock, 0},
{"ref", s_ignore, 0}, /* All undefined treated as external. */
! {"set", tic4x_set, 0},
! {"sect", tic4x_sect, 1}, /* Define named section. */
{"space", s_space, 4},
! {"string", tic4x_stringer, 0},
! {"usect", tic4x_usect, 0}, /* Reserve space in uninit. named sect. */
! {"version", tic4x_version, 0},
! {"word", tic4x_cons, 4}, /* .word allocates 4 bytes. */
! {"xdef", tic4x_globl, 0},
{NULL, 0, 0},
};
*************** const int md_reloc_size = RELSZ; /* Coff
*** 290,296 ****
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. */
! #ifdef C4X_ALT_SYNTAX
const char comment_chars[] = ";!";
#else
const char comment_chars[] = ";";
--- 290,296 ----
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. */
! #ifdef TIC4X_ALT_SYNTAX
const char comment_chars[] = ";!";
#else
const char comment_chars[] = ";";
*************** extern FLONUM_TYPE generic_floating_poin
*** 334,340 ****
/* Turn generic_floating_point_number into a real short/float/double. */
static int
! c4x_gen_to_words (flonum, words, precision)
FLONUM_TYPE flonum;
LITTLENUM_TYPE *words;
int precision;
--- 334,340 ----
/* Turn generic_floating_point_number into a real short/float/double. */
static int
! tic4x_gen_to_words (flonum, words, precision)
FLONUM_TYPE flonum;
LITTLENUM_TYPE *words;
int precision;
*************** c4x_gen_to_words (flonum, words, precisi
*** 651,657 ****
/* Returns pointer past text consumed. */
static char *
! c4x_atof (str, what_kind, words)
char *str;
char what_kind;
LITTLENUM_TYPE *words;
--- 651,657 ----
/* Returns pointer past text consumed. */
static char *
! tic4x_atof (str, what_kind, words)
char *str;
char what_kind;
LITTLENUM_TYPE *words;
*************** c4x_atof (str, what_kind, words)
*** 716,722 ****
return (NULL);
}
! c4x_gen_to_words (generic_floating_point_number,
words, precision);
/* Restore the generic_floating_point_number's storage alloc (and
--- 716,722 ----
return (NULL);
}
! tic4x_gen_to_words (generic_floating_point_number,
words, precision);
/* Restore the generic_floating_point_number's storage alloc (and
*************** c4x_atof (str, what_kind, words)
*** 727,733 ****
}
static void
! c4x_insert_reg (regname, regnum)
char *regname;
int regnum;
{
--- 727,733 ----
}
static void
! tic4x_insert_reg (regname, regnum)
char *regname;
int regnum;
{
*************** c4x_insert_reg (regname, regnum)
*** 745,751 ****
}
static void
! c4x_insert_sym (symname, value)
char *symname;
int value;
{
--- 745,751 ----
}
static void
! tic4x_insert_sym (symname, value)
char *symname;
int value;
{
*************** c4x_insert_sym (symname, value)
*** 758,764 ****
}
static char *
! c4x_expression (str, exp)
char *str;
expressionS *exp;
{
--- 758,764 ----
}
static char *
! tic4x_expression (str, exp)
char *str;
expressionS *exp;
{
*************** c4x_expression (str, exp)
*** 774,780 ****
}
static char *
! c4x_expression_abs (str, value)
char *str;
int *value;
{
--- 774,780 ----
}
static char *
! tic4x_expression_abs (str, value)
char *str;
int *value;
{
*************** c4x_expression_abs (str, value)
*** 790,796 ****
}
static void
! c4x_emit_char (c,b)
char c;
int b;
{
--- 790,796 ----
}
static void
! tic4x_emit_char (c,b)
char c;
int b;
{
*************** c4x_emit_char (c,b)
*** 802,808 ****
}
static void
! c4x_seg_alloc (name, seg, size, symbolP)
char *name ATTRIBUTE_UNUSED;
segT seg ATTRIBUTE_UNUSED;
int size;
--- 802,808 ----
}
static void
! tic4x_seg_alloc (name, seg, size, symbolP)
char *name ATTRIBUTE_UNUSED;
segT seg ATTRIBUTE_UNUSED;
int size;
*************** c4x_seg_alloc (name, seg, size, symbolP)
*** 828,834 ****
/* .asg ["]character-string["], symbol */
static void
! c4x_asg (x)
int x ATTRIBUTE_UNUSED;
{
char c;
--- 828,834 ----
/* .asg ["]character-string["], symbol */
static void
! tic4x_asg (x)
int x ATTRIBUTE_UNUSED;
{
char c;
*************** c4x_asg (x)
*** 856,872 ****
tmp = xmalloc (strlen (name) + 1);
strcpy (tmp, name);
name = tmp;
! if (hash_find (c4x_asg_hash, name))
! hash_replace (c4x_asg_hash, name, (PTR) str);
else
! hash_insert (c4x_asg_hash, name, (PTR) str);
*input_line_pointer = c;
demand_empty_rest_of_line ();
}
/* .bss symbol, size */
static void
! c4x_bss (x)
int x ATTRIBUTE_UNUSED;
{
char c;
--- 856,872 ----
tmp = xmalloc (strlen (name) + 1);
strcpy (tmp, name);
name = tmp;
! if (hash_find (tic4x_asg_hash, name))
! hash_replace (tic4x_asg_hash, name, (PTR) str);
else
! hash_insert (tic4x_asg_hash, name, (PTR) str);
*input_line_pointer = c;
demand_empty_rest_of_line ();
}
/* .bss symbol, size */
static void
! tic4x_bss (x)
int x ATTRIBUTE_UNUSED;
{
char c;
*************** c4x_bss (x)
*** 890,896 ****
}
input_line_pointer =
! c4x_expression_abs (++input_line_pointer, &size);
if (size < 0)
{
as_bad (".bss size %d < 0!", size);
--- 890,896 ----
}
input_line_pointer =
! tic4x_expression_abs (++input_line_pointer, &size);
if (size < 0)
{
as_bad (".bss size %d < 0!", size);
*************** c4x_bss (x)
*** 921,927 ****
}
static void
! c4x_globl (ignore)
int ignore ATTRIBUTE_UNUSED;
{
char *name;
--- 921,927 ----
}
static void
! tic4x_globl (ignore)
int ignore ATTRIBUTE_UNUSED;
{
char *name;
*************** c4x_globl (ignore)
*** 951,957 ****
/* Handle .byte, .word. .int, .long */
static void
! c4x_cons (bytes)
int bytes;
{
register unsigned int c;
--- 951,957 ----
/* Handle .byte, .word. .int, .long */
static void
! tic4x_cons (bytes)
int bytes;
{
register unsigned int c;
*************** c4x_cons (bytes)
*** 962,975 ****
{
input_line_pointer++;
while (is_a_char (c = next_char_of_string ()))
! c4x_emit_char (c, 4);
know (input_line_pointer[-1] == '\"');
}
else
{
expressionS exp;
! input_line_pointer = c4x_expression (input_line_pointer, &exp);
if (exp.X_op == O_constant)
{
switch (bytes)
--- 962,975 ----
{
input_line_pointer++;
while (is_a_char (c = next_char_of_string ()))
! tic4x_emit_char (c, 4);
know (input_line_pointer[-1] == '\"');
}
else
{
expressionS exp;
! input_line_pointer = tic4x_expression (input_line_pointer, &exp);
if (exp.X_op == O_constant)
{
switch (bytes)
*************** c4x_cons (bytes)
*** 995,1001 ****
/* Handle .ascii, .asciz, .string */
static void
! c4x_stringer (append_zero)
int append_zero; /*ex: bytes */
{
int bytes;
--- 995,1001 ----
/* Handle .ascii, .asciz, .string */
static void
! tic4x_stringer (append_zero)
int append_zero; /*ex: bytes */
{
int bytes;
*************** c4x_stringer (append_zero)
*** 1010,1022 ****
input_line_pointer++;
while (is_a_char (c = next_char_of_string ()))
{
! c4x_emit_char (c, 1);
bytes++;
}
if (append_zero)
{
! c4x_emit_char (c, 1);
bytes++;
}
--- 1010,1022 ----
input_line_pointer++;
while (is_a_char (c = next_char_of_string ()))
{
! tic4x_emit_char (c, 1);
bytes++;
}
if (append_zero)
{
! tic4x_emit_char (c, 1);
bytes++;
}
*************** c4x_stringer (append_zero)
*** 1026,1032 ****
{
expressionS exp;
! input_line_pointer = c4x_expression (input_line_pointer, &exp);
if (exp.X_op != O_constant)
{
as_bad("Non-constant symbols not allowed\n");
--- 1026,1032 ----
{
expressionS exp;
! input_line_pointer = tic4x_expression (input_line_pointer, &exp);
if (exp.X_op != O_constant)
{
as_bad("Non-constant symbols not allowed\n");
*************** c4x_stringer (append_zero)
*** 1041,1047 ****
/* Fill out the rest of the expression with 0's to fill up a full word */
if ( bytes&0x3 )
! c4x_emit_char (0, 4-(bytes&0x3));
input_line_pointer--; /* Put terminator back into stream. */
demand_empty_rest_of_line ();
--- 1041,1047 ----
/* Fill out the rest of the expression with 0's to fill up a full word */
if ( bytes&0x3 )
! tic4x_emit_char (0, 4-(bytes&0x3));
input_line_pointer--; /* Put terminator back into stream. */
demand_empty_rest_of_line ();
*************** c4x_stringer (append_zero)
*** 1049,1055 ****
/* .eval expression, symbol */
static void
! c4x_eval (x)
int x ATTRIBUTE_UNUSED;
{
char c;
--- 1049,1055 ----
/* .eval expression, symbol */
static void
! tic4x_eval (x)
int x ATTRIBUTE_UNUSED;
{
char c;
*************** c4x_eval (x)
*** 1058,1064 ****
SKIP_WHITESPACE ();
input_line_pointer =
! c4x_expression_abs (input_line_pointer, &value);
if (*input_line_pointer++ != ',')
{
as_bad ("Symbol missing\n");
--- 1058,1064 ----
SKIP_WHITESPACE ();
input_line_pointer =
! tic4x_expression_abs (input_line_pointer, &value);
if (*input_line_pointer++ != ',')
{
as_bad ("Symbol missing\n");
*************** c4x_eval (x)
*** 1067,1078 ****
name = input_line_pointer;
c = get_symbol_end (); /* Get terminator. */
demand_empty_rest_of_line ();
! c4x_insert_sym (name, value);
}
/* Reset local labels. */
static void
! c4x_newblock (x)
int x ATTRIBUTE_UNUSED;
{
dollar_label_clear ();
--- 1067,1078 ----
name = input_line_pointer;
c = get_symbol_end (); /* Get terminator. */
demand_empty_rest_of_line ();
! tic4x_insert_sym (name, value);
}
/* Reset local labels. */
static void
! tic4x_newblock (x)
int x ATTRIBUTE_UNUSED;
{
dollar_label_clear ();
*************** c4x_newblock (x)
*** 1081,1087 ****
/* .sect "section-name" [, value] */
/* .sect ["]section-name[:subsection-name]["] [, value] */
static void
! c4x_sect (x)
int x ATTRIBUTE_UNUSED;
{
char c;
--- 1081,1087 ----
/* .sect "section-name" [, value] */
/* .sect ["]section-name[:subsection-name]["] [, value] */
static void
! tic4x_sect (x)
int x ATTRIBUTE_UNUSED;
{
char c;
*************** c4x_sect (x)
*** 1119,1129 ****
if (c == ',')
input_line_pointer =
! c4x_expression_abs (input_line_pointer, &num);
else if (*input_line_pointer == ',')
{
input_line_pointer =
! c4x_expression_abs (++input_line_pointer, &num);
}
else
num = 0;
--- 1119,1129 ----
if (c == ',')
input_line_pointer =
! tic4x_expression_abs (input_line_pointer, &num);
else if (*input_line_pointer == ',')
{
input_line_pointer =
! tic4x_expression_abs (++input_line_pointer, &num);
}
else
num = 0;
*************** c4x_sect (x)
*** 1155,1161 ****
/* symbol[:] .set value or .set symbol, value */
static void
! c4x_set (x)
int x ATTRIBUTE_UNUSED;
{
symbolS *symbolP;
--- 1155,1161 ----
/* symbol[:] .set value or .set symbol, value */
static void
! tic4x_set (x)
int x ATTRIBUTE_UNUSED;
{
symbolS *symbolP;
*************** c4x_set (x)
*** 1185,1191 ****
/* [symbol] .usect ["]section-name["], size-in-words [, alignment-flag] */
static void
! c4x_usect (x)
int x ATTRIBUTE_UNUSED;
{
char c;
--- 1185,1191 ----
/* [symbol] .usect ["]section-name["], size-in-words [, alignment-flag] */
static void
! tic4x_usect (x)
int x ATTRIBUTE_UNUSED;
{
char c;
*************** c4x_usect (x)
*** 1210,1220 ****
if (c == ',')
input_line_pointer =
! c4x_expression_abs (input_line_pointer, &size);
else if (*input_line_pointer == ',')
{
input_line_pointer =
! c4x_expression_abs (++input_line_pointer, &size);
}
else
size = 0;
--- 1210,1220 ----
if (c == ',')
input_line_pointer =
! tic4x_expression_abs (input_line_pointer, &size);
else if (*input_line_pointer == ',')
{
input_line_pointer =
! tic4x_expression_abs (++input_line_pointer, &size);
}
else
size = 0;
*************** c4x_usect (x)
*** 1223,1229 ****
if (*input_line_pointer == ',')
{
input_line_pointer =
! c4x_expression_abs (++input_line_pointer, &alignment_flag);
}
else
alignment_flag = 0;
--- 1223,1229 ----
if (*input_line_pointer == ',')
{
input_line_pointer =
! tic4x_expression_abs (++input_line_pointer, &alignment_flag);
}
else
alignment_flag = 0;
*************** c4x_usect (x)
*** 1241,1247 ****
if (!bfd_set_section_flags (stdoutput, seg, SEC_ALLOC))
as_warn ("Error setting flags for \"%s\": %s", name,
bfd_errmsg (bfd_get_error ()));
! c4x_seg_alloc (name, seg, size, line_label);
if (S_GET_STORAGE_CLASS (line_label) != C_EXT)
S_SET_STORAGE_CLASS (line_label, C_STAT);
--- 1241,1247 ----
if (!bfd_set_section_flags (stdoutput, seg, SEC_ALLOC))
as_warn ("Error setting flags for \"%s\": %s", name,
bfd_errmsg (bfd_get_error ()));
! tic4x_seg_alloc (name, seg, size, line_label);
if (S_GET_STORAGE_CLASS (line_label) != C_EXT)
S_SET_STORAGE_CLASS (line_label, C_STAT);
*************** c4x_usect (x)
*** 1252,1294 ****
/* .version cpu-version. */
static void
! c4x_version (x)
int x ATTRIBUTE_UNUSED;
{
unsigned int temp;
input_line_pointer =
! c4x_expression_abs (input_line_pointer, &temp);
! if (!IS_CPU_C3X (temp) && !IS_CPU_C4X (temp))
as_bad ("This assembler does not support processor generation %d",
temp);
! if (c4x_cpu && temp != c4x_cpu)
as_warn ("Changing processor generation on fly not supported...");
! c4x_cpu = temp;
demand_empty_rest_of_line ();
}
static void
! c4x_init_regtable ()
{
unsigned int i;
! for (i = 0; i < c3x_num_registers; i++)
! c4x_insert_reg (c3x_registers[i].name,
! c3x_registers[i].regno);
!
! if (IS_CPU_C4X (c4x_cpu))
! {
! /* Add additional C4x registers, overriding some C3x ones. */
! for (i = 0; i < c4x_num_registers; i++)
! c4x_insert_reg (c4x_registers[i].name,
! c4x_registers[i].regno);
}
}
static void
! c4x_init_symbols ()
{
/* The TI tools accept case insensitive versions of these symbols,
we don't !
--- 1252,1294 ----
/* .version cpu-version. */
static void
! tic4x_version (x)
int x ATTRIBUTE_UNUSED;
{
unsigned int temp;
input_line_pointer =
! tic4x_expression_abs (input_line_pointer, &temp);
! if (!IS_CPU_TIC3X (temp) && !IS_CPU_TIC4X (temp))
as_bad ("This assembler does not support processor generation %d",
temp);
! if (tic4x_cpu && temp != tic4x_cpu)
as_warn ("Changing processor generation on fly not supported...");
! tic4x_cpu = temp;
demand_empty_rest_of_line ();
}
static void
! tic4x_init_regtable ()
{
unsigned int i;
! for (i = 0; i < tic3x_num_registers; i++)
! tic4x_insert_reg (tic3x_registers[i].name,
! tic3x_registers[i].regno);
!
! if (IS_CPU_TIC4X (tic4x_cpu))
! {
! /* Add additional Tic4x registers, overriding some C3x ones. */
! for (i = 0; i < tic4x_num_registers; i++)
! tic4x_insert_reg (tic4x_registers[i].name,
! tic4x_registers[i].regno);
}
}
static void
! tic4x_init_symbols ()
{
/* The TI tools accept case insensitive versions of these symbols,
we don't !
*************** c4x_init_symbols ()
*** 1317,1352 ****
Source: TI: TMS320C3x/C4x Assembly Language Tools User's Guide,
1997, SPRU035C, p. 3-17/3-18. */
! c4x_insert_sym (".REGPARM", c4x_reg_args);
! c4x_insert_sym (".MEMPARM", !c4x_reg_args);
! c4x_insert_sym (".BIGMODEL", c4x_big_model);
! c4x_insert_sym (".C30INTERRUPT", 0);
! c4x_insert_sym (".TMS320xx", c4x_cpu == 0 ? 40 : c4x_cpu);
! c4x_insert_sym (".C3X", c4x_cpu == 30 || c4x_cpu == 31 || c4x_cpu == 32 || c4x_cpu == 33);
! c4x_insert_sym (".C3x", c4x_cpu == 30 || c4x_cpu == 31 || c4x_cpu == 32 || c4x_cpu == 33);
! c4x_insert_sym (".C4X", c4x_cpu == 0 || c4x_cpu == 40 || c4x_cpu == 44);
! c4x_insert_sym (".C4x", c4x_cpu == 0 || c4x_cpu == 40 || c4x_cpu == 44);
/* Do we need to have the following symbols also in lower case? */
! c4x_insert_sym (".TMS320C30", c4x_cpu == 30 || c4x_cpu == 31 || c4x_cpu == 32 || c4x_cpu == 33);
! c4x_insert_sym (".tms320C30", c4x_cpu == 30 || c4x_cpu == 31 || c4x_cpu == 32 || c4x_cpu == 33);
! c4x_insert_sym (".TMS320C31", c4x_cpu == 31);
! c4x_insert_sym (".tms320C31", c4x_cpu == 31);
! c4x_insert_sym (".TMS320C32", c4x_cpu == 32);
! c4x_insert_sym (".tms320C32", c4x_cpu == 32);
! c4x_insert_sym (".TMS320C33", c4x_cpu == 33);
! c4x_insert_sym (".tms320C33", c4x_cpu == 33);
! c4x_insert_sym (".TMS320C40", c4x_cpu == 40 || c4x_cpu == 44 || c4x_cpu == 0);
! c4x_insert_sym (".tms320C40", c4x_cpu == 40 || c4x_cpu == 44 || c4x_cpu == 0);
! c4x_insert_sym (".TMS320C44", c4x_cpu == 44);
! c4x_insert_sym (".tms320C44", c4x_cpu == 44);
! c4x_insert_sym (".TMX320C40", 0); /* C40 first pass silicon ? */
! c4x_insert_sym (".tmx320C40", 0);
}
/* Insert a new instruction template into hash table. */
static int
! c4x_inst_insert (inst)
! c4x_inst_t *inst;
{
static char prev_name[16];
const char *retval = NULL;
--- 1317,1352 ----
Source: TI: TMS320C3x/C4x Assembly Language Tools User's Guide,
1997, SPRU035C, p. 3-17/3-18. */
! tic4x_insert_sym (".REGPARM", tic4x_reg_args);
! tic4x_insert_sym (".MEMPARM", !tic4x_reg_args);
! tic4x_insert_sym (".BIGMODEL", tic4x_big_model);
! tic4x_insert_sym (".C30INTERRUPT", 0);
! tic4x_insert_sym (".TMS320xx", tic4x_cpu == 0 ? 40 : tic4x_cpu);
! tic4x_insert_sym (".C3X", tic4x_cpu == 30 || tic4x_cpu == 31 || tic4x_cpu == 32 || tic4x_cpu == 33);
! tic4x_insert_sym (".C3x", tic4x_cpu == 30 || tic4x_cpu == 31 || tic4x_cpu == 32 || tic4x_cpu == 33);
! tic4x_insert_sym (".C4X", tic4x_cpu == 0 || tic4x_cpu == 40 || tic4x_cpu == 44);
! tic4x_insert_sym (".C4x", tic4x_cpu == 0 || tic4x_cpu == 40 || tic4x_cpu == 44);
/* Do we need to have the following symbols also in lower case? */
! tic4x_insert_sym (".TMS320C30", tic4x_cpu == 30 || tic4x_cpu == 31 || tic4x_cpu == 32 || tic4x_cpu == 33);
! tic4x_insert_sym (".tms320C30", tic4x_cpu == 30 || tic4x_cpu == 31 || tic4x_cpu == 32 || tic4x_cpu == 33);
! tic4x_insert_sym (".TMS320C31", tic4x_cpu == 31);
! tic4x_insert_sym (".tms320C31", tic4x_cpu == 31);
! tic4x_insert_sym (".TMS320C32", tic4x_cpu == 32);
! tic4x_insert_sym (".tms320C32", tic4x_cpu == 32);
! tic4x_insert_sym (".TMS320C33", tic4x_cpu == 33);
! tic4x_insert_sym (".tms320C33", tic4x_cpu == 33);
! tic4x_insert_sym (".TMS320C40", tic4x_cpu == 40 || tic4x_cpu == 44 || tic4x_cpu == 0);
! tic4x_insert_sym (".tms320C40", tic4x_cpu == 40 || tic4x_cpu == 44 || tic4x_cpu == 0);
! tic4x_insert_sym (".TMS320C44", tic4x_cpu == 44);
! tic4x_insert_sym (".tms320C44", tic4x_cpu == 44);
! tic4x_insert_sym (".TMX320C40", 0); /* C40 first pass silicon ? */
! tic4x_insert_sym (".tmx320C40", 0);
}
/* Insert a new instruction template into hash table. */
static int
! tic4x_inst_insert (inst)
! tic4x_inst_t *inst;
{
static char prev_name[16];
const char *retval = NULL;
*************** c4x_inst_insert (inst)
*** 1355,1361 ****
if (!strcmp (inst->name, prev_name) || inst->name[0] == '\0')
return 1;
! retval = hash_insert (c4x_op_hash, inst->name, (PTR) inst);
if (retval != NULL)
fprintf (stderr, "internal error: can't hash `%s': %s\n",
inst->name, retval);
--- 1355,1361 ----
if (!strcmp (inst->name, prev_name) || inst->name[0] == '\0')
return 1;
! retval = hash_insert (tic4x_op_hash, inst->name, (PTR) inst);
if (retval != NULL)
fprintf (stderr, "internal error: can't hash `%s': %s\n",
inst->name, retval);
*************** c4x_inst_insert (inst)
*** 1365,1377 ****
}
/* Make a new instruction template. */
! static c4x_inst_t *
! c4x_inst_make (name, opcode, args)
char *name;
unsigned long opcode;
char *args;
{
! static c4x_inst_t *insts = NULL;
static char *names = NULL;
static int index = 0;
--- 1365,1377 ----
}
/* Make a new instruction template. */
! static tic4x_inst_t *
! tic4x_inst_make (name, opcode, args)
char *name;
unsigned long opcode;
char *args;
{
! static tic4x_inst_t *insts = NULL;
static char *names = NULL;
static int index = 0;
*************** c4x_inst_make (name, opcode, args)
*** 1380,1387 ****
/* Allocate memory to store name strings. */
names = (char *) xmalloc (sizeof (char) * 8192);
/* Allocate memory for additional insts. */
! insts = (c4x_inst_t *)
! xmalloc (sizeof (c4x_inst_t) * 1024);
}
insts[index].name = names;
insts[index].opcode = opcode;
--- 1380,1387 ----
/* Allocate memory to store name strings. */
names = (char *) xmalloc (sizeof (char) * 8192);
/* Allocate memory for additional insts. */
! insts = (tic4x_inst_t *)
! xmalloc (sizeof (tic4x_inst_t) * 1024);
}
insts[index].name = names;
insts[index].opcode = opcode;
*************** c4x_inst_make (name, opcode, args)
*** 1399,1406 ****
/* Add instruction template, creating dynamic templates as required. */
static int
! c4x_inst_add (insts)
! c4x_inst_t *insts;
{
char *s = insts->name;
char *d;
--- 1399,1406 ----
/* Add instruction template, creating dynamic templates as required. */
static int
! tic4x_inst_add (insts)
! tic4x_inst_t *insts;
{
char *s = insts->name;
char *d;
*************** c4x_inst_add (insts)
*** 1412,1418 ****
/* We do not care about INSNs that is not a part of our
oplevel setting */
! if (!insts->oplevel & c4x_oplevel)
return ok;
while (1)
--- 1412,1418 ----
/* We do not care about INSNs that is not a part of our
oplevel setting */
! if (!insts->oplevel & tic4x_oplevel)
return ok;
while (1)
*************** c4x_inst_add (insts)
*** 1422,1432 ****
case 'B':
case 'C':
/* Dynamically create all the conditional insts. */
! for (i = 0; i < num_conds; i++)
{
! c4x_inst_t *inst;
int k = 0;
! char *c = c4x_conds[i].name;
char *e = d;
while (*c)
--- 1422,1432 ----
case 'B':
case 'C':
/* Dynamically create all the conditional insts. */
! for (i = 0; i < tic4x_num_conds; i++)
{
! tic4x_inst_t *inst;
int k = 0;
! char *c = tic4x_conds[i].name;
char *e = d;
while (*c)
*************** c4x_inst_add (insts)
*** 1437,1453 ****
*e = '\0';
/* If instruction found then have already processed it. */
! if (hash_find (c4x_op_hash, name))
return 1;
do
{
! inst = c4x_inst_make (name, insts[k].opcode +
! (c4x_conds[i].cond <<
(*s == 'B' ? 16 : 23)),
insts[k].args);
if (k == 0) /* Save strcmp() with following func. */
! ok &= c4x_inst_insert (inst);
k++;
}
while (!strcmp (insts->name,
--- 1437,1453 ----
*e = '\0';
/* If instruction found then have already processed it. */
! if (hash_find (tic4x_op_hash, name))
return 1;
do
{
! inst = tic4x_inst_make (name, insts[k].opcode +
! (tic4x_conds[i].cond <<
(*s == 'B' ? 16 : 23)),
insts[k].args);
if (k == 0) /* Save strcmp() with following func. */
! ok &= tic4x_inst_insert (inst);
k++;
}
while (!strcmp (insts->name,
*************** c4x_inst_add (insts)
*** 1457,1463 ****
break;
case '\0':
! return c4x_inst_insert (insts);
break;
default:
--- 1457,1463 ----
break;
case '\0':
! return tic4x_inst_insert (insts);
break;
default:
*************** md_begin ()
*** 1478,1543 ****
/* Setup the proper opcode level according to the
commandline parameters */
! c4x_oplevel = OP_C3X;
! if ( IS_CPU_C4X(c4x_cpu) )
! c4x_oplevel |= OP_C4X;
! if ( ( c4x_cpu == 31 && c4x_revision >= 6)
! || (c4x_cpu == 32 && c4x_revision >= 2)
! || (c4x_cpu == 33)
! || c4x_enhanced )
! c4x_oplevel |= OP_ENH;
!
! if ( ( c4x_cpu == 30 && c4x_revision >= 7)
! || (c4x_cpu == 31 && c4x_revision >= 5)
! || (c4x_cpu == 32)
! || c4x_lowpower )
! c4x_oplevel |= OP_LPWR;
!
! if ( ( c4x_cpu == 30 && c4x_revision >= 7)
! || (c4x_cpu == 31 && c4x_revision >= 5)
! || (c4x_cpu == 32)
! || (c4x_cpu == 33)
! || (c4x_cpu == 40 && c4x_revision >= 5)
! || (c4x_cpu == 44)
! || c4x_idle2 )
! c4x_oplevel |= OP_IDLE2;
/* Create hash table for mnemonics. */
! c4x_op_hash = hash_new ();
/* Create hash table for asg pseudo. */
! c4x_asg_hash = hash_new ();
/* Add mnemonics to hash table, expanding conditional mnemonics on fly. */
! for (i = 0; i < c4x_num_insts; i++)
! ok &= c4x_inst_add ((void *) &c4x_insts[i]);
/* Create dummy inst to avoid errors accessing end of table. */
! c4x_inst_make ("", 0, "");
if (!ok)
as_fatal ("Broken assembler. No assembly attempted.");
/* Add registers to symbol table. */
! c4x_init_regtable ();
/* Add predefined symbols to symbol table. */
! c4x_init_symbols ();
}
void
! c4x_end ()
{
bfd_set_arch_mach (stdoutput, bfd_arch_tic4x,
! IS_CPU_C4X (c4x_cpu) ? bfd_mach_c4x : bfd_mach_c3x);
}
static int
! c4x_indirect_parse (operand, indirect)
! c4x_operand_t *operand;
! const c4x_indirect_t *indirect;
{
char *n = indirect->name;
char *s = input_line_pointer;
--- 1478,1543 ----
/* Setup the proper opcode level according to the
commandline parameters */
! tic4x_oplevel = OP_C3X;
! if ( IS_CPU_TIC4X(tic4x_cpu) )
! tic4x_oplevel |= OP_C4X;
! if ( ( tic4x_cpu == 31 && tic4x_revision >= 6)
! || (tic4x_cpu == 32 && tic4x_revision >= 2)
! || (tic4x_cpu == 33)
! || tic4x_enhanced )
! tic4x_oplevel |= OP_ENH;
!
! if ( ( tic4x_cpu == 30 && tic4x_revision >= 7)
! || (tic4x_cpu == 31 && tic4x_revision >= 5)
! || (tic4x_cpu == 32)
! || tic4x_lowpower )
! tic4x_oplevel |= OP_LPWR;
!
! if ( ( tic4x_cpu == 30 && tic4x_revision >= 7)
! || (tic4x_cpu == 31 && tic4x_revision >= 5)
! || (tic4x_cpu == 32)
! || (tic4x_cpu == 33)
! || (tic4x_cpu == 40 && tic4x_revision >= 5)
! || (tic4x_cpu == 44)
! || tic4x_idle2 )
! tic4x_oplevel |= OP_IDLE2;
/* Create hash table for mnemonics. */
! tic4x_op_hash = hash_new ();
/* Create hash table for asg pseudo. */
! tic4x_asg_hash = hash_new ();
/* Add mnemonics to hash table, expanding conditional mnemonics on fly. */
! for (i = 0; i < tic4x_num_insts; i++)
! ok &= tic4x_inst_add ((void *) &tic4x_insts[i]);
/* Create dummy inst to avoid errors accessing end of table. */
! tic4x_inst_make ("", 0, "");
if (!ok)
as_fatal ("Broken assembler. No assembly attempted.");
/* Add registers to symbol table. */
! tic4x_init_regtable ();
/* Add predefined symbols to symbol table. */
! tic4x_init_symbols ();
}
void
! tic4x_end ()
{
bfd_set_arch_mach (stdoutput, bfd_arch_tic4x,
! IS_CPU_TIC4X (tic4x_cpu) ? bfd_mach_tic4x : bfd_mach_tic3x);
}
static int
! tic4x_indirect_parse (operand, indirect)
! tic4x_operand_t *operand;
! const tic4x_indirect_t *indirect;
{
char *n = indirect->name;
char *s = input_line_pointer;
*************** c4x_indirect_parse (operand, indirect)
*** 1552,1558 ****
{
case 'a': /* Need to match aux register. */
b = name;
! #ifdef C4X_ALT_SYNTAX
if (*s == '%')
s++;
#endif
--- 1552,1558 ----
{
case 'a': /* Need to match aux register. */
b = name;
! #ifdef TIC4X_ALT_SYNTAX
if (*s == '%')
s++;
#endif
*************** c4x_indirect_parse (operand, indirect)
*** 1573,1583 ****
return -1;
case 'd': /* Need to match constant for disp. */
! #ifdef C4X_ALT_SYNTAX
if (*s == '%') /* expr() will die if we don't skip this. */
s++;
#endif
! s = c4x_expression (s, &operand->expr);
if (operand->expr.X_op != O_constant)
return 0;
operand->disp = operand->expr.X_add_number;
--- 1573,1583 ----
return -1;
case 'd': /* Need to match constant for disp. */
! #ifdef TIC4X_ALT_SYNTAX
if (*s == '%') /* expr() will die if we don't skip this. */
s++;
#endif
! s = tic4x_expression (s, &operand->expr);
if (operand->expr.X_op != O_constant)
return 0;
operand->disp = operand->expr.X_add_number;
*************** c4x_indirect_parse (operand, indirect)
*** 1591,1601 ****
case 'y': /* Need to match IR0. */
case 'z': /* Need to match IR1. */
! #ifdef C4X_ALT_SYNTAX
if (*s == '%')
s++;
#endif
! s = c4x_expression (s, &operand->expr);
if (operand->expr.X_op != O_register)
return 0;
if (operand->expr.X_add_number != REG_IR0
--- 1591,1601 ----
case 'y': /* Need to match IR0. */
case 'z': /* Need to match IR1. */
! #ifdef TIC4X_ALT_SYNTAX
if (*s == '%')
s++;
#endif
! s = tic4x_expression (s, &operand->expr);
if (operand->expr.X_op != O_register)
return 0;
if (operand->expr.X_add_number != REG_IR0
*************** c4x_indirect_parse (operand, indirect)
*** 1635,1643 ****
}
static char *
! c4x_operand_parse (s, operand)
char *s;
! c4x_operand_t *operand;
{
unsigned int i;
char c;
--- 1635,1643 ----
}
static char *
! tic4x_operand_parse (s, operand)
char *s;
! tic4x_operand_t *operand;
{
unsigned int i;
char c;
*************** c4x_operand_parse (s, operand)
*** 1654,1660 ****
str = input_line_pointer;
c = get_symbol_end (); /* Get terminator. */
new = input_line_pointer;
! if (strlen (str) && (entry = hash_find (c4x_asg_hash, str)) != NULL)
{
*input_line_pointer = c;
input_line_pointer = (char *) entry;
--- 1654,1660 ----
str = input_line_pointer;
c = get_symbol_end (); /* Get terminator. */
new = input_line_pointer;
! if (strlen (str) && (entry = hash_find (tic4x_asg_hash, str)) != NULL)
{
*input_line_pointer = c;
input_line_pointer = (char *) entry;
*************** c4x_operand_parse (s, operand)
*** 1668,1676 ****
operand->mode = M_UNKNOWN;
switch (*input_line_pointer)
{
! #ifdef C4X_ALT_SYNTAX
case '%':
! input_line_pointer = c4x_expression (++input_line_pointer, exp);
if (exp->X_op != O_register)
as_bad ("Expecting a register name");
operand->mode = M_REGISTER;
--- 1668,1676 ----
operand->mode = M_UNKNOWN;
switch (*input_line_pointer)
{
! #ifdef TIC4X_ALT_SYNTAX
case '%':
! input_line_pointer = tic4x_expression (++input_line_pointer, exp);
if (exp->X_op != O_register)
as_bad ("Expecting a register name");
operand->mode = M_REGISTER;
*************** c4x_operand_parse (s, operand)
*** 1678,1684 ****
case '^':
/* Denotes high 16 bits. */
! input_line_pointer = c4x_expression (++input_line_pointer, exp);
if (exp->X_op == O_constant)
operand->mode = M_IMMED;
else if (exp->X_op == O_big)
--- 1678,1684 ----
case '^':
/* Denotes high 16 bits. */
! input_line_pointer = tic4x_expression (++input_line_pointer, exp);
if (exp->X_op == O_constant)
operand->mode = M_IMMED;
else if (exp->X_op == O_big)
*************** c4x_operand_parse (s, operand)
*** 1687,1693 ****
as_bad ("Number too large"); /* bignum required */
else
{
! c4x_gen_to_words (generic_floating_point_number,
operand->fwords, S_PRECISION);
operand->mode = M_IMMED_F;
}
--- 1687,1693 ----
as_bad ("Number too large"); /* bignum required */
else
{
! tic4x_gen_to_words (generic_floating_point_number,
operand->fwords, S_PRECISION);
operand->mode = M_IMMED_F;
}
*************** c4x_operand_parse (s, operand)
*** 1701,1707 ****
}
case '#':
! input_line_pointer = c4x_expression (++input_line_pointer, exp);
if (exp->X_op == O_constant)
operand->mode = M_IMMED;
else if (exp->X_op == O_big)
--- 1701,1707 ----
}
case '#':
! input_line_pointer = tic4x_expression (++input_line_pointer, exp);
if (exp->X_op == O_constant)
operand->mode = M_IMMED;
else if (exp->X_op == O_big)
*************** c4x_operand_parse (s, operand)
*** 1710,1716 ****
as_bad ("Number too large"); /* bignum required. */
else
{
! c4x_gen_to_words (generic_floating_point_number,
operand->fwords, S_PRECISION);
operand->mode = M_IMMED_F;
}
--- 1710,1716 ----
as_bad ("Number too large"); /* bignum required. */
else
{
! tic4x_gen_to_words (generic_floating_point_number,
operand->fwords, S_PRECISION);
operand->mode = M_IMMED_F;
}
*************** c4x_operand_parse (s, operand)
*** 1729,1735 ****
case '\\':
#endif
case '@':
! input_line_pointer = c4x_expression (++input_line_pointer, exp);
if (exp->X_op != O_constant && exp->X_op != O_symbol)
as_bad ("Bad direct addressing construct %s", s);
if (exp->X_op == O_constant)
--- 1729,1735 ----
case '\\':
#endif
case '@':
! input_line_pointer = tic4x_expression (++input_line_pointer, exp);
if (exp->X_op != O_constant && exp->X_op != O_symbol)
as_bad ("Bad direct addressing construct %s", s);
if (exp->X_op == O_constant)
*************** c4x_operand_parse (s, operand)
*** 1743,1758 ****
case '*':
ret = -1;
! for (i = 0; i < c4x_num_indirects; i++)
! if ((ret = c4x_indirect_parse (operand, &c4x_indirects[i])))
break;
if (ret < 0)
break;
! if (i < c4x_num_indirects)
{
operand->mode = M_INDIRECT;
/* Indirect addressing mode number. */
! operand->expr.X_add_number = c4x_indirects[i].modn;
/* Convert *+ARn(0) to *ARn etc. Maybe we should
squeal about silly ones? */
if (operand->expr.X_add_number < 0x08 && !operand->disp)
--- 1743,1758 ----
case '*':
ret = -1;
! for (i = 0; i < tic4x_num_indirects; i++)
! if ((ret = tic4x_indirect_parse (operand, &tic4x_indirects[i])))
break;
if (ret < 0)
break;
! if (i < tic4x_num_indirects)
{
operand->mode = M_INDIRECT;
/* Indirect addressing mode number. */
! operand->expr.X_add_number = tic4x_indirects[i].modn;
/* Convert *+ARn(0) to *ARn etc. Maybe we should
squeal about silly ones? */
if (operand->expr.X_add_number < 0x08 && !operand->disp)
*************** c4x_operand_parse (s, operand)
*** 1765,1771 ****
default:
operand->mode = M_IMMED; /* Assume immediate. */
str = input_line_pointer;
! input_line_pointer = c4x_expression (input_line_pointer, exp);
if (exp->X_op == O_register)
{
know (exp->X_add_symbol == 0);
--- 1765,1771 ----
default:
operand->mode = M_IMMED; /* Assume immediate. */
str = input_line_pointer;
! input_line_pointer = tic4x_expression (input_line_pointer, exp);
if (exp->X_op == O_register)
{
know (exp->X_add_symbol == 0);
*************** c4x_operand_parse (s, operand)
*** 1779,1791 ****
as_bad ("Number too large"); /* bignum required. */
else
{
! c4x_gen_to_words (generic_floating_point_number,
operand->fwords, S_PRECISION);
operand->mode = M_IMMED_F;
}
break;
}
! #ifdef C4X_ALT_SYNTAX
/* Allow ldi foo, ar0 to be equivalent to ldi @foo, ar0. */
else if (exp->X_op == O_symbol)
{
--- 1779,1791 ----
as_bad ("Number too large"); /* bignum required. */
else
{
! tic4x_gen_to_words (generic_floating_point_number,
operand->fwords, S_PRECISION);
operand->mode = M_IMMED_F;
}
break;
}
! #ifdef TIC4X_ALT_SYNTAX
/* Allow ldi foo, ar0 to be equivalent to ldi @foo, ar0. */
else if (exp->X_op == O_symbol)
{
*************** c4x_operand_parse (s, operand)
*** 1801,1815 ****
}
static int
! c4x_operands_match (inst, insn, check)
! c4x_inst_t *inst;
! c4x_insn_t *insn;
int check;
{
const char *args = inst->args;
unsigned long opcode = inst->opcode;
int num_operands = insn->num_operands;
! c4x_operand_t *operand = insn->operands;
expressionS *exp = &operand->expr;
int ret = 1;
int reg;
--- 1801,1815 ----
}
static int
! tic4x_operands_match (inst, insn, check)
! tic4x_inst_t *inst;
! tic4x_insn_t *insn;
int check;
{
const char *args = inst->args;
unsigned long opcode = inst->opcode;
int num_operands = insn->num_operands;
! tic4x_operand_t *operand = insn->operands;
expressionS *exp = &operand->expr;
int ret = 1;
int reg;
*************** c4x_operands_match (inst, insn, check)
*** 1850,1857 ****
use an immediate mode form of ldiu or ldpk instruction. */
if (exp->X_op == O_constant)
{
! if( ( IS_CPU_C4X (c4x_cpu) && exp->X_add_number <= 65535 )
! || ( IS_CPU_C3X (c4x_cpu) && exp->X_add_number <= 255 ) )
{
INSERTS (opcode, exp->X_add_number, 15, 0);
continue;
--- 1850,1857 ----
use an immediate mode form of ldiu or ldpk instruction. */
if (exp->X_op == O_constant)
{
! if( ( IS_CPU_TIC4X (tic4x_cpu) && exp->X_add_number <= 65535 )
! || ( IS_CPU_TIC3X (tic4x_cpu) && exp->X_add_number <= 255 ) )
{
INSERTS (opcode, exp->X_add_number, 15, 0);
continue;
*************** c4x_operands_match (inst, insn, check)
*** 1924,1930 ****
continue;
}
}
! if (IS_CPU_C4X (c4x_cpu))
{
insn->reloc = BFD_RELOC_24_PCREL;
insn->pcrel = 1;
--- 1924,1930 ----
continue;
}
}
! if (IS_CPU_TIC4X (tic4x_cpu))
{
insn->reloc = BFD_RELOC_24_PCREL;
insn->pcrel = 1;
*************** c4x_operands_match (inst, insn, check)
*** 1938,1944 ****
continue;
case 'C':
! if (!IS_CPU_C4X (c4x_cpu))
break;
if (operand->mode != M_INDIRECT)
break;
--- 1938,1944 ----
continue;
case 'C':
! if (!IS_CPU_TIC4X (tic4x_cpu))
break;
if (operand->mode != M_INDIRECT)
break;
*************** c4x_operands_match (inst, insn, check)
*** 1966,1972 ****
break;
reg = exp->X_add_number;
if ( (reg >= REG_R0 && reg <= REG_R7)
! || (IS_CPU_C4X (c4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 7, 0);
else
{
--- 1966,1972 ----
break;
reg = exp->X_add_number;
if ( (reg >= REG_R0 && reg <= REG_R7)
! || (IS_CPU_TIC4X (tic4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 7, 0);
else
{
*************** c4x_operands_match (inst, insn, check)
*** 1989,1995 ****
/* Create floating point number string. */
sprintf (string, "%d.0", (int) exp->X_add_number);
! c4x_atof (string, 's', operand->fwords);
}
INSERTU (opcode, operand->fwords[0], 15, 0);
--- 1989,1995 ----
/* Create floating point number string. */
sprintf (string, "%d.0", (int) exp->X_add_number);
! tic4x_atof (string, 's', operand->fwords);
}
INSERTU (opcode, operand->fwords[0], 15, 0);
*************** c4x_operands_match (inst, insn, check)
*** 2006,2012 ****
break;
reg = exp->X_add_number;
if ( (reg >= REG_R0 && reg <= REG_R7)
! || (IS_CPU_C4X (c4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 15, 8);
else
{
--- 2006,2012 ----
break;
reg = exp->X_add_number;
if ( (reg >= REG_R0 && reg <= REG_R7)
! || (IS_CPU_TIC4X (tic4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 15, 8);
else
{
*************** c4x_operands_match (inst, insn, check)
*** 2032,2038 ****
case 'i':
if ( operand->mode == M_REGISTER
! && c4x_oplevel & OP_ENH )
{
reg = exp->X_add_number;
INSERTU (opcode, reg, 4, 0);
--- 2032,2038 ----
case 'i':
if ( operand->mode == M_REGISTER
! && tic4x_oplevel & OP_ENH )
{
reg = exp->X_add_number;
INSERTU (opcode, reg, 4, 0);
*************** c4x_operands_match (inst, insn, check)
*** 2046,2052 ****
break;
if (operand->disp != 0 && operand->disp != 1)
{
! if (IS_CPU_C4X (c4x_cpu))
break;
if (!check)
as_bad ("Invalid indirect addressing mode displacement %d",
--- 2046,2052 ----
break;
if (operand->disp != 0 && operand->disp != 1)
{
! if (IS_CPU_TIC4X (tic4x_cpu))
break;
if (!check)
as_bad ("Invalid indirect addressing mode displacement %d",
*************** c4x_operands_match (inst, insn, check)
*** 2060,2066 ****
case 'j':
if ( operand->mode == M_REGISTER
! && c4x_oplevel & OP_ENH )
{
reg = exp->X_add_number;
INSERTU (opcode, reg, 12, 8);
--- 2060,2066 ----
case 'j':
if ( operand->mode == M_REGISTER
! && tic4x_oplevel & OP_ENH )
{
reg = exp->X_add_number;
INSERTU (opcode, reg, 12, 8);
*************** c4x_operands_match (inst, insn, check)
*** 2074,2080 ****
break;
if (operand->disp != 0 && operand->disp != 1)
{
! if (IS_CPU_C4X (c4x_cpu))
break;
if (!check)
as_bad ("Invalid indirect addressing mode displacement %d",
--- 2074,2080 ----
break;
if (operand->disp != 0 && operand->disp != 1)
{
! if (IS_CPU_TIC4X (tic4x_cpu))
break;
if (!check)
as_bad ("Invalid indirect addressing mode displacement %d",
*************** c4x_operands_match (inst, insn, check)
*** 2143,2149 ****
continue;
case 'O':
! if (!IS_CPU_C4X (c4x_cpu))
break;
if (operand->mode != M_INDIRECT)
break;
--- 2143,2149 ----
continue;
case 'O':
! if (!IS_CPU_TIC4X (tic4x_cpu))
break;
if (operand->mode != M_INDIRECT)
break;
*************** c4x_operands_match (inst, insn, check)
*** 2197,2203 ****
break;
reg = exp->X_add_number;
if ( (reg >= REG_R0 && reg <= REG_R7)
! || (IS_CPU_C4X (c4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 15, 0);
else
{
--- 2197,2203 ----
break;
reg = exp->X_add_number;
if ( (reg >= REG_R0 && reg <= REG_R7)
! || (IS_CPU_TIC4X (tic4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 15, 0);
else
{
*************** c4x_operands_match (inst, insn, check)
*** 2219,2225 ****
break;
reg = exp->X_add_number;
if ( (reg >= REG_R0 && reg <= REG_R7)
! || (IS_CPU_C4X (c4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 20, 16);
else
{
--- 2219,2225 ----
break;
reg = exp->X_add_number;
if ( (reg >= REG_R0 && reg <= REG_R7)
! || (IS_CPU_TIC4X (tic4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 20, 16);
else
{
*************** c4x_operands_match (inst, insn, check)
*** 2276,2283 ****
insn->exp = *exp;
continue;
! case 'T': /* 5-bit immediate value for c4x stik. */
! if (!IS_CPU_C4X (c4x_cpu))
break;
if (operand->mode != M_IMMED)
break;
--- 2276,2283 ----
insn->exp = *exp;
continue;
! case 'T': /* 5-bit immediate value for tic4x stik. */
! if (!IS_CPU_TIC4X (tic4x_cpu))
break;
if (operand->mode != M_IMMED)
break;
*************** c4x_operands_match (inst, insn, check)
*** 2337,2348 ****
break;
if (exp->X_op == O_constant)
{
! if (exp->X_add_number < 512 && IS_CPU_C4X (c4x_cpu))
{
INSERTU (opcode, exp->X_add_number, 8, 0);
continue;
}
! else if (exp->X_add_number < 32 && IS_CPU_C3X (c4x_cpu))
{
INSERTU (opcode, exp->X_add_number | 0x20, 4, 0);
continue;
--- 2337,2348 ----
break;
if (exp->X_op == O_constant)
{
! if (exp->X_add_number < 512 && IS_CPU_TIC4X (tic4x_cpu))
{
INSERTU (opcode, exp->X_add_number, 8, 0);
continue;
}
! else if (exp->X_add_number < 32 && IS_CPU_TIC3X (tic4x_cpu))
{
INSERTU (opcode, exp->X_add_number | 0x20, 4, 0);
continue;
*************** c4x_operands_match (inst, insn, check)
*** 2359,2365 ****
break; /* No relocations allowed. */
case 'W': /* Short immediate int (0--7). */
! if (!IS_CPU_C4X (c4x_cpu))
break;
if (operand->mode != M_IMMED)
break;
--- 2359,2365 ----
break; /* No relocations allowed. */
case 'W': /* Short immediate int (0--7). */
! if (!IS_CPU_TIC4X (tic4x_cpu))
break;
if (operand->mode != M_IMMED)
break;
*************** c4x_operands_match (inst, insn, check)
*** 2390,2396 ****
insn->exp = *exp;
continue;
! case 'X': /* Expansion register for c4x. */
if (operand->mode != M_REGISTER)
break;
reg = exp->X_add_number;
--- 2390,2396 ----
insn->exp = *exp;
continue;
! case 'X': /* Expansion register for tic4x. */
if (operand->mode != M_REGISTER)
break;
reg = exp->X_add_number;
*************** c4x_operands_match (inst, insn, check)
*** 2404,2410 ****
}
continue;
! case 'Y': /* Address register for c4x lda. */
if (operand->mode != M_REGISTER)
break;
reg = exp->X_add_number;
--- 2404,2410 ----
}
continue;
! case 'Y': /* Address register for tic4x lda. */
if (operand->mode != M_REGISTER)
break;
reg = exp->X_add_number;
*************** c4x_operands_match (inst, insn, check)
*** 2418,2424 ****
}
continue;
! case 'Z': /* Expansion register for c4x. */
if (operand->mode != M_REGISTER)
break;
reg = exp->X_add_number;
--- 2418,2424 ----
}
continue;
! case 'Z': /* Expansion register for tic4x. */
if (operand->mode != M_REGISTER)
break;
reg = exp->X_add_number;
*************** c4x_operands_match (inst, insn, check)
*** 2475,2482 ****
}
static void
! c4x_insn_check (insn)
! c4x_insn_t *insn;
{
if (!strcmp(insn->name, "lda"))
--- 2475,2482 ----
}
static void
! tic4x_insn_check (insn)
! tic4x_insn_t *insn;
{
if (!strcmp(insn->name, "lda"))
*************** c4x_insn_check (insn)
*** 2507,2514 ****
}
static void
! c4x_insn_output (insn)
! c4x_insn_t *insn;
{
char *dst;
--- 2507,2514 ----
}
static void
! tic4x_insn_output (insn)
! tic4x_insn_t *insn;
{
char *dst;
*************** c4x_insn_output (insn)
*** 2533,2551 ****
/* Parse the operands. */
int
! c4x_operands_parse (s, operands, num_operands)
char *s;
! c4x_operand_t *operands;
int num_operands;
{
if (!*s)
return num_operands;
do
! s = c4x_operand_parse (s, &operands[num_operands++]);
! while (num_operands < C4X_OPERANDS_MAX && *s++ == ',');
! if (num_operands > C4X_OPERANDS_MAX)
{
as_bad ("Too many operands scanned");
return -1;
--- 2533,2551 ----
/* Parse the operands. */
int
! tic4x_operands_parse (s, operands, num_operands)
char *s;
! tic4x_operand_t *operands;
int num_operands;
{
if (!*s)
return num_operands;
do
! s = tic4x_operand_parse (s, &operands[num_operands++]);
! while (num_operands < TIC4X_OPERANDS_MAX && *s++ == ',');
! if (num_operands > TIC4X_OPERANDS_MAX)
{
as_bad ("Too many operands scanned");
return -1;
*************** md_assemble (str)
*** 2564,2571 ****
char *s;
int i;
int parsed = 0;
! c4x_inst_t *inst; /* Instruction template. */
! c4x_inst_t *first_inst;
if (str && insn->parallel)
{
--- 2564,2571 ----
char *s;
int i;
int parsed = 0;
! tic4x_inst_t *inst; /* Instruction template. */
! tic4x_inst_t *first_inst;
if (str && insn->parallel)
{
*************** md_assemble (str)
*** 2580,2586 ****
if (*s) /* Null terminate for hash_find. */
*s++ = '\0'; /* and skip past null. */
strcat (insn->name, "_");
! strncat (insn->name, str, C4X_NAME_MAX - strlen (insn->name));
/* Kludge to overcome problems with scrubber removing
space between mnemonic and indirect operand (starting with *)
--- 2580,2586 ----
if (*s) /* Null terminate for hash_find. */
*s++ = '\0'; /* and skip past null. */
strcat (insn->name, "_");
! strncat (insn->name, str, TIC4X_NAME_MAX - strlen (insn->name));
/* Kludge to overcome problems with scrubber removing
space between mnemonic and indirect operand (starting with *)
*************** md_assemble (str)
*** 2590,2596 ****
insn->operands[insn->num_operands++].mode = M_PARALLEL;
! if ((i = c4x_operands_parse
(s, insn->operands, insn->num_operands)) < 0)
{
insn->parallel = 0;
--- 2590,2596 ----
insn->operands[insn->num_operands++].mode = M_PARALLEL;
! if ((i = tic4x_operands_parse
(s, insn->operands, insn->num_operands)) < 0)
{
insn->parallel = 0;
*************** md_assemble (str)
*** 2603,2610 ****
if (insn->in_use)
{
! if ((insn->inst = (struct c4x_inst *)
! hash_find (c4x_op_hash, insn->name)) == NULL)
{
as_bad ("Unknown opcode `%s'.", insn->name);
insn->parallel = 0;
--- 2603,2610 ----
if (insn->in_use)
{
! if ((insn->inst = (struct tic4x_inst *)
! hash_find (tic4x_op_hash, insn->name)) == NULL)
{
as_bad ("Unknown opcode `%s'.", insn->name);
insn->parallel = 0;
*************** md_assemble (str)
*** 2616,2622 ****
first_inst = NULL;
do
{
! ok = c4x_operands_match (inst, insn, 1);
if (ok < 0)
{
if (!first_inst)
--- 2616,2622 ----
first_inst = NULL;
do
{
! ok = tic4x_operands_match (inst, insn, 1);
if (ok < 0)
{
if (!first_inst)
*************** md_assemble (str)
*** 2627,2639 ****
if (ok > 0)
{
! c4x_insn_check (insn);
! c4x_insn_output (insn);
}
else if (!ok)
{
if (first_inst)
! c4x_operands_match (first_inst, insn, 0);
as_bad ("Invalid operands for %s", insn->name);
}
else
--- 2627,2639 ----
if (ok > 0)
{
! tic4x_insn_check (insn);
! tic4x_insn_output (insn);
}
else if (!ok)
{
if (first_inst)
! tic4x_operands_match (first_inst, insn, 0);
as_bad ("Invalid operands for %s", insn->name);
}
else
*************** md_assemble (str)
*** 2648,2656 ****
s++;
if (*s) /* Null terminate for hash_find. */
*s++ = '\0'; /* and skip past null. */
! strncpy (insn->name, str, C4X_NAME_MAX - 3);
! if ((i = c4x_operands_parse (s, insn->operands, 0)) < 0)
{
insn->inst = NULL; /* Flag that error occured. */
insn->parallel = 0;
--- 2648,2656 ----
s++;
if (*s) /* Null terminate for hash_find. */
*s++ = '\0'; /* and skip past null. */
! strncpy (insn->name, str, TIC4X_NAME_MAX - 3);
! if ((i = tic4x_operands_parse (s, insn->operands, 0)) < 0)
{
insn->inst = NULL; /* Flag that error occured. */
insn->parallel = 0;
*************** md_assemble (str)
*** 2666,2672 ****
}
void
! c4x_cleanup ()
{
if (insn->in_use)
md_assemble (NULL);
--- 2666,2672 ----
}
void
! tic4x_cleanup ()
{
if (insn->in_use)
md_assemble (NULL);
*************** md_atof (type, litP, sizeP)
*** 2726,2732 ****
if (ieee)
t = atof_ieee (input_line_pointer, type, words);
else
! t = c4x_atof (input_line_pointer, type, words);
if (t)
input_line_pointer = t;
*sizeP = prec * sizeof (LITTLENUM_TYPE);
--- 2726,2732 ----
if (ieee)
t = atof_ieee (input_line_pointer, type, words);
else
! t = tic4x_atof (input_line_pointer, type, words);
if (t)
input_line_pointer = t;
*sizeP = prec * sizeof (LITTLENUM_TYPE);
*************** md_apply_fix3 (fixP, value, seg)
*** 2799,2805 ****
if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) fixP->fx_done = 1;
}
! /* Should never be called for c4x. */
void
md_convert_frag (headers, sec, fragP)
bfd *headers ATTRIBUTE_UNUSED;
--- 2799,2805 ----
if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) fixP->fx_done = 1;
}
! /* Should never be called for tic4x. */
void
md_convert_frag (headers, sec, fragP)
bfd *headers ATTRIBUTE_UNUSED;
*************** md_convert_frag (headers, sec, fragP)
*** 2809,2815 ****
as_fatal ("md_convert_frag");
}
! /* Should never be called for c4x. */
void
md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
char *ptr ATTRIBUTE_UNUSED;
--- 2809,2815 ----
as_fatal ("md_convert_frag");
}
! /* Should never be called for tic4x. */
void
md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
char *ptr ATTRIBUTE_UNUSED;
*************** md_create_short_jump (ptr, from_addr, to
*** 2821,2827 ****
as_fatal ("md_create_short_jmp\n");
}
! /* Should never be called for c4x. */
void
md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
char *ptr ATTRIBUTE_UNUSED;
--- 2821,2827 ----
as_fatal ("md_create_short_jmp\n");
}
! /* Should never be called for tic4x. */
void
md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
char *ptr ATTRIBUTE_UNUSED;
*************** md_create_long_jump (ptr, from_addr, to_
*** 2833,2839 ****
as_fatal ("md_create_long_jump\n");
}
! /* Should never be called for c4x. */
int
md_estimate_size_before_relax (fragP, segtype)
register fragS *fragP ATTRIBUTE_UNUSED;
--- 2833,2839 ----
as_fatal ("md_create_long_jump\n");
}
! /* Should never be called for tic4x. */
int
md_estimate_size_before_relax (fragP, segtype)
register fragS *fragP ATTRIBUTE_UNUSED;
*************** md_parse_option (c, arg)
*** 2854,2902 ****
case OPTION_CPU: /* cpu brand */
if (tolower (*arg) == 'c')
arg++;
! c4x_cpu = atoi (arg);
! if (!IS_CPU_C3X (c4x_cpu) && !IS_CPU_C4X (c4x_cpu))
! as_warn ("Unsupported processor generation %d", c4x_cpu);
break;
case OPTION_REV: /* cpu revision */
! c4x_revision = atoi (arg);
break;
case 'b':
as_warn ("Option -b is depreciated, please use -mbig");
case OPTION_BIG: /* big model */
! c4x_big_model = 1;
break;
case 'p':
as_warn ("Option -p is depreciated, please use -mmemparm");
case OPTION_MEMPARM: /* push args */
! c4x_reg_args = 0;
break;
case 'r':
as_warn ("Option -r is depreciated, please use -mregparm");
case OPTION_REGPARM: /* register args */
! c4x_reg_args = 1;
break;
case 's':
as_warn ("Option -s is depreciated, please use -msmall");
case OPTION_SMALL: /* small model */
! c4x_big_model = 0;
break;
case OPTION_IDLE2:
! c4x_idle2 = 1;
break;
case OPTION_LOWPOWER:
! c4x_lowpower = 1;
break;
case OPTION_ENHANCED:
! c4x_enhanced = 1;
break;
default:
--- 2854,2902 ----
case OPTION_CPU: /* cpu brand */
if (tolower (*arg) == 'c')
arg++;
! tic4x_cpu = atoi (arg);
! if (!IS_CPU_TIC3X (tic4x_cpu) && !IS_CPU_TIC4X (tic4x_cpu))
! as_warn ("Unsupported processor generation %d", tic4x_cpu);
break;
case OPTION_REV: /* cpu revision */
! tic4x_revision = atoi (arg);
break;
case 'b':
as_warn ("Option -b is depreciated, please use -mbig");
case OPTION_BIG: /* big model */
! tic4x_big_model = 1;
break;
case 'p':
as_warn ("Option -p is depreciated, please use -mmemparm");
case OPTION_MEMPARM: /* push args */
! tic4x_reg_args = 0;
break;
case 'r':
as_warn ("Option -r is depreciated, please use -mregparm");
case OPTION_REGPARM: /* register args */
! tic4x_reg_args = 1;
break;
case 's':
as_warn ("Option -s is depreciated, please use -msmall");
case OPTION_SMALL: /* small model */
! tic4x_big_model = 0;
break;
case OPTION_IDLE2:
! tic4x_idle2 = 1;
break;
case OPTION_LOWPOWER:
! tic4x_lowpower = 1;
break;
case OPTION_ENHANCED:
! tic4x_enhanced = 1;
break;
default:
*************** md_show_usage (stream)
*** 2936,2942 ****
definitions of TI C3x tools style local labels $n where n is a single
decimal digit. */
int
! c4x_unrecognized_line (c)
int c;
{
int lab;
--- 2936,2942 ----
definitions of TI C3x tools style local labels $n where n is a single
decimal digit. */
int
! tic4x_unrecognized_line (c)
int c;
{
int lab;
*************** md_section_align (segment, size)
*** 3018,3024 ****
}
static int
! c4x_pc_offset (op)
unsigned int op;
{
/* Determine the PC offset for a C[34]x instruction.
--- 3018,3024 ----
}
static int
! tic4x_pc_offset (op)
unsigned int op;
{
/* Determine the PC offset for a C[34]x instruction.
*************** md_pcrel_from (fixP)
*** 3090,3102 ****
op = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
return ((fixP->fx_where + fixP->fx_frag->fr_address) >> 2) +
! c4x_pc_offset (op);
}
/* Fill the alignment area with NOP's on .text, unless fill-data
was specified. */
int
! c4x_do_align (alignment, fill, len, max)
int alignment ATTRIBUTE_UNUSED;
const char *fill ATTRIBUTE_UNUSED;
int len ATTRIBUTE_UNUSED;
--- 3090,3102 ----
op = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
return ((fixP->fx_where + fixP->fx_frag->fr_address) >> 2) +
! tic4x_pc_offset (op);
}
/* Fill the alignment area with NOP's on .text, unless fill-data
was specified. */
int
! tic4x_do_align (alignment, fill, len, max)
int alignment ATTRIBUTE_UNUSED;
const char *fill ATTRIBUTE_UNUSED;
int len ATTRIBUTE_UNUSED;
*************** c4x_do_align (alignment, fill, len, max)
*** 3129,3135 ****
/* Look for and remove parallel instruction operator ||. */
void
! c4x_start_line ()
{
char *s = input_line_pointer;
--- 3129,3135 ----
/* Look for and remove parallel instruction operator ||. */
void
! tic4x_start_line ()
{
char *s = input_line_pointer;
Index: gas/config/tc-tic4x.h
===================================================================
RCS file: /cvs/src/src/gas/config/tc-tic4x.h,v
retrieving revision 1.2
diff -c -3 -p -r1.2 tc-tic4x.h
*** gas/config/tc-tic4x.h 11 Nov 2002 14:29:01 -0000 1.2
--- gas/config/tc-tic4x.h 2 Apr 2003 16:31:51 -0000
***************
*** 20,26 ****
the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define TC_TIC4X
! #define C4X
#ifndef BFD_ASSEMBLER
#error TMS320C4x requires BFD_ASSEMBLER
--- 20,26 ----
the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define TC_TIC4X
! #define TIC4X
#ifndef BFD_ASSEMBLER
#error TMS320C4x requires BFD_ASSEMBLER
***************
*** 80,100 ****
/* Accept numbers with a suffix, e.g. 0ffffh, 1010b. */
#define NUMBERS_WITH_SUFFIX 1
! extern int c4x_unrecognized_line PARAMS ((int));
! #define tc_unrecognized_line(c) c4x_unrecognized_line (c)
#define md_number_to_chars number_to_chars_littleendian
! extern int c4x_do_align PARAMS ((int, const char *, int, int));
! #define md_do_align(n,fill,len,max,label) if( c4x_do_align (n,fill,len,max) ) goto label;
/* Start of line hook to remove parallel instruction operator || */
! extern void c4x_start_line PARAMS ((void));
! #define md_start_line_hook() c4x_start_line()
! extern void c4x_cleanup PARAMS ((void));
! #define md_cleanup() c4x_cleanup()
! extern void c4x_end PARAMS ((void));
! #define md_end() c4x_end()
--- 80,100 ----
/* Accept numbers with a suffix, e.g. 0ffffh, 1010b. */
#define NUMBERS_WITH_SUFFIX 1
! extern int tic4x_unrecognized_line PARAMS ((int));
! #define tc_unrecognized_line(c) tic4x_unrecognized_line (c)
#define md_number_to_chars number_to_chars_littleendian
! extern int tic4x_do_align PARAMS ((int, const char *, int, int));
! #define md_do_align(n,fill,len,max,label) if( tic4x_do_align (n,fill,len,max) ) goto label;
/* Start of line hook to remove parallel instruction operator || */
! extern void tic4x_start_line PARAMS ((void));
! #define md_start_line_hook() tic4x_start_line()
! extern void tic4x_cleanup PARAMS ((void));
! #define md_cleanup() tic4x_cleanup()
! extern void tic4x_end PARAMS ((void));
! #define md_end() tic4x_end()
Index: include/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/ChangeLog,v
retrieving revision 1.204
diff -c -3 -p -r1.204 ChangeLog
*** include/ChangeLog 1 Apr 2003 15:50:30 -0000 1.204
--- include/ChangeLog 2 Apr 2003 16:31:51 -0000
***************
*** 1,3 ****
--- 1,10 ----
+ 2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
+
+ * coff/tic4x.h: Namespace cleanup. Replace s/c4x/tic4x
+ and s/c3x/tic3x/
+ * coff/tc-tic4x.h: Ditto
+ * opcode/tic4x.h: Ditto
+
2003-04-01 Bob Wilson <bob dot wilson at acm dot org>
* dis-asm.h (print_insn_xtensa): Declare.
Index: include/coff/tic4x.h
===================================================================
RCS file: /cvs/src/src/include/coff/tic4x.h,v
retrieving revision 1.2
diff -c -3 -p -r1.2 tic4x.h
*** include/coff/tic4x.h 20 Jan 2003 22:34:39 -0000 1.2
--- include/coff/tic4x.h 2 Apr 2003 16:31:51 -0000
***************
*** 31,42 ****
#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC
#define TICOFF_TARGET_MACHINE_GET(FLAGS) \
! (((FLAGS) & F_VERS) ? bfd_mach_c4x : bfd_mach_c3x)
#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) \
do \
{ \
! if ((MACHINE) == bfd_mach_c4x) \
*(FLAGSP) |= F_VERS; \
} \
while (0)
--- 31,42 ----
#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC
#define TICOFF_TARGET_MACHINE_GET(FLAGS) \
! (((FLAGS) & F_VERS) ? bfd_mach_tic4x : bfd_mach_tic3x)
#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) \
do \
{ \
! if ((MACHINE) == bfd_mach_tic4x) \
*(FLAGSP) |= F_VERS; \
} \
while (0)
Index: include/opcode/tic4x.h
===================================================================
RCS file: /cvs/src/src/include/opcode/tic4x.h,v
retrieving revision 1.5
diff -c -3 -p -r1.5 tic4x.h
*** include/opcode/tic4x.h 19 Nov 2002 11:59:12 -0000 1.5
--- include/opcode/tic4x.h 2 Apr 2003 16:31:51 -0000
***************
*** 19,26 ****
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
! #define IS_CPU_C3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
! #define IS_CPU_C4X(v) ((v) == 0 || (v) == 40 || (v) == 44)
/* Define some bitfield extraction/insertion macros. */
#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l))))
--- 19,26 ----
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
! #define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
! #define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44)
/* Define some bitfield extraction/insertion macros. */
#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l))))
*************** c4x_reg_t;
*** 50,71 ****
#define REG_IF REG_IIE /* C3x only */
#define REG_IOF REG_IIF /* C3x only */
! #define C3X_REG_MAX REG_RC
! #define C4X_REG_MAX REG_TVTP
/* Register table size including C4x expansion regs. */
! #define REG_TABLE_SIZE (C4X_REG_MAX + 1)
! struct c4x_register
{
char * name;
unsigned long regno;
};
! typedef struct c4x_register c4x_register_t;
/* We could store register synonyms here. */
! static const c4x_register_t c3x_registers[] =
{
{"f0", REG_R0},
{"r0", REG_R0},
--- 50,71 ----
#define REG_IF REG_IIE /* C3x only */
#define REG_IOF REG_IIF /* C3x only */
! #define TIC3X_REG_MAX REG_RC
! #define TIC4X_REG_MAX REG_TVTP
/* Register table size including C4x expansion regs. */
! #define REG_TABLE_SIZE (TIC4X_REG_MAX + 1)
! struct tic4x_register
{
char * name;
unsigned long regno;
};
! typedef struct tic4x_register tic4x_register_t;
/* We could store register synonyms here. */
! static const tic4x_register_t tic3x_registers[] =
{
{"f0", REG_R0},
{"r0", REG_R0},
*************** static const c4x_register_t c3x_register
*** 106,115 ****
{"", 0}
};
! const unsigned int c3x_num_registers = (((sizeof c3x_registers) / (sizeof c3x_registers[0])) - 1);
/* Define C4x registers in addition to C3x registers. */
! static const c4x_register_t c4x_registers[] =
{
{"die", REG_DIE}, /* Clobbers C3x REG_IE */
{"iie", REG_IIE}, /* Clobbers C3x REG_IF */
--- 106,115 ----
{"", 0}
};
! const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1);
/* Define C4x registers in addition to C3x registers. */
! static const tic4x_register_t tic4x_registers[] =
{
{"die", REG_DIE}, /* Clobbers C3x REG_IE */
{"iie", REG_IIE}, /* Clobbers C3x REG_IF */
*************** static const c4x_register_t c4x_register
*** 127,145 ****
{"", 0}
};
! const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1);
! struct c4x_cond
{
char * name;
unsigned long cond;
};
! typedef struct c4x_cond c4x_cond_t;
/* Define conditional branch/load suffixes. Put desired form for
disassembler last. */
! static const c4x_cond_t c4x_conds[] =
{
{ "u", 0x00 },
{ "c", 0x01 }, { "lo", 0x01 },
--- 127,145 ----
{"", 0}
};
! const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1);
! struct tic4x_cond
{
char * name;
unsigned long cond;
};
! typedef struct tic4x_cond tic4x_cond_t;
/* Define conditional branch/load suffixes. Put desired form for
disassembler last. */
! static const tic4x_cond_t tic4x_conds[] =
{
{ "u", 0x00 },
{ "c", 0x01 }, { "lo", 0x01 },
*************** static const c4x_cond_t c4x_conds[] =
*** 167,188 ****
{ "", 0x0}
};
! const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1);
! struct c4x_indirect
{
char * name;
unsigned long modn;
};
! typedef struct c4x_indirect c4x_indirect_t;
/* Define indirect addressing modes where:
d displacement (signed)
y ir0
z ir1 */
! static const c4x_indirect_t c4x_indirects[] =
{
{ "*+a(d)", 0x00 },
{ "*-a(d)", 0x01 },
--- 167,188 ----
{ "", 0x0}
};
! const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1);
! struct tic4x_indirect
{
char * name;
unsigned long modn;
};
! typedef struct tic4x_indirect tic4x_indirect_t;
/* Define indirect addressing modes where:
d displacement (signed)
y ir0
z ir1 */
! static const tic4x_indirect_t tic4x_indirects[] =
{
{ "*+a(d)", 0x00 },
{ "*-a(d)", 0x01 },
*************** static const c4x_indirect_t c4x_indirect
*** 216,227 ****
{ "", 0x0}
};
! #define C3X_MODN_MAX 0x19
! const unsigned int c4x_num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);
/* Instruction template. */
! struct c4x_inst
{
char * name;
unsigned long opcode;
--- 216,227 ----
{ "", 0x0}
};
! #define TIC3X_MODN_MAX 0x19
! const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1);
/* Instruction template. */
! struct tic4x_inst
{
char * name;
unsigned long opcode;
*************** struct c4x_inst
*** 230,236 ****
unsigned long oplevel;
};
! typedef struct c4x_inst c4x_inst_t;
/* Opcode infix
B condition 16--20 U,C,Z,LO,HI, etc.
--- 230,236 ----
unsigned long oplevel;
};
! typedef struct tic4x_inst tic4x_inst_t;
/* Opcode infix
B condition 16--20 U,C,Z,LO,HI, etc.
*************** typedef struct c4x_inst c4x_inst_t;
*** 278,285 ****
Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP
*/
! #define C4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */
! #define C4X_NAME_MAX 16 /* Max number of chars in parallel name. */
/* Define the instruction level */
#define OP_C3X 0x1 /* C30 support - supported by all */
--- 278,285 ----
Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP
*/
! #define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */
! #define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */
/* Define the instruction level */
#define OP_C3X 0x1 /* C30 support - supported by all */
*************** typedef struct c4x_inst c4x_inst_t;
*** 873,880 ****
*/
! /* Define c3x opcodes for assembler and disassembler. */
! static const c4x_inst_t c4x_insts[] =
{
/* Put synonyms after the desired forms in table so that they get
overwritten in the lookup table. The disassembler will thus
--- 873,880 ----
*/
! /* Define tic4x opcodes for assembler and disassembler. */
! static const tic4x_inst_t tic4x_insts[] =
{
/* Put synonyms after the desired forms in table so that they get
overwritten in the lookup table. The disassembler will thus
*************** static const c4x_inst_t c4x_insts[] =
*** 1070,1079 ****
TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
! /* Dummy entry, not included in c3x_num_insts. This
lets code examine entry i + 1 without checking
if we've run off the end of the table. */
{ "", 0x0, 0x00, "", 0 }
};
! const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1);
--- 1070,1079 ----
TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
! /* Dummy entry, not included in tic4x_num_insts. This
lets code examine entry i + 1 without checking
if we've run off the end of the table. */
{ "", 0x0, 0x00, "", 0 }
};
! const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1);
Index: ld/ChangeLog
===================================================================
RCS file: /cvs/src/src/ld/ChangeLog,v
retrieving revision 1.891
diff -c -3 -p -r1.891 ChangeLog
*** ld/ChangeLog 1 Apr 2003 15:50:25 -0000 1.891
--- ld/ChangeLog 2 Apr 2003 16:31:52 -0000
***************
*** 1,3 ****
--- 1,11 ----
+ 2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
+
+ * emulparams/tic3xcoff.sh (SCRIPT_NAME): Namespace
+ cleanup. Replace s/c4x/tic4x and s/c3x/tic3x/
+ * emulparams/tic3xcoff_onchip.sh: Ditto
+ * emulparams/tic4xcoff.sh: Ditto
+ * scripttempl/tic4xcoff.sc: Ditto
+
2003-04-01 Bob Wilson <bob dot wilson at acm dot org>
* Makefile.am (ALL_EMULATIONS): Add eelf32xtensa.o.
Index: ld/emulparams/tic3xcoff.sh
===================================================================
RCS file: /cvs/src/src/ld/emulparams/tic3xcoff.sh,v
retrieving revision 1.2
diff -c -3 -p -r1.2 tic3xcoff.sh
*** ld/emulparams/tic3xcoff.sh 20 Jan 2003 22:34:39 -0000 1.2
--- ld/emulparams/tic3xcoff.sh 2 Apr 2003 16:31:52 -0000
***************
*** 1,6 ****
SCRIPT_NAME=tic4xcoff
! OUTPUT_FORMAT="coff2-c4x"
! OUTPUT_ARCH="c3x"
! ARCH=c3x
TEMPLATE_NAME=ticoff
OUTPUT_FORMAT_TEMPLATE=tic4x
--- 1,6 ----
SCRIPT_NAME=tic4xcoff
! OUTPUT_FORMAT="coff2-tic4x"
! OUTPUT_ARCH="tic3x"
! ARCH=tic3x
TEMPLATE_NAME=ticoff
OUTPUT_FORMAT_TEMPLATE=tic4x
Index: ld/emulparams/tic3xcoff_onchip.sh
===================================================================
RCS file: /cvs/src/src/ld/emulparams/tic3xcoff_onchip.sh,v
retrieving revision 1.1
diff -c -3 -p -r1.1 tic3xcoff_onchip.sh
*** ld/emulparams/tic3xcoff_onchip.sh 21 Jan 2003 17:09:47 -0000 1.1
--- ld/emulparams/tic3xcoff_onchip.sh 2 Apr 2003 16:31:52 -0000
***************
*** 1,7 ****
SCRIPT_NAME=tic4xcoff
! OUTPUT_FORMAT="coff2-c4x"
! OUTPUT_ARCH="c3x"
! ARCH=c3x
TEMPLATE_NAME=ticoff
OUTPUT_FORMAT_TEMPLATE=tic4x
ONCHIP=yes
--- 1,7 ----
SCRIPT_NAME=tic4xcoff
! OUTPUT_FORMAT="coff2-tic4x"
! OUTPUT_ARCH="tic3x"
! ARCH=tic3x
TEMPLATE_NAME=ticoff
OUTPUT_FORMAT_TEMPLATE=tic4x
ONCHIP=yes
Index: ld/emulparams/tic4xcoff.sh
===================================================================
RCS file: /cvs/src/src/ld/emulparams/tic4xcoff.sh,v
retrieving revision 1.2
diff -c -3 -p -r1.2 tic4xcoff.sh
*** ld/emulparams/tic4xcoff.sh 20 Jan 2003 22:34:39 -0000 1.2
--- ld/emulparams/tic4xcoff.sh 2 Apr 2003 16:31:52 -0000
***************
*** 1,6 ****
SCRIPT_NAME=tic4xcoff
! OUTPUT_FORMAT="coff2-c4x"
! OUTPUT_ARCH="c4x"
! ARCH=c4x
TEMPLATE_NAME=ticoff
OUTPUT_FORMAT_TEMPLATE=tic4x
--- 1,6 ----
SCRIPT_NAME=tic4xcoff
! OUTPUT_FORMAT="coff2-tic4x"
! OUTPUT_ARCH="tic4x"
! ARCH=tic4x
TEMPLATE_NAME=ticoff
OUTPUT_FORMAT_TEMPLATE=tic4x
Index: ld/scripttempl/tic4xcoff.sc
===================================================================
RCS file: /cvs/src/src/ld/scripttempl/tic4xcoff.sc,v
retrieving revision 1.2
diff -c -3 -p -r1.2 tic4xcoff.sc
*** ld/scripttempl/tic4xcoff.sc 20 Jan 2003 22:34:39 -0000 1.2
--- ld/scripttempl/tic4xcoff.sc 2 Apr 2003 16:31:52 -0000
***************
*** 31,38 ****
# This emulation assumes config 7.
case $OUTPUT_ARCH in
! c3x) OUTPUT_ARCHNAME="TMS320C3x" ;;
! c4x) OUTPUT_ARCHNAME="TMS320C4x" ;;
esac
case $ONCHIP in
--- 31,38 ----
# This emulation assumes config 7.
case $OUTPUT_ARCH in
! tic3x) OUTPUT_ARCHNAME="TMS320C3x" ;;
! tic4x) OUTPUT_ARCHNAME="TMS320C4x" ;;
esac
case $ONCHIP in
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.556
diff -c -3 -p -r1.556 ChangeLog
*** opcodes/ChangeLog 1 Apr 2003 13:08:06 -0000 1.556
--- opcodes/ChangeLog 2 Apr 2003 16:31:52 -0000
***************
*** 1,3 ****
--- 1,8 ----
+ 2003-04-02 Svein E. Seldal <Svein dot Seldal at solidas dot com>
+
+ * tic4x-dis.c: Namespace cleanup. Replace s/c4x/tic4x and
+ s/c3x/tic3x/
+
2003-04-01 Nick Clifton <nickc at redhat dot com>
* arm-dis.c: Remove presence of (r) and (tm) symbols.
Index: opcodes/tic4x-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/tic4x-dis.c,v
retrieving revision 1.4
diff -c -3 -p -r1.4 tic4x-dis.c
*** opcodes/tic4x-dis.c 18 Nov 2002 09:09:35 -0000 1.4
--- opcodes/tic4x-dis.c 2 Apr 2003 16:31:52 -0000
***************
*** 23,32 ****
#include "dis-asm.h"
#include "opcode/tic4x.h"
! #define C4X_DEBUG 0
! #define C4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
! #define C4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */
typedef enum
{
--- 23,32 ----
#include "dis-asm.h"
#include "opcode/tic4x.h"
! #define TIC4X_DEBUG 0
! #define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
! #define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */
typedef enum
{
*************** typedef enum
*** 43,91 ****
{
INDIRECT_SHORT,
INDIRECT_LONG,
! INDIRECT_C4X
}
indirect_t;
! static int c4x_version = 0;
! static int c4x_dp = 0;
! static int c4x_pc_offset
PARAMS ((unsigned int));
! static int c4x_print_char
PARAMS ((struct disassemble_info *, char));
! static int c4x_print_str
PARAMS ((struct disassemble_info *, char *));
! static int c4x_print_register
PARAMS ((struct disassemble_info *, unsigned long));
! static int c4x_print_addr
PARAMS ((struct disassemble_info *, unsigned long));
! static int c4x_print_relative
PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
! void c4x_print_ftoa
PARAMS ((unsigned int, FILE *, fprintf_ftype));
! static int c4x_print_direct
PARAMS ((struct disassemble_info *, unsigned long));
! static int c4x_print_immed
PARAMS ((struct disassemble_info *, immed_t, unsigned long));
! static int c4x_print_cond
PARAMS ((struct disassemble_info *, unsigned int));
! static int c4x_print_indirect
PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
! static int c4x_print_op
! PARAMS ((struct disassemble_info *, unsigned long, c4x_inst_t *, unsigned long));
! static void c4x_hash_opcode_special
! PARAMS ((c4x_inst_t **, const c4x_inst_t *));
! static void c4x_hash_opcode
! PARAMS ((c4x_inst_t **, c4x_inst_t **, const c4x_inst_t *, unsigned long));
! static int c4x_disassemble
PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
int print_insn_tic4x
PARAMS ((bfd_vma, struct disassemble_info *));
static int
! c4x_pc_offset (op)
unsigned int op;
{
/* Determine the PC offset for a C[34]x instruction.
--- 43,91 ----
{
INDIRECT_SHORT,
INDIRECT_LONG,
! INDIRECT_TIC4X
}
indirect_t;
! static int tic4x_version = 0;
! static int tic4x_dp = 0;
! static int tic4x_pc_offset
PARAMS ((unsigned int));
! static int tic4x_print_char
PARAMS ((struct disassemble_info *, char));
! static int tic4x_print_str
PARAMS ((struct disassemble_info *, char *));
! static int tic4x_print_register
PARAMS ((struct disassemble_info *, unsigned long));
! static int tic4x_print_addr
PARAMS ((struct disassemble_info *, unsigned long));
! static int tic4x_print_relative
PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
! void tic4x_print_ftoa
PARAMS ((unsigned int, FILE *, fprintf_ftype));
! static int tic4x_print_direct
PARAMS ((struct disassemble_info *, unsigned long));
! static int tic4x_print_immed
PARAMS ((struct disassemble_info *, immed_t, unsigned long));
! static int tic4x_print_cond
PARAMS ((struct disassemble_info *, unsigned int));
! static int tic4x_print_indirect
PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
! static int tic4x_print_op
! PARAMS ((struct disassemble_info *, unsigned long, tic4x_inst_t *, unsigned long));
! static void tic4x_hash_opcode_special
! PARAMS ((tic4x_inst_t **, const tic4x_inst_t *));
! static void tic4x_hash_opcode
! PARAMS ((tic4x_inst_t **, tic4x_inst_t **, const tic4x_inst_t *, unsigned long));
! static int tic4x_disassemble
PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
int print_insn_tic4x
PARAMS ((bfd_vma, struct disassemble_info *));
static int
! tic4x_pc_offset (op)
unsigned int op;
{
/* Determine the PC offset for a C[34]x instruction.
*************** c4x_pc_offset (op)
*** 143,149 ****
}
static int
! c4x_print_char (info, ch)
struct disassemble_info * info;
char ch;
{
--- 143,149 ----
}
static int
! tic4x_print_char (info, ch)
struct disassemble_info * info;
char ch;
{
*************** c4x_print_char (info, ch)
*** 153,159 ****
}
static int
! c4x_print_str (info, str)
struct disassemble_info *info;
char *str;
{
--- 153,159 ----
}
static int
! tic4x_print_str (info, str)
struct disassemble_info *info;
char *str;
{
*************** c4x_print_str (info, str)
*** 163,190 ****
}
static int
! c4x_print_register (info, regno)
struct disassemble_info *info;
unsigned long regno;
{
! static c4x_register_t **registertable = NULL;
unsigned int i;
if (registertable == NULL)
{
! registertable = (c4x_register_t **)
! xmalloc (sizeof (c4x_register_t *) * REG_TABLE_SIZE);
! for (i = 0; i < c3x_num_registers; i++)
! registertable[c3x_registers[i].regno] = (void *)&c3x_registers[i];
! if (IS_CPU_C4X (c4x_version))
{
/* Add C4x additional registers, overwriting
any C3x registers if necessary. */
! for (i = 0; i < c4x_num_registers; i++)
! registertable[c4x_registers[i].regno] = (void *)&c4x_registers[i];
}
}
! if ((int) regno > (IS_CPU_C4X (c4x_version) ? C4X_REG_MAX : C3X_REG_MAX))
return 0;
if (info != NULL)
(*info->fprintf_func) (info->stream, "%s", registertable[regno]->name);
--- 163,190 ----
}
static int
! tic4x_print_register (info, regno)
struct disassemble_info *info;
unsigned long regno;
{
! static tic4x_register_t **registertable = NULL;
unsigned int i;
if (registertable == NULL)
{
! registertable = (tic4x_register_t **)
! xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE);
! for (i = 0; i < tic3x_num_registers; i++)
! registertable[tic3x_registers[i].regno] = (void *)&tic3x_registers[i];
! if (IS_CPU_TIC4X (tic4x_version))
{
/* Add C4x additional registers, overwriting
any C3x registers if necessary. */
! for (i = 0; i < tic4x_num_registers; i++)
! registertable[tic4x_registers[i].regno] = (void *)&tic4x_registers[i];
}
}
! if ((int) regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX))
return 0;
if (info != NULL)
(*info->fprintf_func) (info->stream, "%s", registertable[regno]->name);
*************** c4x_print_register (info, regno)
*** 192,198 ****
}
static int
! c4x_print_addr (info, addr)
struct disassemble_info *info;
unsigned long addr;
{
--- 192,198 ----
}
static int
! tic4x_print_addr (info, addr)
struct disassemble_info *info;
unsigned long addr;
{
*************** c4x_print_addr (info, addr)
*** 202,225 ****
}
static int
! c4x_print_relative (info, pc, offset, opcode)
struct disassemble_info *info;
unsigned long pc;
long offset;
unsigned long opcode;
{
! return c4x_print_addr (info, pc + offset + c4x_pc_offset (opcode));
}
static int
! c4x_print_direct (info, arg)
struct disassemble_info *info;
unsigned long arg;
{
if (info != NULL)
{
(*info->fprintf_func) (info->stream, "@");
! c4x_print_addr (info, arg + (c4x_dp << 16));
}
return 1;
}
--- 202,225 ----
}
static int
! tic4x_print_relative (info, pc, offset, opcode)
struct disassemble_info *info;
unsigned long pc;
long offset;
unsigned long opcode;
{
! return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode));
}
static int
! tic4x_print_direct (info, arg)
struct disassemble_info *info;
unsigned long arg;
{
if (info != NULL)
{
(*info->fprintf_func) (info->stream, "@");
! tic4x_print_addr (info, arg + (tic4x_dp << 16));
}
return 1;
}
*************** c4x_print_direct (info, arg)
*** 227,233 ****
/* FIXME: make the floating point stuff not rely on host
floating point arithmetic. */
void
! c4x_print_ftoa (val, stream, pfunc)
unsigned int val;
FILE *stream;
fprintf_ftype pfunc;
--- 227,233 ----
/* FIXME: make the floating point stuff not rely on host
floating point arithmetic. */
void
! tic4x_print_ftoa (val, stream, pfunc)
unsigned int val;
FILE *stream;
fprintf_ftype pfunc;
*************** c4x_print_ftoa (val, stream, pfunc)
*** 253,259 ****
}
static int
! c4x_print_immed (info, type, arg)
struct disassemble_info *info;
immed_t type;
unsigned long arg;
--- 253,259 ----
}
static int
! tic4x_print_immed (info, type, arg)
struct disassemble_info *info;
immed_t type;
unsigned long arg;
*************** c4x_print_immed (info, type, arg)
*** 312,329 ****
}
static int
! c4x_print_cond (info, cond)
struct disassemble_info *info;
unsigned int cond;
{
! static c4x_cond_t **condtable = NULL;
unsigned int i;
if (condtable == NULL)
{
! condtable = (c4x_cond_t **)xmalloc (sizeof (c4x_cond_t *) * 32);
! for (i = 0; i < num_conds; i++)
! condtable[c4x_conds[i].cond] = (void *)&c4x_conds[i];
}
if (cond > 31 || condtable[cond] == NULL)
return 0;
--- 312,329 ----
}
static int
! tic4x_print_cond (info, cond)
struct disassemble_info *info;
unsigned int cond;
{
! static tic4x_cond_t **condtable = NULL;
unsigned int i;
if (condtable == NULL)
{
! condtable = (tic4x_cond_t **)xmalloc (sizeof (tic4x_cond_t *) * 32);
! for (i = 0; i < tic4x_num_conds; i++)
! condtable[tic4x_conds[i].cond] = (void *)&tic4x_conds[i];
}
if (cond > 31 || condtable[cond] == NULL)
return 0;
*************** c4x_print_cond (info, cond)
*** 333,339 ****
}
static int
! c4x_print_indirect (info, type, arg)
struct disassemble_info *info;
indirect_t type;
unsigned long arg;
--- 333,339 ----
}
static int
! tic4x_print_indirect (info, type, arg)
struct disassemble_info *info;
indirect_t type;
unsigned long arg;
*************** c4x_print_indirect (info, type, arg)
*** 348,354 ****
disp = 1;
switch(type)
{
! case INDIRECT_C4X: /* *+ARn(disp) */
disp = EXTRU (arg, 7, 3);
aregno = EXTRU (arg, 2, 0) + REG_AR0;
modn = 0;
--- 348,354 ----
disp = 1;
switch(type)
{
! case INDIRECT_TIC4X: /* *+ARn(disp) */
disp = EXTRU (arg, 7, 3);
aregno = EXTRU (arg, 2, 0) + REG_AR0;
modn = 0;
*************** c4x_print_indirect (info, type, arg)
*** 366,394 ****
return 0;
break;
default:
! abort ();
}
! if (modn > C3X_MODN_MAX)
return 0;
! a = c4x_indirects[modn].name;
while (*a)
{
switch (*a)
{
case 'a':
! c4x_print_register (info, aregno);
break;
case 'd':
! c4x_print_immed (info, IMMED_UINT, disp);
break;
case 'y':
! c4x_print_str (info, "ir0");
break;
case 'z':
! c4x_print_str (info, "ir1");
break;
default:
! c4x_print_char (info, *a);
break;
}
a++;
--- 366,395 ----
return 0;
break;
default:
! (*info->fprintf_func)(info->stream, "# internal error: Unknown indirect type %d", type);
! return 0;
}
! if (modn > TIC3X_MODN_MAX)
return 0;
! a = tic4x_indirects[modn].name;
while (*a)
{
switch (*a)
{
case 'a':
! tic4x_print_register (info, aregno);
break;
case 'd':
! tic4x_print_immed (info, IMMED_UINT, disp);
break;
case 'y':
! tic4x_print_str (info, "ir0");
break;
case 'z':
! tic4x_print_str (info, "ir1");
break;
default:
! tic4x_print_char (info, *a);
break;
}
a++;
*************** c4x_print_indirect (info, type, arg)
*** 397,406 ****
}
static int
! c4x_print_op (info, instruction, p, pc)
struct disassemble_info *info;
unsigned long instruction;
! c4x_inst_t *p;
unsigned long pc;
{
int val;
--- 398,407 ----
}
static int
! tic4x_print_op (info, instruction, p, pc)
struct disassemble_info *info;
unsigned long instruction;
! tic4x_inst_t *p;
unsigned long pc;
{
int val;
*************** c4x_print_op (info, instruction, p, pc)
*** 414,431 ****
switch (*s)
{
case 'B':
! if (! c4x_print_cond (info, EXTRU (instruction, 20, 16)))
return 0;
break;
case 'C':
! if (! c4x_print_cond (info, EXTRU (instruction, 27, 23)))
return 0;
break;
case '_':
parallel = s + 1; /* Skip past `_' in name */
break;
default:
! c4x_print_char (info, *s);
break;
}
s++;
--- 415,432 ----
switch (*s)
{
case 'B':
! if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
return 0;
break;
case 'C':
! if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
return 0;
break;
case '_':
parallel = s + 1; /* Skip past `_' in name */
break;
default:
! tic4x_print_char (info, *s);
break;
}
s++;
*************** c4x_print_op (info, instruction, p, pc)
*** 434,478 ****
/* Print arguments. */
s = p->args;
if (*s)
! c4x_print_char (info, ' ');
while (*s)
{
switch (*s)
{
case '*': /* indirect 0--15 */
! if (! c4x_print_indirect (info, INDIRECT_LONG,
EXTRU (instruction, 15, 0)))
return 0;
break;
case '#': /* only used for ldp, ldpk */
! c4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
break;
case '@': /* direct 0--15 */
! c4x_print_direct (info, EXTRU (instruction, 15, 0));
break;
case 'A': /* address register 24--22 */
! if (! c4x_print_register (info, EXTRU (instruction, 24, 22) +
REG_AR0))
return 0;
break;
case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
address 0--23. */
! if (IS_CPU_C4X (c4x_version))
! c4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
p->opcode);
else
! c4x_print_addr (info, EXTRU (instruction, 23, 0));
break;
case 'C': /* indirect (short C4x) 0--7 */
! if (! IS_CPU_C4X (c4x_version))
return 0;
! if (! c4x_print_indirect (info, INDIRECT_C4X,
EXTRU (instruction, 7, 0)))
return 0;
break;
--- 435,479 ----
/* Print arguments. */
s = p->args;
if (*s)
! tic4x_print_char (info, ' ');
while (*s)
{
switch (*s)
{
case '*': /* indirect 0--15 */
! if (! tic4x_print_indirect (info, INDIRECT_LONG,
EXTRU (instruction, 15, 0)))
return 0;
break;
case '#': /* only used for ldp, ldpk */
! tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
break;
case '@': /* direct 0--15 */
! tic4x_print_direct (info, EXTRU (instruction, 15, 0));
break;
case 'A': /* address register 24--22 */
! if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
REG_AR0))
return 0;
break;
case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
address 0--23. */
! if (IS_CPU_TIC4X (tic4x_version))
! tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
p->opcode);
else
! tic4x_print_addr (info, EXTRU (instruction, 23, 0));
break;
case 'C': /* indirect (short C4x) 0--7 */
! if (! IS_CPU_TIC4X (tic4x_version))
return 0;
! if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
EXTRU (instruction, 7, 0)))
return 0;
break;
*************** c4x_print_op (info, instruction, p, pc)
*** 483,508 ****
case 'E': /* register 0--7 */
case 'e':
! if (! c4x_print_register (info, EXTRU (instruction, 7, 0)))
return 0;
break;
case 'F': /* 16-bit float immediate 0--15 */
! c4x_print_immed (info, IMMED_SFLOAT,
EXTRU (instruction, 15, 0));
break;
case 'i': /* Extended indirect 0--7 */
if ( EXTRU (instruction, 7, 5) == 7 )
{
! if( !c4x_print_register (info, EXTRU (instruction, 4, 0)) )
return 0;
break;
}
/* Fallthrough */
case 'I': /* indirect (short) 0--7 */
! if (! c4x_print_indirect (info, INDIRECT_SHORT,
EXTRU (instruction, 7, 0)))
return 0;
break;
--- 484,509 ----
case 'E': /* register 0--7 */
case 'e':
! if (! tic4x_print_register (info, EXTRU (instruction, 7, 0)))
return 0;
break;
case 'F': /* 16-bit float immediate 0--15 */
! tic4x_print_immed (info, IMMED_SFLOAT,
EXTRU (instruction, 15, 0));
break;
case 'i': /* Extended indirect 0--7 */
if ( EXTRU (instruction, 7, 5) == 7 )
{
! if( !tic4x_print_register (info, EXTRU (instruction, 4, 0)) )
return 0;
break;
}
/* Fallthrough */
case 'I': /* indirect (short) 0--7 */
! if (! tic4x_print_indirect (info, INDIRECT_SHORT,
EXTRU (instruction, 7, 0)))
return 0;
break;
*************** c4x_print_op (info, instruction, p, pc)
*** 510,615 ****
case 'j': /* Extended indirect 8--15 */
if ( EXTRU (instruction, 15, 13) == 7 )
{
! if( !c4x_print_register (info, EXTRU (instruction, 12, 8)) )
return 0;
break;
}
case 'J': /* indirect (short) 8--15 */
! if (! c4x_print_indirect (info, INDIRECT_SHORT,
EXTRU (instruction, 15, 8)))
return 0;
break;
case 'G': /* register 8--15 */
case 'g':
! if (! c4x_print_register (info, EXTRU (instruction, 15, 8)))
return 0;
break;
case 'H': /* register 16--18 */
! if (! c4x_print_register (info, EXTRU (instruction, 18, 16)))
return 0;
break;
case 'K': /* register 19--21 */
! if (! c4x_print_register (info, EXTRU (instruction, 21, 19)))
return 0;
break;
case 'L': /* register 22--24 */
! if (! c4x_print_register (info, EXTRU (instruction, 24, 22)))
return 0;
break;
case 'M': /* register 22--22 */
! c4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
break;
case 'N': /* register 23--23 */
! c4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
break;
case 'O': /* indirect (short C4x) 8--15 */
! if (! IS_CPU_C4X (c4x_version))
return 0;
! if (! c4x_print_indirect (info, INDIRECT_C4X,
EXTRU (instruction, 15, 8)))
return 0;
break;
case 'P': /* displacement 0--15 (used by Bcond and BcondD) */
! c4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
p->opcode);
break;
case 'Q': /* register 0--15 */
case 'q':
! if (! c4x_print_register (info, EXTRU (instruction, 15, 0)))
return 0;
break;
case 'R': /* register 16--20 */
case 'r':
! if (! c4x_print_register (info, EXTRU (instruction, 20, 16)))
return 0;
break;
case 'S': /* 16-bit signed immediate 0--15 */
! c4x_print_immed (info, IMMED_SINT,
EXTRS (instruction, 15, 0));
break;
case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */
! if (! IS_CPU_C4X (c4x_version))
return 0;
! if (! c4x_print_immed (info, IMMED_SUINT,
EXTRU (instruction, 20, 16)))
return 0;
break;
case 'U': /* 16-bit unsigned int immediate 0--15 */
! c4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
break;
case 'V': /* 5/9-bit unsigned vector 0--4/8 */
! c4x_print_immed (info, IMMED_SUINT,
! IS_CPU_C4X (c4x_version) ?
EXTRU (instruction, 8, 0) :
EXTRU (instruction, 4, 0) & ~0x20);
break;
case 'W': /* 8-bit signed immediate 0--7 */
! if (! IS_CPU_C4X (c4x_version))
return 0;
! c4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
break;
case 'X': /* expansion register 4--0 */
val = EXTRU (instruction, 4, 0) + REG_IVTP;
if (val < REG_IVTP || val > REG_TVTP)
return 0;
! if (! c4x_print_register (info, val))
return 0;
break;
--- 511,616 ----
case 'j': /* Extended indirect 8--15 */
if ( EXTRU (instruction, 15, 13) == 7 )
{
! if( !tic4x_print_register (info, EXTRU (instruction, 12, 8)) )
return 0;
break;
}
case 'J': /* indirect (short) 8--15 */
! if (! tic4x_print_indirect (info, INDIRECT_SHORT,
EXTRU (instruction, 15, 8)))
return 0;
break;
case 'G': /* register 8--15 */
case 'g':
! if (! tic4x_print_register (info, EXTRU (instruction, 15, 8)))
return 0;
break;
case 'H': /* register 16--18 */
! if (! tic4x_print_register (info, EXTRU (instruction, 18, 16)))
return 0;
break;
case 'K': /* register 19--21 */
! if (! tic4x_print_register (info, EXTRU (instruction, 21, 19)))
return 0;
break;
case 'L': /* register 22--24 */
! if (! tic4x_print_register (info, EXTRU (instruction, 24, 22)))
return 0;
break;
case 'M': /* register 22--22 */
! tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
break;
case 'N': /* register 23--23 */
! tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
break;
case 'O': /* indirect (short C4x) 8--15 */
! if (! IS_CPU_TIC4X (tic4x_version))
return 0;
! if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
EXTRU (instruction, 15, 8)))
return 0;
break;
case 'P': /* displacement 0--15 (used by Bcond and BcondD) */
! tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
p->opcode);
break;
case 'Q': /* register 0--15 */
case 'q':
! if (! tic4x_print_register (info, EXTRU (instruction, 15, 0)))
return 0;
break;
case 'R': /* register 16--20 */
case 'r':
! if (! tic4x_print_register (info, EXTRU (instruction, 20, 16)))
return 0;
break;
case 'S': /* 16-bit signed immediate 0--15 */
! tic4x_print_immed (info, IMMED_SINT,
EXTRS (instruction, 15, 0));
break;
case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */
! if (! IS_CPU_TIC4X (tic4x_version))
return 0;
! if (! tic4x_print_immed (info, IMMED_SUINT,
EXTRU (instruction, 20, 16)))
return 0;
break;
case 'U': /* 16-bit unsigned int immediate 0--15 */
! tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
break;
case 'V': /* 5/9-bit unsigned vector 0--4/8 */
! tic4x_print_immed (info, IMMED_SUINT,
! IS_CPU_TIC4X (tic4x_version) ?
EXTRU (instruction, 8, 0) :
EXTRU (instruction, 4, 0) & ~0x20);
break;
case 'W': /* 8-bit signed immediate 0--7 */
! if (! IS_CPU_TIC4X (tic4x_version))
return 0;
! tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
break;
case 'X': /* expansion register 4--0 */
val = EXTRU (instruction, 4, 0) + REG_IVTP;
if (val < REG_IVTP || val > REG_TVTP)
return 0;
! if (! tic4x_print_register (info, val))
return 0;
break;
*************** c4x_print_op (info, instruction, p, pc)
*** 617,623 ****
val = EXTRU (instruction, 20, 16);
if (val < REG_AR0 || val > REG_SP)
return 0;
! if (! c4x_print_register (info, val))
return 0;
break;
--- 618,624 ----
val = EXTRU (instruction, 20, 16);
if (val < REG_AR0 || val > REG_SP)
return 0;
! if (! tic4x_print_register (info, val))
return 0;
break;
*************** c4x_print_op (info, instruction, p, pc)
*** 625,646 ****
val = EXTRU (instruction, 20, 16) + REG_IVTP;
if (val < REG_IVTP || val > REG_TVTP)
return 0;
! if (! c4x_print_register (info, val))
return 0;
break;
case '|': /* Parallel instruction */
! c4x_print_str (info, " || ");
! c4x_print_str (info, parallel);
! c4x_print_char (info, ' ');
break;
case ';':
! c4x_print_char (info, ',');
break;
default:
! c4x_print_char (info, *s);
break;
}
s++;
--- 626,647 ----
val = EXTRU (instruction, 20, 16) + REG_IVTP;
if (val < REG_IVTP || val > REG_TVTP)
return 0;
! if (! tic4x_print_register (info, val))
return 0;
break;
case '|': /* Parallel instruction */
! tic4x_print_str (info, " || ");
! tic4x_print_str (info, parallel);
! tic4x_print_char (info, ' ');
break;
case ';':
! tic4x_print_char (info, ',');
break;
default:
! tic4x_print_char (info, *s);
break;
}
s++;
*************** c4x_print_op (info, instruction, p, pc)
*** 649,661 ****
}
static void
! c4x_hash_opcode_special (optable_special, inst)
! c4x_inst_t **optable_special;
! const c4x_inst_t *inst;
{
int i;
! for( i=0; i<C4X_SPESOP_SIZE; i++ )
if( optable_special[i] != NULL
&& optable_special[i]->opcode == inst->opcode )
{
--- 650,662 ----
}
static void
! tic4x_hash_opcode_special (optable_special, inst)
! tic4x_inst_t **optable_special;
! const tic4x_inst_t *inst;
{
int i;
! for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
if( optable_special[i] != NULL
&& optable_special[i]->opcode == inst->opcode )
{
*************** c4x_hash_opcode_special (optable_special
*** 664,670 ****
return;
}
! for( i=0; i<C4X_SPESOP_SIZE; i++ )
if( optable_special[i] == NULL )
{
/* Add the new opcode */
--- 665,671 ----
return;
}
! for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
if( optable_special[i] == NULL )
{
/* Add the new opcode */
*************** c4x_hash_opcode_special (optable_special
*** 673,704 ****
}
/* This should never occur. This happens if the number of special
! instructions exceeds C4X_SPESOP_SIZE. Please increase the variable
of this variable */
! #if C4X_DEBUG
! printf("optable_special[] is full, please increase C4X_SPESOP_SIZE!\n");
#endif
}
static void
! c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel)
! c4x_inst_t **optable;
! c4x_inst_t **optable_special;
! const c4x_inst_t *inst;
! const unsigned long c4x_oplevel;
{
int j;
! int opcode = inst->opcode >> (32 - C4X_HASH_SIZE);
! int opmask = inst->opmask >> (32 - C4X_HASH_SIZE);
! /* Use a C4X_HASH_SIZE bit index as a hash index. We should
have unique entries so there's no point having a linked list
for each entry? */
for (j = opcode; j < opmask; j++)
if ( (j & opmask) == opcode
! && inst->oplevel & c4x_oplevel )
{
! #if C4X_DEBUG
/* We should only have collisions for synonyms like
ldp for ldi. */
if (optable[j] != NULL)
--- 674,705 ----
}
/* This should never occur. This happens if the number of special
! instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
of this variable */
! #if TIC4X_DEBUG
! printf("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
#endif
}
static void
! tic4x_hash_opcode (optable, optable_special, inst, tic4x_oplevel)
! tic4x_inst_t **optable;
! tic4x_inst_t **optable_special;
! const tic4x_inst_t *inst;
! const unsigned long tic4x_oplevel;
{
int j;
! int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE);
! int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE);
! /* Use a TIC4X_HASH_SIZE bit index as a hash index. We should
have unique entries so there's no point having a linked list
for each entry? */
for (j = opcode; j < opmask; j++)
if ( (j & opmask) == opcode
! && inst->oplevel & tic4x_oplevel )
{
! #if TIC4X_DEBUG
/* We should only have collisions for synonyms like
ldp for ldi. */
if (optable[j] != NULL)
*************** c4x_hash_opcode (optable, optable_specia
*** 710,722 ****
hash. Store them in a special-list, that will handle full
32-bit INSN, not only the first 11-bit (or so). */
if ( optable[j] != NULL
! && inst->opmask & ~(opmask << (32 - C4X_HASH_SIZE)) )
{
/* Add the instruction already on the list */
! c4x_hash_opcode_special(optable_special, optable[j]);
/* Add the new instruction */
! c4x_hash_opcode_special(optable_special, inst);
}
optable[j] = (void *)inst;
--- 711,723 ----
hash. Store them in a special-list, that will handle full
32-bit INSN, not only the first 11-bit (or so). */
if ( optable[j] != NULL
! && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)) )
{
/* Add the instruction already on the list */
! tic4x_hash_opcode_special(optable_special, optable[j]);
/* Add the new instruction */
! tic4x_hash_opcode_special(optable_special, inst);
}
optable[j] = (void *)inst;
*************** c4x_hash_opcode (optable, optable_specia
*** 730,796 ****
The function returns the length of this instruction in words. */
static int
! c4x_disassemble (pc, instruction, info)
unsigned long pc;
unsigned long instruction;
struct disassemble_info *info;
{
! static c4x_inst_t **optable = NULL;
! static c4x_inst_t **optable_special = NULL;
! c4x_inst_t *p;
int i;
! unsigned long c4x_oplevel;
! c4x_version = info->mach;
! c4x_oplevel = (IS_CPU_C4X (c4x_version)) ? OP_C4X : 0;
! c4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH;
if (optable == NULL)
{
! optable = (c4x_inst_t **)
! xcalloc (sizeof (c4x_inst_t *), (1 << C4X_HASH_SIZE));
! optable_special = (c4x_inst_t **)
! xcalloc (sizeof (c4x_inst_t *), C4X_SPESOP_SIZE );
/* Install opcodes in reverse order so that preferred
forms overwrite synonyms. */
! for (i = c4x_num_insts - 1; i >= 0; i--)
! c4x_hash_opcode (optable, optable_special, &c4x_insts[i], c4x_oplevel);
/* We now need to remove the insn that are special from the
"normal" optable, to make the disasm search this extra list
for them.
*/
! for (i=0; i<C4X_SPESOP_SIZE; i++)
if ( optable_special[i] != NULL )
! optable[optable_special[i]->opcode >> (32 - C4X_HASH_SIZE)] = NULL;
}
/* See if we can pick up any loading of the DP register... */
if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
! c4x_dp = EXTRU (instruction, 15, 0);
! p = optable[instruction >> (32 - C4X_HASH_SIZE)];
if ( p != NULL )
{
if ( ((instruction & p->opmask) == p->opcode)
! && c4x_print_op (NULL, instruction, p, pc) )
! c4x_print_op (info, instruction, p, pc);
else
(*info->fprintf_func) (info->stream, "%08x", instruction);
}
else
{
! for (i = 0; i<C4X_SPESOP_SIZE; i++)
if (optable_special[i] != NULL
&& optable_special[i]->opcode == instruction )
{
(*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
break;
}
! if (i==C4X_SPESOP_SIZE)
(*info->fprintf_func) (info->stream, "%08x", instruction);
}
--- 731,797 ----
The function returns the length of this instruction in words. */
static int
! tic4x_disassemble (pc, instruction, info)
unsigned long pc;
unsigned long instruction;
struct disassemble_info *info;
{
! static tic4x_inst_t **optable = NULL;
! static tic4x_inst_t **optable_special = NULL;
! tic4x_inst_t *p;
int i;
! unsigned long tic4x_oplevel;
! tic4x_version = info->mach;
! tic4x_oplevel = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0;
! tic4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH;
if (optable == NULL)
{
! optable = (tic4x_inst_t **)
! xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE));
! optable_special = (tic4x_inst_t **)
! xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE );
/* Install opcodes in reverse order so that preferred
forms overwrite synonyms. */
! for (i = tic4x_num_insts - 1; i >= 0; i--)
! tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i], tic4x_oplevel);
/* We now need to remove the insn that are special from the
"normal" optable, to make the disasm search this extra list
for them.
*/
! for (i=0; i<TIC4X_SPESOP_SIZE; i++)
if ( optable_special[i] != NULL )
! optable[optable_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL;
}
/* See if we can pick up any loading of the DP register... */
if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
! tic4x_dp = EXTRU (instruction, 15, 0);
! p = optable[instruction >> (32 - TIC4X_HASH_SIZE)];
if ( p != NULL )
{
if ( ((instruction & p->opmask) == p->opcode)
! && tic4x_print_op (NULL, instruction, p, pc) )
! tic4x_print_op (info, instruction, p, pc);
else
(*info->fprintf_func) (info->stream, "%08x", instruction);
}
else
{
! for (i = 0; i<TIC4X_SPESOP_SIZE; i++)
if (optable_special[i] != NULL
&& optable_special[i]->opcode == instruction )
{
(*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
break;
}
! if (i==TIC4X_SPESOP_SIZE)
(*info->fprintf_func) (info->stream, "%08x", instruction);
}
*************** print_insn_tic4x (memaddr, info)
*** 822,826 ****
info->bytes_per_chunk = 4;
info->octets_per_byte = 4;
info->display_endian = BFD_ENDIAN_LITTLE;
! return c4x_disassemble (pc, op, info) * 4;
}
--- 823,827 ----
info->bytes_per_chunk = 4;
info->octets_per_byte = 4;
info->display_endian = BFD_ENDIAN_LITTLE;
! return tic4x_disassemble (pc, op, info) * 4;
}