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Patch to properly assemble/disassemble ColdFire MAC/EMAC instructions
- From: Peter Barada <peter at the-baradas dot com>
- To: binutils at sources dot redhat dot com
- Cc: peter at the-baradas dot com
- Date: Tue, 20 Apr 2004 11:52:06 -0400 (EDT)
- Subject: Patch to properly assemble/disassemble ColdFire MAC/EMAC instructions
Teun Grinwis pointed out to me that the assembler currently has
support for the MAC, but not support for the EMAC, so I added the
instructions and operands.
I also ripped out the gross hack of the macmw/macml/msacmw/msacml
insns and added '&' parsing so it understands mask addressing for the
mac instructions. While I was chaning the parser, I added the
proper scale factors tokens for the mac instructions, namely '<<' and
'>>'. I left in the previous support of using '+1", '-1' to specify
the scale factor.
Now the assembler properly handles:
mac.w %a1l,%a2u,<<,(%a3)&,%d1,%acc1
2004-04-20 Peter Barada <peter@the-baradas.com>
* Add support for ColdFire EMAC instrucitons.
* Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
handle Motorola MAC syntax.
* Allow disassembly of ColdFire V4e object files.
Index: bfd/archures.c
===================================================================
RCS file: /cvs/uberbaum/bfd/archures.c,v
retrieving revision 1.91
diff -c -3 -p -r1.91 archures.c
*** bfd/archures.c 30 Mar 2004 14:04:26 -0000 1.91
--- bfd/archures.c 20 Apr 2004 15:33:23 -0000
*************** DESCRIPTION
*** 85,90 ****
--- 85,91 ----
.#define bfd_mach_mcf5307 11
.#define bfd_mach_mcf5407 12
.#define bfd_mach_mcf528x 13
+ .#define bfd_mach_mcfv4e 14
. bfd_arch_vax, {* DEC Vax *}
. bfd_arch_i960, {* Intel 960 *}
. {* The order of the following is important.
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/uberbaum/bfd/bfd-in2.h,v
retrieving revision 1.266
diff -c -3 -p -r1.266 bfd-in2.h
*** bfd/bfd-in2.h 1 Apr 2004 11:20:01 -0000 1.266
--- bfd/bfd-in2.h 20 Apr 2004 15:33:24 -0000
*************** enum bfd_architecture
*** 1483,1488 ****
--- 1483,1489 ----
#define bfd_mach_mcf5307 11
#define bfd_mach_mcf5407 12
#define bfd_mach_mcf528x 13
+ #define bfd_mach_mcfv4e 14
bfd_arch_vax, /* DEC Vax */
bfd_arch_i960, /* Intel 960 */
/* The order of the following is important.
Index: bfd/cpu-m68k.c
===================================================================
RCS file: /cvs/uberbaum/bfd/cpu-m68k.c,v
retrieving revision 1.6
diff -c -3 -p -r1.6 cpu-m68k.c
*** bfd/cpu-m68k.c 21 Oct 2003 13:28:58 -0000 1.6
--- bfd/cpu-m68k.c 20 Apr 2004 15:33:24 -0000
***************
*** 1,6 ****
/* BFD library support routines for architectures.
Copyright 1990, 1991, 1992, 1993, 1994, 1997, 1998, 2000, 2001, 2002,
! 2003 Free Software Foundation, Inc.
Hacked by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
--- 1,6 ----
/* BFD library support routines for architectures.
Copyright 1990, 1991, 1992, 1993, 1994, 1997, 1998, 2000, 2001, 2002,
! 2003, 2004 Free Software Foundation, Inc.
Hacked by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
*************** static const bfd_arch_info_type arch_inf
*** 40,46 ****
N(bfd_mach_mcf5307, "m68k:5307", FALSE, &arch_info_struct[10]),
N(bfd_mach_mcf5407, "m68k:5407", FALSE, &arch_info_struct[11]),
N(bfd_mach_m68060, "m68k:68060", FALSE, &arch_info_struct[12]),
! N(bfd_mach_mcf528x, "m68k:528x", FALSE, 0),
};
const bfd_arch_info_type bfd_m68k_arch =
--- 40,47 ----
N(bfd_mach_mcf5307, "m68k:5307", FALSE, &arch_info_struct[10]),
N(bfd_mach_mcf5407, "m68k:5407", FALSE, &arch_info_struct[11]),
N(bfd_mach_m68060, "m68k:68060", FALSE, &arch_info_struct[12]),
! N(bfd_mach_mcf528x, "m68k:528x", FALSE, &arch_info_struct[13]),
! N(bfd_mach_mcfv4e, "m68k:cfv4e", FALSE, 0),
};
const bfd_arch_info_type bfd_m68k_arch =
Index: gas/config/m68k-parse.h
===================================================================
RCS file: /cvs/uberbaum/gas/config/m68k-parse.h,v
retrieving revision 1.5
diff -c -3 -p -r1.5 m68k-parse.h
*** gas/config/m68k-parse.h 21 Oct 2003 13:28:59 -0000 1.5
--- gas/config/m68k-parse.h 20 Apr 2004 15:33:24 -0000
***************
*** 1,6 ****
/* m68k-parse.h -- header file for m68k assembler
Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
! 2003 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
--- 1,6 ----
/* m68k-parse.h -- header file for m68k assembler
Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
! 2003, 2004 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
*************** enum m68k_register
*** 84,90 ****
ZPC, /* Hack for Program space, but 0 addressing */
SR, /* Status Reg */
CCR, /* Condition code Reg */
! ACC, /* Accumulator Reg */
MACSR, /* MAC Status Reg */
MASK, /* Modulus Reg */
--- 84,95 ----
ZPC, /* Hack for Program space, but 0 addressing */
SR, /* Status Reg */
CCR, /* Condition code Reg */
! ACC, /* Accumulator Reg0 (EMAC or ACC on MAC) */
! ACC1, /* Accumulator Reg 1 (EMAC) */
! ACC2, /* Accumulator Reg 2 (EMAC) */
! ACC3, /* Accumulator Reg 3 (EMAC) */
! ACCEXT01, /* Accumulator extension 0&1 (EMAC) */
! ACCEXT23, /* Accumulator extension 2&3 (EMAC) */
MACSR, /* MAC Status Reg */
MASK, /* Modulus Reg */
*************** enum m68k_operand_type
*** 295,300 ****
--- 300,307 ----
BASE,
POST,
PRE,
+ LSH, /* MAC/EMAC scalefactor '<<' */
+ RSH, /* MAC/EMAC scalefactor '>>' */
REGLST
};
*************** struct m68k_op
*** 322,327 ****
--- 329,337 ----
/* The outer displacement. */
struct m68k_exp odisp;
+
+ /* was a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing) */
+ int trailing_ampersand;
};
#endif /* ! defined (M68K_PARSE_H) */
Index: gas/config/m68k-parse.y
===================================================================
RCS file: /cvs/uberbaum/gas/config/m68k-parse.y,v
retrieving revision 1.4
diff -c -3 -p -r1.4 m68k-parse.y
*** gas/config/m68k-parse.y 22 Nov 2003 15:32:28 -0000 1.4
--- gas/config/m68k-parse.y 20 Apr 2004 15:33:24 -0000
*************** static struct m68k_op *op;
*** 98,103 ****
--- 98,104 ----
struct m68k_exp exp;
unsigned long mask;
int onereg;
+ int trailing_ampersand;
}
%token <reg> DR AR FPR FPCR LPC ZAR ZDR LZPC CREG
*************** static struct m68k_op *op;
*** 109,114 ****
--- 110,116 ----
%type <exp> optcexpr optexprc
%type <mask> reglist ireglist reglistpair
%type <onereg> reglistreg
+ %type <trailing_ampersand> optional_ampersand
%%
*************** static struct m68k_op *op;
*** 116,129 ****
operand:
generic_operand
! | motorola_operand
| mit_operand
;
/* A generic operand. */
generic_operand:
! DR
{
op->mode = DREG;
op->reg = $1;
--- 118,151 ----
operand:
generic_operand
! | motorola_operand optional_ampersand
! {
! op->trailing_ampersand = $2;
! }
| mit_operand
;
+ optional_ampersand:
+ /* empty */
+ { $$ = 0; }
+ | '&'
+ { $$ = 1; }
+ ;
+
/* A generic operand. */
generic_operand:
! '<' '<'
! {
! op->mode = LSH;
! }
!
! | '>' '>'
! {
! op->mode = RSH;
! }
!
! | DR
{
op->mode = DREG;
op->reg = $1;
*************** yylex ()
*** 757,768 ****
case '/':
case '[':
case ']':
return *str++;
case '+':
/* It so happens that a '+' can only appear at the end of an
! operand. If it appears anywhere else, it must be a unary
! plus on an expression. */
! if (str[1] == '\0')
return *str++;
break;
case '-':
--- 779,792 ----
case '/':
case '[':
case ']':
+ case '<':
+ case '>':
return *str++;
case '+':
/* It so happens that a '+' can only appear at the end of an
! operand, or if it is trailed by an '&'(see mac load insn).
! If it appears anywhere else, it must be a unary. */
! if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0')
return *str++;
break;
case '-':
Index: gas/config/tc-m68k.c
===================================================================
RCS file: /cvs/uberbaum/gas/config/tc-m68k.c,v
retrieving revision 1.49
diff -c -3 -p -r1.49 tc-m68k.c
*** gas/config/tc-m68k.c 26 Jan 2004 18:09:30 -0000 1.49
--- gas/config/tc-m68k.c 20 Apr 2004 15:33:26 -0000
*************** struct m68k_cpu
*** 371,422 ****
static const struct m68k_cpu archs[] =
{
! { m68000, "68000", 0 },
! { m68010, "68010", 0 },
! { m68020, "68020", 0 },
! { m68030, "68030", 0 },
! { m68040, "68040", 0 },
! { m68060, "68060", 0 },
! { cpu32, "cpu32", 0 },
! { m68881, "68881", 0 },
! { m68851, "68851", 0 },
! { mcf5200, "5200", 0 },
! { mcf5206e,"5206e", 0 },
! { mcf528x, "528x", 0 },
! { mcf5307, "5307", 0 },
! { mcf5407, "5407", 0 },
! { mcfv4e, "cfv4e", 0 },
/* Aliases (effectively, so far as gas is concerned) for the above
cpus. */
! { m68020, "68k", 1 },
! { m68000, "68008", 1 },
! { m68000, "68302", 1 },
! { m68000, "68306", 1 },
! { m68000, "68307", 1 },
! { m68000, "68322", 1 },
! { m68000, "68356", 1 },
! { m68000, "68ec000", 1 },
! { m68000, "68hc000", 1 },
! { m68000, "68hc001", 1 },
! { m68020, "68ec020", 1 },
! { m68030, "68ec030", 1 },
! { m68040, "68ec040", 1 },
! { m68060, "68ec060", 1 },
! { cpu32, "68330", 1 },
! { cpu32, "68331", 1 },
! { cpu32, "68332", 1 },
! { cpu32, "68333", 1 },
! { cpu32, "68334", 1 },
! { cpu32, "68336", 1 },
! { cpu32, "68340", 1 },
! { cpu32, "68341", 1 },
! { cpu32, "68349", 1 },
! { cpu32, "68360", 1 },
! { m68881, "68882", 1 },
! { mcf5200, "5202", 1 },
! { mcf5200, "5204", 1 },
! { mcf5200, "5206", 1 },
! { mcf5407, "cfv4", 1 },
};
static const int n_archs = sizeof (archs) / sizeof (archs[0]);
--- 371,422 ----
static const struct m68k_cpu archs[] =
{
! { m68000, "68000", 0 },
! { m68010, "68010", 0 },
! { m68020, "68020", 0 },
! { m68030, "68030", 0 },
! { m68040, "68040", 0 },
! { m68060, "68060", 0 },
! { cpu32, "cpu32", 0 },
! { m68881, "68881", 0 },
! { m68851, "68851", 0 },
! { mcf5200, "5200", 0 },
! { mcf5206e, "5206e", 0 },
! { mcf528x|mcfmac, "528x", 0 },
! { mcf5307|mcfmac, "5307", 0 },
! { mcf5407|mcfmac, "5407", 0 },
! { mcfv4e|mcfemac, "cfv4e", 0 },
/* Aliases (effectively, so far as gas is concerned) for the above
cpus. */
! { m68020, "68k", 1 },
! { m68000, "68008", 1 },
! { m68000, "68302", 1 },
! { m68000, "68306", 1 },
! { m68000, "68307", 1 },
! { m68000, "68322", 1 },
! { m68000, "68356", 1 },
! { m68000, "68ec000", 1 },
! { m68000, "68hc000", 1 },
! { m68000, "68hc001", 1 },
! { m68020, "68ec020", 1 },
! { m68030, "68ec030", 1 },
! { m68040, "68ec040", 1 },
! { m68060, "68ec060", 1 },
! { cpu32, "68330", 1 },
! { cpu32, "68331", 1 },
! { cpu32, "68332", 1 },
! { cpu32, "68333", 1 },
! { cpu32, "68334", 1 },
! { cpu32, "68336", 1 },
! { cpu32, "68340", 1 },
! { cpu32, "68341", 1 },
! { cpu32, "68349", 1 },
! { cpu32, "68360", 1 },
! { m68881, "68882", 1 },
! { mcf5200, "5202", 1 },
! { mcf5200, "5204", 1 },
! { mcf5200, "5206", 1 },
! { mcf5407|mcfmac, "cfv4", 1 },
};
static const int n_archs = sizeof (archs) / sizeof (archs[0]);
*************** m68k_ip (instring)
*** 1505,1510 ****
--- 1505,1518 ----
++losing;
break;
+ case '4':
+ if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
+ && (opP->mode != DISP
+ || opP->reg < ADDR0
+ || opP->reg > ADDR7))
+ ++losing;
+ break;
+
case 'B': /* FOO */
if (opP->mode != ABSL
|| (flag_long_jumps
*************** m68k_ip (instring)
*** 1552,1557 ****
--- 1560,1571 ----
losing++;
break;
+ case 'e':
+ if (opP->reg != ACC && opP->reg != ACC1
+ && opP->reg != ACC2 && opP->reg != ACC3)
+ losing++;
+ break;
+
case 'F':
if (opP->mode != FPREG)
losing++;
*************** m68k_ip (instring)
*** 1562,1567 ****
--- 1576,1586 ----
losing++;
break;
+ case 'g':
+ if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
+ losing++;
+ break;
+
case 'H':
if (opP->reg != MASK)
losing++;
*************** m68k_ip (instring)
*** 1574,1579 ****
--- 1593,1603 ----
losing++;
break;
+ case 'i':
+ if (opP->mode != LSH && opP->mode != RSH)
+ losing++;
+ break;
+
case 'J':
if (opP->mode != CONTROL
|| opP->reg < USP
*************** m68k_ip (instring)
*** 1994,1999 ****
--- 2018,2024 ----
case 'w':
case 'y':
case 'z':
+ case '4':
#ifndef NO_68851
case '|':
#endif
*************** m68k_ip (instring)
*** 2519,2524 ****
--- 2544,2559 ----
as_bad (_("unknown/incorrect operand"));
/* abort (); */
}
+
+ /* If s[0] is '4', then this is for the mac instructions
+ that can have a trailing_ampersand set. If so, set 0x100
+ bit on tmpreg so install_gen_operand can check for it and
+ set the appropriate bit (word2, bit 5). */
+ if (s[0] == '4')
+ {
+ if (opP->trailing_ampersand)
+ tmpreg |= 0x100;
+ }
install_gen_operand (s[1], tmpreg);
break;
*************** m68k_ip (instring)
*** 2737,2742 ****
--- 2772,2781 ----
install_operand (s[1], opP->reg - DATA);
break;
+ case 'e': /*EMAC ACC, reg/reg */
+ install_operand (s[1], opP->reg - ACC);
+ break;
+
case 'E': /* Ignore it. */
break;
*************** m68k_ip (instring)
*** 2744,2749 ****
--- 2783,2792 ----
install_operand (s[1], opP->reg - FP0);
break;
+ case 'g': /*EMAC ACCEXTx */
+ install_operand (s[1], opP->reg - ACCEXT01);
+ break;
+
case 'G': /* Ignore it. */
case 'H':
break;
*************** m68k_ip (instring)
*** 2753,2758 ****
--- 2796,2805 ----
install_operand (s[1], tmpreg);
break;
+ case 'i': /* MAC/EMAC scale factor */
+ install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
+ break;
+
case 'J': /* JF foo. */
switch (opP->reg)
{
*************** install_operand (mode, val)
*** 3286,3310 ****
the_ins.opcode[0] |= ((val & 0x7) << 9);
the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
break;
! case 'n':
the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
the_ins.opcode[0] |= ((val & 0x7) << 9);
break;
! case 'o':
the_ins.opcode[1] |= val << 12;
the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
break;
! case 'M':
the_ins.opcode[0] |= (val & 0xF);
the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
break;
! case 'N':
the_ins.opcode[1] |= (val & 0xF);
the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
break;
case 'h':
the_ins.opcode[1] |= ((val != 1) << 10);
break;
case 'c':
default:
as_fatal (_("failed sanity check."));
--- 3333,3378 ----
the_ins.opcode[0] |= ((val & 0x7) << 9);
the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
break;
! case 'n': /* mac Rx on !load */
the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
the_ins.opcode[0] |= ((val & 0x7) << 9);
+ the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
break;
! case 'o': /* mac Rx on load */
the_ins.opcode[1] |= val << 12;
the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
break;
! case 'M': /* mac Ry on !load */
the_ins.opcode[0] |= (val & 0xF);
the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
break;
! case 'N': /* mac Ry on load */
the_ins.opcode[1] |= (val & 0xF);
the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
break;
case 'h':
the_ins.opcode[1] |= ((val != 1) << 10);
break;
+ case 'F':
+ the_ins.opcode[0] |= ((val & 0x3) << 9);
+ break;
+ case 'f':
+ the_ins.opcode[0] |= ((val & 0x3) << 0);
+ break;
+ case 'G':
+ the_ins.opcode[0] |= ((~val & 0x1) << 7);
+ the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+ break;
+ case 'H':
+ the_ins.opcode[0] |= ((val & 0x1) << 7);
+ the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+ break;
+ case 'I':
+ the_ins.opcode[1] |= ((val & 0x3) << 9);
+ break;
+ case ']':
+ the_ins.opcode[0] |= (val & 0x1) <<10;
+ break;
case 'c':
default:
as_fatal (_("failed sanity check."));
*************** install_gen_operand (mode, val)
*** 3318,3323 ****
--- 3386,3396 ----
{
switch (mode)
{
+ case '/': /* special for mask loads for mac/msac insns with
+ possible mask; trailing_ampersend set in bit 8 */
+ the_ins.opcode[0] |= (val & 0x3f);
+ the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
+ break;
case 's':
the_ins.opcode[0] |= val;
break;
*************** static const struct init_entry init_tabl
*** 3507,3512 ****
--- 3580,3591 ----
{ "cc", CCR },
{ "acc", ACC },
+ { "acc0", ACC },
+ { "acc1", ACC1 },
+ { "acc2", ACC2 },
+ { "acc3", ACC3 },
+ { "accext01", ACCEXT01 },
+ { "accext23", ACCEXT23 },
{ "macsr", MACSR },
{ "mask", MASK },
Index: include/opcode/m68k.h
===================================================================
RCS file: /cvs/uberbaum/include/opcode/m68k.h,v
retrieving revision 1.5
diff -c -3 -p -r1.5 m68k.h
*** include/opcode/m68k.h 21 Oct 2003 13:28:59 -0000 1.5
--- include/opcode/m68k.h 20 Apr 2004 15:33:31 -0000
***************
*** 42,47 ****
--- 42,49 ----
#define mcf5407 0x1000
#define mcfv4e 0x2000
#define mcf528x 0x4000
+ #define mcfmac 0x8000
+ #define mcfemac 0x10000
/* Handy aliases. */
#define m68040up (m68040 | m68060)
*************** struct m68k_opcode_alias
*** 99,105 ****
operand; the second, the place it is stored. */
/* Kinds of operands:
! Characters used: AaBbCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWwXxYyZz0123|*~%;@!&$?/<>#^+-
D data register only. Stored as 3 bits.
A address register only. Stored as 3 bits.
--- 101,107 ----
operand; the second, the place it is stored. */
/* Kinds of operands:
! Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
D data register only. Stored as 3 bits.
A address register only. Stored as 3 bits.
*************** struct m68k_opcode_alias
*** 134,141 ****
--- 136,146 ----
S the SR. No need to store, just as with CCR.
U the USP. No need to store, just as with CCR.
E the ACC. No need to store, just as with CCR.
+ e the ACC[0123]
G the MACSR. No need to store, just as with CCR.
+ g the ACCEXT{01,23}.
H the MASK. No need to store, just as with CCR.
+ i MAC/EMAC scale factor
I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
extracted from the 'd' field of word one, which means that an extended
*************** struct m68k_opcode_alias
*** 230,236 ****
w (modes 2-5,7.2)
y (modes 2,5)
z (modes 2,5,7.2)
! x mov3q immediate operand. */
/* For the 68851: */
/* I didn't use much imagination in choosing the
--- 235,243 ----
w (modes 2-5,7.2)
y (modes 2,5)
z (modes 2,5,7.2)
! x mov3q immediate operand.
! 4 (modes 2,3,4,5)
! */
/* For the 68851: */
/* I didn't use much imagination in choosing the
*************** struct m68k_opcode_alias
*** 283,289 ****
*/
/* Places to put an operand, for non-general operands:
! Characters used: BbCcDdghijkLlMmNnostWw123456789
s source, low bits of first word.
d dest, shifted 9 in first word
--- 290,296 ----
*/
/* Places to put an operand, for non-general operands:
! Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
s source, low bits of first word.
d dest, shifted 9 in first word
*************** struct m68k_opcode_alias
*** 348,353 ****
--- 355,367 ----
F double precision float, low bit of 1st word, immediate uses 8 bytes
x extended precision float, low bit of 1st word, immediate uses 12 bytes
p packed float, low bit of 1st word, immediate uses 12 bytes
+ G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
+ H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
+ F EMAC ACCx
+ f EMAC ACCy
+ I MAC/EMAC scale factor
+ / Like 's', but set 2nd word, bit 5 if trailing_ampersand set
+ ] first word, bit 10
*/
extern const struct m68k_opcode m68k_opcodes[];
Index: opcodes/m68k-dis.c
===================================================================
RCS file: /cvs/uberbaum/opcodes/m68k-dis.c,v
retrieving revision 1.11
diff -c -3 -p -r1.11 m68k-dis.c
*** opcodes/m68k-dis.c 21 Oct 2003 13:28:59 -0000 1.11
--- opcodes/m68k-dis.c 20 Apr 2004 15:33:34 -0000
***************
*** 1,6 ****
/* Print Motorola 68k instructions.
Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
! 1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify
--- 1,6 ----
/* Print Motorola 68k instructions.
Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
! 1998, 1999, 2000, 2001, 2002, 2003, 2004
Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify
*************** print_insn_m68k (memaddr, info)
*** 264,279 ****
arch_mask = mcf5200;
break;
case bfd_mach_mcf528x:
! arch_mask = mcf528x;
break;
case bfd_mach_mcf5206e:
! arch_mask = mcf5206e;
break;
case bfd_mach_mcf5307:
! arch_mask = mcf5307;
break;
case bfd_mach_mcf5407:
! arch_mask = mcf5407;
break;
}
--- 264,282 ----
arch_mask = mcf5200;
break;
case bfd_mach_mcf528x:
! arch_mask = mcf528x | mcfmac;
break;
case bfd_mach_mcf5206e:
! arch_mask = mcf5206e | mcfmac;
break;
case bfd_mach_mcf5307:
! arch_mask = mcf5307 | mcfmac;
break;
case bfd_mach_mcf5407:
! arch_mask = mcf5407 | mcfmac;
! break;
! case bfd_mach_mcfv4e:
! arch_mask = mcfv4e | mcfemac;
break;
}
*************** print_insn_arg (d, buffer, p0, addr, inf
*** 736,741 ****
--- 739,762 ----
fpcr_names[fetch_arg (buffer, place, 3, info)]);
break;
+ case 'e':
+ val = fetch_arg(buffer, place, 2, info);
+ (*info->fprintf_func) (info->stream, "%%acc%d", val);
+ break;
+
+ case 'g':
+ val = fetch_arg(buffer, place, 2, info);
+ (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
+ break;
+
+ case 'i':
+ val = fetch_arg(buffer, place, 2, info);
+ if (val == 1)
+ (*info->fprintf_func) (info->stream, "<<");
+ else if (val == 3)
+ (*info->fprintf_func) (info->stream, ">>");
+ break;
+
case 'I':
/* Get coprocessor ID... */
val = fetch_arg (buffer, 'd', 3, info);
*************** print_insn_arg (d, buffer, p0, addr, inf
*** 744,749 ****
--- 765,771 ----
(*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
break;
+ case '4':
case '*':
case '~':
case '%':
*************** print_insn_arg (d, buffer, p0, addr, inf
*** 881,886 ****
--- 903,918 ----
return -1;
}
}
+
+ /* If place is '/', then this is the case of the mask bit for
+ mac/emac loads. Now that the arg has been printed, grab the
+ mask bit and if set, add a '&' to the arg. */
+ if (place == '/')
+ {
+ val = fetch_arg (buffer, place, 1, info);
+ if (val)
+ (*info->fprintf_func) (info->stream, "&");
+ }
break;
case 'L':
*************** fetch_arg (buffer, code, bits, info)
*** 1075,1080 ****
--- 1107,1140 ----
register int val = 0;
switch (code)
{
+ case '/': /* mac/emac mask bit */
+ val = buffer[3] >> 5;
+ break;
+
+ case 'G': /* emac ACC load */
+ val = ((buffer[3] >> 3) & 0x2) | ((~buffer[2] >> 7) & 0x1);
+ break;
+
+ case 'H': /* emac ACC !load */
+ val = ((buffer[3] >> 3) & 0x2) | ((buffer[2] >> 7) & 0x1);
+ break;
+
+ case ']': /* accext bit */
+ val = buffer[0] >> 2;
+ break;
+
+ case 'I': /* mac/emac scale factor */
+ val = buffer[0] >> 1;
+ break;
+
+ case 'F': /* emac ACCx */
+ val = buffer[0] >> 1;
+ break;
+
+ case 'f':
+ val = buffer[0];
+ break;
+
case 's':
val = buffer[1];
break;
Index: opcodes/m68k-opc.c
===================================================================
RCS file: /cvs/uberbaum/opcodes/m68k-opc.c,v
retrieving revision 1.10
diff -c -3 -p -r1.10 m68k-opc.c
*** opcodes/m68k-opc.c 6 Nov 2003 04:32:07 -0000 1.10
--- opcodes/m68k-opc.c 20 Apr 2004 15:33:34 -0000
***************
*** 1,6 ****
/* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
! 2000, 2001, 2003
Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
--- 1,6 ----
/* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
! 2000, 2001, 2003, 2004
Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
*************** const struct m68k_opcode m68k_opcodes[]
*** 1459,1502 ****
{"lsrl", one(0160210), one(0170770), "QdDs", m68000up | mcf },
{"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcf },
! /* FIXME: add MAM mode (`&' after <ea> operand) / remove MACM */
! {"macw", two(0120000, 0000000), two(0170660, 0005400), "uMum", mcf5206eup },
! {"macw", two(0120000, 0001000), two(0170660, 0005400), "uMumMh",mcf5206eup },
! {"macw", two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
! {"macw", two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
! {"macw", two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
! {"macw", two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
! {"macw", two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
! {"macw", two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
! {"macw", two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
! {"macw", two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
! {"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
! {"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
! {"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
! {"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
! {"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
! {"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
! {"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
! {"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
!
! {"macl", two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcf5206eup },
! {"macl", two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcf5206eup },
! {"macl", two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
! {"macl", two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
! {"macl", two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
! {"macl", two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
! {"macl", two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
! {"macl", two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
! {"macl", two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
! {"macl", two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
! {"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
! {"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
! {"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
! {"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
! {"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
! {"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
! {"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
! {"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
/* NOTE: The mcf5200 family programmer's reference manual does not
indicate the byte form of the movea instruction is invalid (as it
--- 1459,1491 ----
{"lsrl", one(0160210), one(0170770), "QdDs", m68000up | mcf },
{"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcf },
! {"macw", two(0xa000, 0x0000), two(0xf1b0, 0x0800), "uMum", mcfmac },
! {"macw", two(0xa000, 0x0000), two(0xf1b0, 0x0b00), "uMumiI", mcfmac },
! {"macw", two(0xa000, 0x0200), two(0xf1b0, 0x0b00), "uMumMh", mcfmac },
! {"macw", two(0xa080, 0x0000), two(0xf180, 0x0f30), "uNuo4/Rn", mcfmac },
! {"macw", two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
! {"macw", two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
!
! {"macw", two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX */
! {"macw", two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX */
! {"macw", two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX */
! {"macw", two(0xa000, 0x0000), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX */
! {"macw", two(0xa000, 0x0000), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX */
! {"macw", two(0xa000, 0x0200), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX */
!
! {"macl", two(0xa000, 0x0800), two(0xf1b0, 0x0800), "RMRm", mcfmac },
! {"macl", two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
! {"macl", two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
! {"macl", two(0xa080, 0x0800), two(0xf180, 0x0f30), "RNRo4/Rn", mcfmac },
! {"macl", two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
! {"macl", two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
!
! {"macl", two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
! {"macl", two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
! {"macl", two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
! {"macl", two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
! {"macl", two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
! {"macl", two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
/* NOTE: The mcf5200 family programmer's reference manual does not
indicate the byte form of the movea instruction is invalid (as it
*************** const struct m68k_opcode m68k_opcodes[]
*** 1518,1523 ****
--- 1507,1514 ----
{"moveal", one(0020100), one(0170700), "*lAd", m68000up | mcf },
{"moveaw", one(0030100), one(0170700), "*wAd", m68000up | mcf },
+ {"movclrl", one(0xA1C0), one(0xf9f0), "eFRs", mcfemac },
+
{"movec", one(0047173), one(0177777), "R1Jj", m68010up | mcf },
{"movec", one(0047173), one(0177777), "R1#j", m68010up | mcf },
{"movec", one(0047172), one(0177777), "JjR1", m68010up },
*************** const struct m68k_opcode m68k_opcodes[]
*** 1588,1603 ****
{"movel", one(0020000), one(0170000), "olnd", mcfv4up },
{"movel", one(0047140), one(0177770), "AsUd", m68000up | mcfv4e },
{"movel", one(0047150), one(0177770), "UdAs", m68000up | mcfv4e },
! {"movel", one(0120600), one(0177760), "EsRs", mcf5206eup },
! {"movel", one(0120400), one(0177760), "RsEs", mcf5206eup },
! {"movel", one(0120474), one(0177777), "#lEs", mcf5206eup },
! {"movel", one(0124600), one(0177760), "GsRs", mcf5206eup },
! {"movel", one(0124400), one(0177760), "RsGs", mcf5206eup },
! {"movel", one(0124474), one(0177777), "#lGs", mcf5206eup },
! {"movel", one(0126600), one(0177760), "HsRs", mcf5206eup },
! {"movel", one(0126400), one(0177760), "RsHs", mcf5206eup },
! {"movel", one(0126474), one(0177777), "#lHs", mcf5206eup },
! {"movel", one(0124700), one(0177777), "GsCs", mcf5206eup },
{"move", one(0030000), one(0170000), "*w%d", m68000up },
{"move", one(0030000), one(0170000), "ms%d", mcf },
--- 1579,1609 ----
{"movel", one(0020000), one(0170000), "olnd", mcfv4up },
{"movel", one(0047140), one(0177770), "AsUd", m68000up | mcfv4e },
{"movel", one(0047150), one(0177770), "UdAs", m68000up | mcfv4e },
! {"movel", one(0120600), one(0177760), "EsRs", mcfmac },
! {"movel", one(0120400), one(0177760), "RsEs", mcfmac },
! {"movel", one(0120474), one(0177777), "#lEs", mcfmac },
! {"movel", one(0124600), one(0177760), "GsRs", mcfmac },
! {"movel", one(0124400), one(0177760), "RsGs", mcfmac },
! {"movel", one(0124474), one(0177777), "#lGs", mcfmac },
! {"movel", one(0126600), one(0177760), "HsRs", mcfmac },
! {"movel", one(0126400), one(0177760), "RsHs", mcfmac },
! {"movel", one(0126474), one(0177777), "#lHs", mcfmac },
! {"movel", one(0124700), one(0177777), "GsCs", mcfmac },
!
! {"movel", one(0xa180), one(0xf9f0), "eFRs", mcfemac }, /* accX,Rx */
! {"movel", one(0xab80), one(0xfbf0), "g]Rs", mcfemac }, /* accextX,Rx */
! {"movel", one(0xa980), one(0xfff0), "G-Rs", mcfemac }, /* macsr,Rx */
! {"movel", one(0xad80), one(0xfff0), "H-Rs", mcfemac }, /* mask,Rx */
! {"movel", one(0xa110), one(0xf9fc), "efeF", mcfemac }, /* accy,accX */
! {"movel", one(0xa9c0), one(0xffff), "G-C-", mcfemac }, /* macsr,ccr */
! {"movel", one(0xa100), one(0xf9f0), "RseF", mcfemac }, /* Rx,accX */
! {"movel", one(0xa13c), one(0xf9ff), "#leF", mcfemac }, /* #,accX */
! {"movel", one(0xab00), one(0xfbc0), "Rsg]", mcfemac }, /* Rx,accextX */
! {"movel", one(0xab3c), one(0xfbff), "#lg]", mcfemac }, /* #,accextX */
! {"movel", one(0xa900), one(0xffc0), "RsG-", mcfemac }, /* Rx,macsr */
! {"movel", one(0xa93c), one(0xffff), "#lG-", mcfemac }, /* #,macsr */
! {"movel", one(0xad00), one(0xffc0), "RsH-", mcfemac }, /* Rx,mask */
! {"movel", one(0xad3c), one(0xffff), "#lH-", mcfemac }, /* #,mask */
{"move", one(0030000), one(0170000), "*w%d", m68000up },
{"move", one(0030000), one(0170000), "ms%d", mcf },
*************** const struct m68k_opcode m68k_opcodes[]
*** 1637,1680 ****
{"move16", one(0xf610), one(0xfff8), "as_L", m68040up },
{"move16", one(0xf618), one(0xfff8), "_Las", m68040up },
! /* FIXME: add MAM mode (`&' after <ea> operand) / remove MSACM */
! {"msacw", two(0120000, 0000400), two(0170660, 0005400), "uMum", mcf5206eup },
! {"msacw", two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcf5206eup },
! {"msacw", two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
! {"msacw", two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
! {"msacw", two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
! {"msacw", two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
! {"msacw", two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
! {"msacw", two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
! {"msacw", two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
! {"msacw", two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
! {"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
! {"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
! {"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
! {"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
! {"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
! {"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
! {"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
! {"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
!
! {"msacl", two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcf5206eup },
! {"msacl", two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcf5206eup },
! {"msacl", two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
! {"msacl", two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
! {"msacl", two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
! {"msacl", two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
! {"msacl", two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
! {"msacl", two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
! {"msacl", two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
! {"msacl", two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
! {"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
! {"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
! {"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
! {"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
! {"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
! {"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
! {"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
! {"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
{"mulsw", one(0140700), one(0170700), ";wDd", m68000up|mcf },
{"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
--- 1643,1675 ----
{"move16", one(0xf610), one(0xfff8), "as_L", m68040up },
{"move16", one(0xf618), one(0xfff8), "_Las", m68040up },
! {"msacw", two(0xa000, 0x0100), two(0xf1b0, 0x0800), "uMum", mcfmac },
! {"msacw", two(0xa000, 0x0100), two(0xf1b0, 0x0b00), "uMumiI", mcfmac },
! {"msacw", two(0xa000, 0x0300), two(0xf1b0, 0x0b00), "uMumMh", mcfmac },
! {"msacw", two(0xa080, 0x0100), two(0xf180, 0x0f30), "uNuo4/Rn", mcfmac },
! {"msacw", two(0xa080, 0x0100), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
! {"msacw", two(0xa080, 0x0300), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
!
! {"msacw", two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX */
! {"msacw", two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX */
! {"msacw", two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX */
! {"msacw", two(0xa000, 0x0100), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX */
! {"msacw", two(0xa000, 0x0100), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX */
! {"msacw", two(0xa000, 0x0300), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX */
!
! {"msacl", two(0xa000, 0x0900), two(0xf1b0, 0x0800), "RMRm", mcfmac },
! {"msacl", two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
! {"msacl", two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
! {"msacl", two(0xa080, 0x0900), two(0xf180, 0x0f30), "RNRo4/Rn", mcfmac },
! {"msacl", two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
! {"msacl", two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
!
! {"msacl", two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
! {"msacl", two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
! {"msacl", two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
! {"msacl", two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
! {"msacl", two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
! {"msacl", two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
{"mulsw", one(0140700), one(0170700), ";wDd", m68000up|mcf },
{"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },