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Re: mtsprg on BOOKE
- From: Kumar Gala <kumar dot gala at freescale dot com>
- To: <jbaker at qnx dot com>
- Cc: <binutils at sources dot redhat dot com>, "James E Wilson" <wilson at specifixinc dot com>
- Date: Mon, 1 Nov 2004 14:25:42 -0600
- Subject: Re: mtsprg on BOOKE
- References: <41865588.8080002@qnx.com>
Jeff,
Looking at opcode/ppc-opc.c I think what you want to look at modifying
the following:
/* The operands table.
The fields are bits, shift, insert, extract, flags.
We used to put parens around the various additions, like the one
for BA just below. However, that caused trouble with feeble
compilers with a limit on depth of a parenthesized expression, like
(reportedly) the compiler in Microsoft Developer Studio 5. So we
omit the parens, since the macros are never used in a context where
the addition will be ambiguous. */
.... [snip] ....
/* The SPRG register number in an XFX form m[ft]sprg instruction. */
#define SPRG SPRBAT + 1
#define SPRG_MASK (0x3 << 16)
{ 2, 16, NULL, NULL, 0 },
--
You will want to grow the size of the field from 2 bits to 3. I can
remember if you will need to adjust the shift amount or not. I would
also recommend adding some testcases to gas/testsuite/ppc/booke.{s,d}
- kumar
On Nov 1, 2004, at 9:26 AM, Jeff Baker wrote:
I've never worked in the opcodes area before and I'm not sure how to
implement this change.? Can anyone give me a hand?
James E Wilson wrote:
> On Fri, 2004-10-29 at 09:17, Jeff Baker wrote:
>
>>Why does the following assembly produce errors on BOOKE?
>>mtsprg 7, %r3
>
>
> Looking at the sources, opcode/ppc-opc.c, I see that the mtsprg macro
> only takes 2-bit sprg register numbers, which is apparently correct
for
> the basic ppc architecture, but not for e500.? This should probably
be
> conditional on the architecture choice.? I haven't looked at any
> architecture or processor manuals to double check.
>
> Meanwhile, "mtsprg7 %r3" will work.? Likewise for mfsprg.