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Re: Broken SH2a patches
- From: Nick Clifton <nickc at redhat dot com>
- To: Andrew STUBBS <andrew dot stubbs at st dot com>, 'Alexandre Oliva' <aoliva at redhat dot com>
- Cc: binutils at sources dot redhat dot com
- Date: Mon, 08 Nov 2004 09:07:00 +0000
- Subject: Re: Broken SH2a patches
- References: <02e501c4bdb0$9f530b50$180f81a4@uk.w2k.superh.com>
Hi Andrew,
Sorry that this is later than advertised...
I agree that there may be some problem inserting it into the diagram, but
the important ting is that it must be inserted into the inheritance tree in
the code and that the |s (ors) are removed from the instruction table (the
op32 stuff may be ok, but the others have to go).
Ok, here is a patch that I think fixes up the diagram and removes the
|'s from the opcodes table. What do you think ?
My other concern is the arch_op32 thingy. I don't know what it is for, or
what the affect on the architecture code is, but you should be aware that it
will not be encoded into the elf flags and, therefore, will not be available
at link time. If it is only intended to be for the assembler then it may be
ok.
It is intended for the assembler and disassembler. It has no affect on
architecture selection.
Cheers
Nick
bfd/ChangeLog
2004-11-08 Nick Clifton <nickc@redhat.com>
* archures.c: Add fake SH2A architectures.
* bfd-in2.h: Regenerate.
* cpu-sh.c: Add entries for fake SH2A architectures.
binutils/ChangeLog
2004-11-08 Nick Clifton <nickc@redhat.com>
* readelf.c: Add support for fake SH2A architectures.
gas/testsuite/ChangeLog
2004-11-08 Nick Clifton <nickc@redhat.com>
* gas/sh/arch/arch_expected.txt: Replace expected sh3e
architectures with sh2a_(fake2).
* gas/sh/arch/sh4.s: Replace fabs with frchg as the fabs
instructions is used by SH2A as well.
include/elf/ChangeLog
2004-11-08 Nick Clifton <nickc@redhat.com>
* sh.h: Use hex constants for the EF flags to better demonstrate
how the masking works.
(EF_SH2A_FAKE1, EF_SH2A_FAKE2, EF_SH2A_FAKE3, EF_SH2A_FAKE4):
Define.
(EF_SH_BFD_TABLE): Add fake SH2A architectures.
ld/testsuite/ChangeLog
2004-11-08 Nick Clifton <nickc@redhat.com>
* ld-sh/arch/arch_expected.txt: Replace expected sh3e
architectures with sh2a_(fake2).
* ld-sh/arch/sh4.s: Replace fabs with frchg as the fabs
instructions is used by SH2A as well.
opcodes/ChangeLog
2004-11-08 Nick Clifton <nickc@redhat.com>
* sh-opc.h (sh_table): Create fake SH2A architectures so that
every SH opcode has exactly one associated base architecture.
Update the SH architecture relationship diagram to add nodes for
these fake architectures.
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.98
diff -c -3 -p -r1.98 archures.c
*** bfd/archures.c 4 Nov 2004 14:58:13 -0000 1.98
--- bfd/archures.c 8 Nov 2004 08:52:54 -0000
*************** DESCRIPTION
*** 234,239 ****
--- 234,243 ----
.#define bfd_mach_sh_dsp 0x2d
.#define bfd_mach_sh2a 0x2a
.#define bfd_mach_sh2a_nofpu 0x2b
+ .#define bfd_mach_sh2a_fake1 0x2a1
+ .#define bfd_mach_sh2a_fake2 0x2a2
+ .#define bfd_mach_sh2a_fake3 0x2a3
+ .#define bfd_mach_sh2a_fake4 0x2a4
.#define bfd_mach_sh2e 0x2e
.#define bfd_mach_sh3 0x30
.#define bfd_mach_sh3_nommu 0x31
Index: bfd/cpu-sh.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-sh.c,v
retrieving revision 1.17
diff -c -3 -p -r1.17 cpu-sh.c
*** bfd/cpu-sh.c 13 Aug 2004 03:15:56 -0000 1.17
--- bfd/cpu-sh.c 8 Nov 2004 08:52:56 -0000
***************
*** 24,46 ****
#include "libbfd.h"
#include "../opcodes/sh-opc.h"
! #define SH_NEXT &arch_info_struct[0]
! #define SH2_NEXT &arch_info_struct[1]
! #define SH2E_NEXT &arch_info_struct[2]
! #define SH_DSP_NEXT &arch_info_struct[3]
! #define SH3_NEXT &arch_info_struct[4]
! #define SH3_NOMMU_NEXT &arch_info_struct[5]
! #define SH3_DSP_NEXT &arch_info_struct[6]
! #define SH3E_NEXT &arch_info_struct[7]
! #define SH4_NEXT &arch_info_struct[8]
! #define SH4A_NEXT &arch_info_struct[9]
! #define SH4AL_DSP_NEXT &arch_info_struct[10]
! #define SH4_NOFPU_NEXT &arch_info_struct[11]
! #define SH4_NOMMU_NOFPU_NEXT &arch_info_struct[12]
! #define SH4A_NOFPU_NEXT &arch_info_struct[13]
! #define SH2A_NEXT &arch_info_struct[14]
! #define SH2A_NOFPU_NEXT &arch_info_struct[15]
! #define SH64_NEXT NULL
static const bfd_arch_info_type arch_info_struct[] =
{
--- 24,50 ----
#include "libbfd.h"
#include "../opcodes/sh-opc.h"
! #define SH_NEXT arch_info_struct + 0
! #define SH2_NEXT arch_info_struct + 1
! #define SH2E_NEXT arch_info_struct + 2
! #define SH_DSP_NEXT arch_info_struct + 3
! #define SH3_NEXT arch_info_struct + 4
! #define SH3_NOMMU_NEXT arch_info_struct + 5
! #define SH3_DSP_NEXT arch_info_struct + 6
! #define SH3E_NEXT arch_info_struct + 7
! #define SH4_NEXT arch_info_struct + 8
! #define SH4A_NEXT arch_info_struct + 9
! #define SH4AL_DSP_NEXT arch_info_struct + 10
! #define SH4_NOFPU_NEXT arch_info_struct + 11
! #define SH4_NOMMU_NOFPU_NEXT arch_info_struct + 12
! #define SH4A_NOFPU_NEXT arch_info_struct + 13
! #define SH2A_NEXT arch_info_struct + 14
! #define SH2A_NOFPU_NEXT arch_info_struct + 15
! #define SH64_NEXT arch_info_struct + 16
! #define SH2A_FAKE1_NEXT arch_info_struct + 17
! #define SH2A_FAKE2_NEXT arch_info_struct + 18
! #define SH2A_FAKE3_NEXT arch_info_struct + 19
! #define SH2A_FAKE4_NEXT NULL
static const bfd_arch_info_type arch_info_struct[] =
{
*************** static const bfd_arch_info_type arch_inf
*** 268,273 ****
--- 272,333 ----
bfd_default_scan,
SH64_NEXT
},
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_sh2a_fake1,
+ "sh", /* Arch_name. */
+ "sh2a_(fake1)", /* Printable name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ SH2A_FAKE1_NEXT
+ },
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_sh2a_fake2,
+ "sh", /* Arch_name. */
+ "sh2a_(fake2)", /* Printable name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ SH2A_FAKE2_NEXT
+ },
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_sh2a_fake3,
+ "sh", /* Arch_name. */
+ "sh2a_(fake3)", /* Printable name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ SH2A_FAKE3_NEXT
+ },
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_sh2a_fake4,
+ "sh", /* Arch_name. */
+ "sh2a_(fake4)", /* Printable name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ SH2A_FAKE4_NEXT
+ },
};
const bfd_arch_info_type bfd_sh_arch =
*************** const bfd_arch_info_type bfd_sh_arch =
*** 293,299 ****
The prototypes for these SH specific functions are found in
sh-opc.h . */
! static struct { unsigned long bfd_mach, arch, arch_up; } bfd_to_arch_table[] =
{
{ bfd_mach_sh, arch_sh1, arch_sh1_up },
{ bfd_mach_sh2, arch_sh2, arch_sh2_up },
--- 353,365 ----
The prototypes for these SH specific functions are found in
sh-opc.h . */
! static struct
! {
! unsigned long bfd_mach;
! unsigned long arch;
! unsigned long arch_up;
! }
! bfd_to_arch_table[] =
{
{ bfd_mach_sh, arch_sh1, arch_sh1_up },
{ bfd_mach_sh2, arch_sh2, arch_sh2_up },
*************** static struct { unsigned long bfd_mach,
*** 311,316 ****
--- 377,388 ----
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofp_up },
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofp_up },
+
+ { bfd_mach_sh2a_fake1, arch_sh2a_nofpu_fake1, arch_sh2a_nofpu_sh3_nommu_up },
+ { bfd_mach_sh2a_fake2, arch_sh2a_fake2, arch_sh2a_sh3e_up },
+ { bfd_mach_sh2a_fake3, arch_sh2a_nofpu_fake3, arch_sh2a_nofpu_sh4_nommu_up },
+ { bfd_mach_sh2a_fake4, arch_sh2a_fake4, arch_sh2a_sh4_up },
+
{ 0, 0, 0 } /* Terminator. */
};
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.264
diff -c -3 -p -r1.264 readelf.c
*** binutils/readelf.c 3 Nov 2004 10:44:43 -0000 1.264
--- binutils/readelf.c 8 Nov 2004 08:52:59 -0000
*************** get_machine_flags (unsigned e_flags, uns
*** 2081,2088 ****
case EF_SH2A: strcat (buf, ", sh2a"); break;
case EF_SH4_NOFPU: strcat (buf, ", sh4-nofpu"); break;
case EF_SH4A_NOFPU: strcat (buf, ", sh4a-nofpu"); break;
case EF_SH2A_NOFPU: strcat (buf, ", sh2a-nofpu"); break;
! default: strcat (buf, ", unknown ISA"); break;
}
break;
--- 2081,2094 ----
case EF_SH2A: strcat (buf, ", sh2a"); break;
case EF_SH4_NOFPU: strcat (buf, ", sh4-nofpu"); break;
case EF_SH4A_NOFPU: strcat (buf, ", sh4a-nofpu"); break;
+ case EF_SH4_NOMMU_NOFPU: strcat (buf,", sh4-nommu-nofpu"); break;
case EF_SH2A_NOFPU: strcat (buf, ", sh2a-nofpu"); break;
! case EF_SH3_NOMMU: strcat (buf, ", sh3-nommu"); break;
! case EF_SH2A_FAKE1: strcat (buf, ", sh2a (fake1)"); break;
! case EF_SH2A_FAKE2: strcat (buf, ", sh2a (fake2)"); break;
! case EF_SH2A_FAKE3: strcat (buf, ", sh2a (fake3)"); break;
! case EF_SH2A_FAKE4: strcat (buf, ", sh2a (fake4)"); break;
! default: strcat (buf, ", unknown ISA: "); break;
}
break;
Index: gas/testsuite/gas/sh/arch/arch_expected.txt
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/sh/arch/arch_expected.txt,v
retrieving revision 1.1
diff -c -3 -p -r1.1 arch_expected.txt
*** gas/testsuite/gas/sh/arch/arch_expected.txt 29 Jun 2004 16:35:05 -0000 1.1
--- gas/testsuite/gas/sh/arch/arch_expected.txt 8 Nov 2004 08:53:01 -0000
*************** sh3.s -isa=sh4a
*** 241,259 ****
sh3.s -isa=sh4a-up sh4a
sh3.s -isa=sh4al-dsp sh4al-dsp
sh3.s -isa=sh4al-dsp-up sh4al-dsp
! sh3e.s default-options sh3e
sh3e.s -dsp ERROR
! sh3e.s -isa=any sh3e
sh3e.s -isa=dsp ERROR
! sh3e.s -isa=fp sh3e
sh3e.s -isa=sh-dsp ERROR
sh3e.s -isa=sh-dsp-up ERROR
sh3e.s -isa=sh ERROR
! sh3e.s -isa=sh-up sh3e
sh3e.s -isa=sh2 ERROR
! sh3e.s -isa=sh2-up sh3e
! sh3e.s -isa=sh2e ERROR
! sh3e.s -isa=sh2e-up sh3e
sh3e.s -isa=sh3-dsp ERROR
sh3e.s -isa=sh3-dsp-up ERROR
sh3e.s -isa=sh3-nommu ERROR
--- 241,259 ----
sh3.s -isa=sh4a-up sh4a
sh3.s -isa=sh4al-dsp sh4al-dsp
sh3.s -isa=sh4al-dsp-up sh4al-dsp
! sh3e.s default-options sh2a_(fake2)
sh3e.s -dsp ERROR
! sh3e.s -isa=any sh2a_(fake2)
sh3e.s -isa=dsp ERROR
! sh3e.s -isa=fp sh2a_(fake2)
sh3e.s -isa=sh-dsp ERROR
sh3e.s -isa=sh-dsp-up ERROR
sh3e.s -isa=sh ERROR
! sh3e.s -isa=sh-up sh2a_(fake2)
sh3e.s -isa=sh2 ERROR
! sh3e.s -isa=sh2-up sh2a_(fake2)
! sh3e.s -isa=sh2e sh2a_(fake2)
! sh3e.s -isa=sh2e-up sh2a_(fake2)
sh3e.s -isa=sh3-dsp ERROR
sh3e.s -isa=sh3-dsp-up ERROR
sh3e.s -isa=sh3-nommu ERROR
Index: gas/testsuite/gas/sh/arch/sh4.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/sh/arch/sh4.s,v
retrieving revision 1.1
diff -c -3 -p -r1.1 sh4.s
*** gas/testsuite/gas/sh/arch/sh4.s 29 Jun 2004 16:35:05 -0000 1.1
--- gas/testsuite/gas/sh/arch/sh4.s 8 Nov 2004 08:53:01 -0000
***************
*** 1,3 ****
.section .text
sh4:
! fabs dr0
--- 1,3 ----
.section .text
sh4:
! frchg
Index: include/elf/sh.h
===================================================================
RCS file: /cvs/src/src/include/elf/sh.h,v
retrieving revision 1.19
diff -c -3 -p -r1.19 sh.h
*** include/elf/sh.h 29 Jul 2004 05:17:37 -0000 1.19
--- include/elf/sh.h 8 Nov 2004 08:53:01 -0000
***************
*** 22,49 ****
/* Processor specific flags for the ELF header e_flags field. */
! #define EF_SH_MACH_MASK 0x1f
! #define EF_SH_UNKNOWN 0 /* For backwards compatibility. */
! #define EF_SH1 1
! #define EF_SH2 2
! #define EF_SH3 3
! #define EF_SH_DSP 4
! #define EF_SH3_DSP 5
! #define EF_SH4AL_DSP 6
! #define EF_SH3E 8
! #define EF_SH4 9
! #define EF_SH2E 11
! #define EF_SH4A 12
! #define EF_SH2A 13
!
! #define EF_SH4_NOFPU 16
! #define EF_SH4A_NOFPU 17
! #define EF_SH4_NOMMU_NOFPU 18
! #define EF_SH2A_NOFPU 19
! #define EF_SH3_NOMMU 20
/* This one can only mix in objects from other EF_SH5 objects. */
! #define EF_SH5 10
/* Define the mapping from ELF to bfd mach numbers.
bfd_mach_* are defined in bfd_in2.h (generated from
--- 22,56 ----
/* Processor specific flags for the ELF header e_flags field. */
! #define EF_SH_MACH_MASK 0x1f
! #define EF_SH_UNKNOWN 0x00 /* For backwards compatibility. */
! #define EF_SH1 0x01
! #define EF_SH2 0x02
! #define EF_SH3 0x03
! #define EF_SH_DSP 0x04
! #define EF_SH3_DSP 0x05
! #define EF_SH4AL_DSP 0x06
! #define EF_SH3E 0x08
! #define EF_SH4 0x09
/* This one can only mix in objects from other EF_SH5 objects. */
! #define EF_SH5 0x0a
!
! #define EF_SH2E 0x0b
! #define EF_SH4A 0x0c
! #define EF_SH2A 0x0d
!
! #define EF_SH4_NOFPU 0x10
! #define EF_SH4A_NOFPU 0x11
! #define EF_SH4_NOMMU_NOFPU 0x12
! #define EF_SH2A_NOFPU 0x13
! #define EF_SH3_NOMMU 0x14
!
! #define EF_SH2A_FAKE1 0x15
! #define EF_SH2A_FAKE2 0x16
! #define EF_SH2A_FAKE3 0x17
! #define EF_SH2A_FAKE4 0x18
!
/* Define the mapping from ELF to bfd mach numbers.
bfd_mach_* are defined in bfd_in2.h (generated from
***************
*** 68,74 ****
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
/* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \
! /* EF_SH3_NOMMU */ bfd_mach_sh3_nommu
/* Convert arch_sh* into EF_SH*. */
int sh_find_elf_flags (unsigned int arch_set);
--- 75,85 ----
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
/* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \
! /* EF_SH3_NOMMU */ bfd_mach_sh3_nommu ,\
! /* EF_SH2A_FAKE1 */ bfd_mach_sh2a_fake1 , \
! /* EF_SH2A_FAKE2 */ bfd_mach_sh2a_fake2 , \
! /* EF_SH2A_FAKE3 */ bfd_mach_sh2a_fake3 , \
! /* EF_SH2A_FAKE4 */ bfd_mach_sh2a_fake4
/* Convert arch_sh* into EF_SH*. */
int sh_find_elf_flags (unsigned int arch_set);
Index: ld/testsuite/ld-sh/arch/arch_expected.txt
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-sh/arch/arch_expected.txt,v
retrieving revision 1.1
diff -c -3 -p -r1.1 arch_expected.txt
*** ld/testsuite/ld-sh/arch/arch_expected.txt 29 Jun 2004 16:35:05 -0000 1.1
--- ld/testsuite/ld-sh/arch/arch_expected.txt 8 Nov 2004 08:53:01 -0000
*************** sh.o sh2e.o
*** 32,38 ****
sh.o sh3-dsp.o sh3-dsp
sh.o sh3-nommu.o sh3-nommu
sh.o sh3.o sh3
! sh.o sh3e.o sh3e
sh.o sh4-nofpu.o sh4-nofpu
sh.o sh4-nommu-nofpu.o sh4-nommu-nofpu
sh.o sh4.o sh4
--- 32,38 ----
sh.o sh3-dsp.o sh3-dsp
sh.o sh3-nommu.o sh3-nommu
sh.o sh3.o sh3
! sh.o sh3e.o sh2a_(fake2)
sh.o sh4-nofpu.o sh4-nofpu
sh.o sh4-nommu-nofpu.o sh4-nommu-nofpu
sh.o sh4.o sh4
*************** sh2.o sh2e.o
*** 47,53 ****
sh2.o sh3-dsp.o sh3-dsp
sh2.o sh3-nommu.o sh3-nommu
sh2.o sh3.o sh3
! sh2.o sh3e.o sh3e
sh2.o sh4-nofpu.o sh4-nofpu
sh2.o sh4-nommu-nofpu.o sh4-nommu-nofpu
sh2.o sh4.o sh4
--- 47,53 ----
sh2.o sh3-dsp.o sh3-dsp
sh2.o sh3-nommu.o sh3-nommu
sh2.o sh3.o sh3
! sh2.o sh3e.o sh2a_(fake2)
sh2.o sh4-nofpu.o sh4-nofpu
sh2.o sh4-nommu-nofpu.o sh4-nommu-nofpu
sh2.o sh4.o sh4
*************** sh2e.o sh2e.o
*** 62,68 ****
sh2e.o sh3-dsp.o ERROR
sh2e.o sh3-nommu.o sh3e
sh2e.o sh3.o sh3e
! sh2e.o sh3e.o sh3e
sh2e.o sh4-nofpu.o sh4
sh2e.o sh4-nommu-nofpu.o sh4
sh2e.o sh4.o sh4
--- 62,68 ----
sh2e.o sh3-dsp.o ERROR
sh2e.o sh3-nommu.o sh3e
sh2e.o sh3.o sh3e
! sh2e.o sh3e.o sh2a_(fake2)
sh2e.o sh4-nofpu.o sh4
sh2e.o sh4-nommu-nofpu.o sh4
sh2e.o sh4.o sh4
*************** sh3.o sh4a.o
*** 116,128 ****
sh3.o sh4al-dsp.o sh4al-dsp
sh3.o sh-unknown.o sh3
sh3e.o sh-dsp.o ERROR
! sh3e.o sh.o sh3e
! sh3e.o sh2.o sh3e
! sh3e.o sh2e.o sh3e
sh3e.o sh3-dsp.o ERROR
sh3e.o sh3-nommu.o sh3e
sh3e.o sh3.o sh3e
! sh3e.o sh3e.o sh3e
sh3e.o sh4-nofpu.o sh4
sh3e.o sh4-nommu-nofpu.o sh4
sh3e.o sh4.o sh4
--- 116,128 ----
sh3.o sh4al-dsp.o sh4al-dsp
sh3.o sh-unknown.o sh3
sh3e.o sh-dsp.o ERROR
! sh3e.o sh.o sh2a_(fake2)
! sh3e.o sh2.o sh2a_(fake2)
! sh3e.o sh2e.o sh2a_(fake2)
sh3e.o sh3-dsp.o ERROR
sh3e.o sh3-nommu.o sh3e
sh3e.o sh3.o sh3e
! sh3e.o sh3e.o sh2a_(fake2)
sh3e.o sh4-nofpu.o sh4
sh3e.o sh4-nommu-nofpu.o sh4
sh3e.o sh4.o sh4
Index: ld/testsuite/ld-sh/arch/sh4.s
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-sh/arch/sh4.s,v
retrieving revision 1.1
diff -c -3 -p -r1.1 sh4.s
*** ld/testsuite/ld-sh/arch/sh4.s 29 Jun 2004 16:35:05 -0000 1.1
--- ld/testsuite/ld-sh/arch/sh4.s 8 Nov 2004 08:53:01 -0000
***************
*** 1,3 ****
.section .text
sh4:
! fabs dr0
--- 1,3 ----
.section .text
sh4:
! frchg
Index: opcodes/sh-opc.h
===================================================================
RCS file: /cvs/src/src/opcodes/sh-opc.h,v
retrieving revision 1.22
diff -c -3 -p -r1.22 sh-opc.h
*** opcodes/sh-opc.h 29 Jul 2004 05:19:27 -0000 1.22
--- opcodes/sh-opc.h 8 Nov 2004 08:53:02 -0000
*************** typedef enum
*** 198,244 ****
}
sh_dsp_reg_nums;
- #define arch_sh1_base 0x0001
- #define arch_sh2_base 0x0002
- #define arch_sh3_base 0x0004
- #define arch_sh4_base 0x0008
- #define arch_sh4a_base 0x0010
- #define arch_sh2a_base 0x0020
-
- /* This is an annotation on instruction types, but we abuse the arch
- field in instructions to denote it. */
- #define arch_op32 0x00100000 /* This is a 32-bit opcode. */
-
- #define arch_sh_no_mmu 0x04000000
- #define arch_sh_has_mmu 0x08000000
- #define arch_sh_no_co 0x10000000 /* neither FPU nor DSP co-processor */
- #define arch_sh_sp_fpu 0x20000000 /* single precision FPU */
- #define arch_sh_dp_fpu 0x40000000 /* double precision FPU */
- #define arch_sh_has_dsp 0x80000000
-
-
#define arch_sh_base_mask 0x0000003f
! #define arch_opann_mask 0x00100000
#define arch_sh_mmu_mask 0x0c000000
#define arch_sh_co_mask 0xf0000000
! #define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
! #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
! #define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp)
! #define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co)
! #define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu)
! #define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp)
! #define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu)
! #define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)
! #define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)
! #define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co)
! #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)
! #define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co)
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
--- 198,248 ----
}
sh_dsp_reg_nums;
#define arch_sh_base_mask 0x0000003f
! #define arch_sh1_base 0x00000001
! #define arch_sh2_base 0x00000002
! #define arch_sh3_base 0x00000004
! #define arch_sh4_base 0x00000008
! #define arch_sh4a_base 0x00000010
! #define arch_sh2a_base 0x00000020
!
#define arch_sh_mmu_mask 0x0c000000
+ #define arch_sh_no_mmu 0x04000000
+ #define arch_sh_has_mmu 0x08000000
+
#define arch_sh_co_mask 0xf0000000
+ #define arch_sh_no_co 0x10000000 /* Neither FPU nor DSP co-processor. */
+ #define arch_sh_sp_fpu 0x20000000 /* Single precision FPU. */
+ #define arch_sh_dp_fpu 0x40000000 /* Double precision FPU. */
+ #define arch_sh_has_dsp 0x80000000
+
+ /* This is an annotation on instruction types, but we
+ abuse the arch field in instructions to denote it. */
+ #define arch_opann_mask 0x00100000
+ #define arch_op32 0x00100000 /* This is a 32-bit opcode. */
! #define arch_sh1 (arch_sh1_base |arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh2 (arch_sh2_base |arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
! #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh2e (arch_sh2_base |arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
! #define arch_sh_dsp (arch_sh2_base |arch_sh_no_mmu|arch_sh_has_dsp)
! #define arch_sh3_nommu (arch_sh3_base |arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh3 (arch_sh3_base |arch_sh_has_mmu|arch_sh_no_co)
! #define arch_sh3e (arch_sh3_base |arch_sh_has_mmu|arch_sh_sp_fpu)
! #define arch_sh3_dsp (arch_sh3_base |arch_sh_has_mmu|arch_sh_has_dsp)
! #define arch_sh4 (arch_sh4_base |arch_sh_has_mmu|arch_sh_dp_fpu)
! #define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)
! #define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)
! #define arch_sh4_nofpu (arch_sh4_base |arch_sh_has_mmu|arch_sh_no_co)
! #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)
! #define arch_sh4_nommu_nofpu (arch_sh4_base |arch_sh_no_mmu|arch_sh_no_co)
!
! #define arch_sh2a_nofpu_fake1 (arch_sh2_base |arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh2a_fake2 (arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
! #define arch_sh2a_nofpu_fake3 (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
! #define arch_sh2a_fake4 (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
*************** bfd_boolean sh_merge_bfd_arch (bfd *ibfd
*** 276,323 ****
SH2
.------------'|`--------------------.
/ | \
! SH-DSP SH3-nommu SH2E
! | |`--------. |
! | | \ |
! | SH3 SH4-nommu-nofpu |
! | | | |
! | .------------'|`----------+---------. |
! |/ / \|
! | | .-------' |
! | |/ |
! SH3-dsp SH4-nofpu SH3E
! | |`--------------------. |
! | | \|
! | SH4A-nofpu SH4
! | .------------' `--------------------. |
! |/ \|
! SH4AL-dsp SH4A
!
*/
! /* Central branches */
! #define arch_sh1_up (arch_sh1 | arch_sh2_up)
! #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up)
! #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up)
! #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up)
! #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
! #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
! #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
!
! /* Right branch */
! #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up)
! #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
! #define arch_sh4_up (arch_sh4 | arch_sh4a_up)
! #define arch_sh4a_up (arch_sh4a)
!
! /* Left branch */
! #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
! #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
! #define arch_sh4al_dsp_up (arch_sh4al_dsp)
!
! /* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */
! #define arch_sh2a_up (arch_sh2a)
! #define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up)
typedef struct
--- 280,341 ----
SH2
.------------'|`--------------------.
/ | \
! SH2 SH2A SH2E
! (dsp) (fake1) |
! | /\ |
! | / \ |
! | / \ |
! | .----' SH3 SH2A
! | / (nommu) (fake2)
! | | /\ /\
! | | / \ / \
! | | / \ / \
! | | SH2A SH3 / |
! | | (fake3) /|\ / |
! | | /\ / | \ / |
! | | ----' \ .../ | ----. / |
! | | / . \ | \/ |
! | SH2A . SH4 | SH3E |
! | (nofpu) . (nommu) | | |
! | | . (nofpu) | | |
! | ...+..... | .--' | |
! | / | . | / | |
! SH3 | SH4 SH2A |
! (dsp) | (nofpu) (fake4) |
! | | /\ /\ |
! | | / '---. .--'. \ .-----'
! | | / \ / \/
! -+---- . SH4A SH4 SH2A <------....
! | (nofpu) |
! | / \ .-'
! | .--------' '---. /
! | / \/
! SH4AL SH4A
! (dsp)
*/
! #define arch_sh1_up (arch_sh1 | arch_sh2_up)
! #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up)
! #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up)
! #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up)
! #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
! #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
! #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
! #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up)
! #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
! #define arch_sh4_up (arch_sh4 | arch_sh4a_up)
! #define arch_sh4a_up (arch_sh4a)
! #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
! #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
! #define arch_sh4al_dsp_up (arch_sh4al_dsp)
! /* SH2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */
! #define arch_sh2a_up (arch_sh2a)
! #define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up)
!
! #define arch_sh2a_nofpu_sh3_nommu_up (arch_sh2a_nofpu_fake1 | arch_sh2_up)
! #define arch_sh2a_sh3e_up (arch_sh2a_fake2 | arch_sh3e_up)
! #define arch_sh2a_nofpu_sh4_nommu_up (arch_sh2a_nofpu_fake3 | arch_sh4_nommu_nofpu_up)
! #define arch_sh2a_sh4_up (arch_sh2a_fake4 | arch_sh3e_up)
typedef struct
*************** const sh_opcode_info sh_table[] =
*** 634,640 ****
/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
! /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up},
/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
--- 652,658 ----
/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
! /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_sh4_nommu_up},
/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
*************** const sh_opcode_info sh_table[] =
*** 664,672 ****
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
! /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
! /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up},
--- 682,690 ----
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
! /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_sh3_nommu_up},
! /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_sh3_nommu_up},
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up},
*************** const sh_opcode_info sh_table[] =
*** 985,1007 ****
{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
! /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up},
! /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up},
! /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up},
! /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up},
! /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up},
! /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up},
! /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up},
/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
--- 1003,1025 ----
{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
! /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up},
! /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up},
! /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up},
! /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_sh4_up},
! /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_sh4_up},
! /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up},
! /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_sh4_up},
/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
*************** const sh_opcode_info sh_table[] =
*** 1012,1053 ****
/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up},
/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up},
! /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up},
/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up},
! /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
! /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
! /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
! /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
! /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
! /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
! /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
! /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
! /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
! /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
! /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
! /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
! /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */
{"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */
--- 1030,1071 ----
/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up},
/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up},
! /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up},
/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up},
! /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
! /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
! /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
! /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
! /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
! /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_sh4_up},
/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
! /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_sh4_up},
! /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_sh4_up},
! /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_sh4_up},
! /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_sh4_up},
! /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_sh4_up},
! /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_sh4_up},
! /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_sh4_up},
/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */
{"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */
*************** const sh_opcode_info sh_table[] =
*** 1070,1079 ****
{"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up},
! /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
! /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up},
/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up},
--- 1088,1097 ----
{"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up},
! /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_sh4_up},
/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
! /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_sh4_up},
/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up},
*************** const sh_opcode_info sh_table[] =
*** 1081,1100 ****
/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up},
! /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up},
! /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up},
! /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up},
/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
! /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up},
/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up},
! /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up},
/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up},
--- 1099,1118 ----
/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up},
! /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_sh4_up},
! /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_sh3e_up},
! /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_sh4_up},
/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up},
/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
! /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_sh4_up},
/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up},
! /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_sh4_up},
/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up},