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gas and MIPS cp0 instructions
- From: Zack Weinberg <zack at codesourcery dot com>
- To: binutils at sources dot redhat dot com
- Date: Thu, 09 Dec 2004 12:32:42 -0800
- Subject: gas and MIPS cp0 instructions
One of CodeSourcery's clients is asking me why GAS rejects
cache 0x15,0($4)
when set to -mcpu=mips2. They claim, quite strenuously, that
> Many of the CP0 instructions while documented in the ISA manuals,
> are not strictly speaking part of the ISA definiton(s) themselves
> (by MIPS Technologies). Eret, cache, mtc0, mtc0, sync, ssnop (and
> friends) are part of the instructions which should be treated as
> ISA-independent.
>
> This is something that GNU has gotten consistantly wrong over the
> years. Cache is a legal instruction in MIPS-III, MIPS32, MIPS64
> (and a few other) processors. You can't tell if the instruction is
> supported or not just by looking at the ISA level.
I'd like to get your collective opinion on this.
zw