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Re: gas and MIPS cp0 instructions


On Thu, 2004-12-09 at 12:32 -0800, Zack Weinberg wrote:
> One of CodeSourcery's clients is asking me why GAS rejects
> 
>         cache 0x15,0($4)
> 
> when set to -mcpu=mips2.  They claim, quite strenuously, that 
> 
> > Many of the CP0 instructions while documented in the ISA manuals,
> > are not strictly speaking part of the ISA definiton(s) themselves
> > (by MIPS Technologies).  Eret, cache, mtc0, mtc0, sync, ssnop (and
> > friends) are part of the instructions which should be treated as
> > ISA-independent.
> >
> > This is something that GNU has gotten consistantly wrong over the
> > years.  Cache is a legal instruction in MIPS-III, MIPS32, MIPS64
> > (and a few other) processors.  You can't tell if the instruction is
> > supported or not just by looking at the ISA level.
> 
> I'd like to get your collective opinion on this.

They're wrong according to the documentation that I can find. I see it
as an R4000 instruction in my Kane and Heinrich book where it states
that it's an R4000 instruction only, the newer MIPS32 and MIPS64
standards have it, curiously, as a MIPS32 instruction only, but I'm
willing to bet that's a typo in the version I have. Also, we allow
instructions by processor as well. If they have a cpu that has the
instruction then it can be added to gas so that if they accept that
instruction in some encoding it can be added.

If they has some other documentation that states something else I'd love
to see it and will happily enable the instruction for a particular ISA -
if they can prove that all chips of that ISA provide the instruction.
Otherwise we can go with individual cpus.

-eric



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