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Re: [PATCH] Add a second 'pinfo' member to mips_opcode to extend number of available bits
On Thursday 20 January 2005 11:59, Eric Christopher wrote:
> On Thu, 2005-01-20 at 11:52 +0000, Richard Sandiford wrote:
> > Just a suggestion (I've no authority here ;) but maybe it would
> > be better to use names like INSN2_* for flags that apply to pinfo2?
> > Less chance of using the wrong pinfo field accidentally.
>
> Seems like a good idea to me.
OK, here is a patch to do that. I'll apply it if it looks OK.
-Fred
Changes to include/opcode/ChangeLog
2005-01-21 Fred Fish <fnf@specifixinc.com>
* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
Changes to opcodes/ChangeLog:
2005-01-21 Fred Fish <fnf@specifixinc.com>
* mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
* mips-dis.c: Ditto.
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.40
diff -c -p -r1.40 mips.h
*** include/opcode/mips.h 19 Jan 2005 23:29:12 -0000 1.40
--- include/opcode/mips.h 21 Jan 2005 18:14:54 -0000
*************** struct mips_opcode
*** 383,393 ****
instruction. */
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
! #define INSN_ALIAS 0x00000001
/* Instruction reads MDMX accumulator. */
! #define INSN_READ_MDMX_ACC 0x00000002
/* Instruction writes MDMX accumulator. */
! #define INSN_WRITE_MDMX_ACC 0x00000004
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
--- 383,393 ----
instruction. */
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
! #define INSN2_ALIAS 0x00000001
/* Instruction reads MDMX accumulator. */
! #define INSN2_READ_MDMX_ACC 0x00000002
/* Instruction writes MDMX accumulator. */
! #define INSN2_WRITE_MDMX_ACC 0x00000004
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.47
diff -c -p -r1.47 mips-dis.c
*** opcodes/mips-dis.c 19 Jan 2005 23:31:15 -0000 1.47
--- opcodes/mips-dis.c 21 Jan 2005 18:14:55 -0000
*************** print_insn_mips (memaddr, word, info)
*** 1083,1089 ****
for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
{
if (op->pinfo == INSN_MACRO
! || (no_aliases && (op->pinfo2 & INSN_ALIAS)))
continue;
if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
{
--- 1083,1089 ----
for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
{
if (op->pinfo == INSN_MACRO
! || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
continue;
if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
{
*************** print_insn_mips (memaddr, word, info)
*** 1111,1117 ****
for (; op < &mips_opcodes[NUMOPCODES]; op++)
{
if (op->pinfo != INSN_MACRO
! && !(no_aliases && (op->pinfo2 & INSN_ALIAS))
&& (word & op->mask) == op->match)
{
register const char *d;
--- 1111,1117 ----
for (; op < &mips_opcodes[NUMOPCODES]; op++)
{
if (op->pinfo != INSN_MACRO
! && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
&& (word & op->mask) == op->match)
{
register const char *d;
*************** print_insn_mips16 (memaddr, info)
*** 1311,1317 ****
for (op = mips16_opcodes; op < opend; op++)
{
if (op->pinfo != INSN_MACRO
! && !(no_aliases && (op->pinfo2 & INSN_ALIAS))
&& (insn & op->mask) == op->match)
{
const char *s;
--- 1311,1317 ----
for (op = mips16_opcodes; op < opend; op++)
{
if (op->pinfo != INSN_MACRO
! && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
&& (insn & op->mask) == op->match)
{
const char *s;
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.48
diff -c -p -r1.48 mips-opc.c
*** opcodes/mips-opc.c 19 Jan 2005 23:31:15 -0000 1.48
--- opcodes/mips-opc.c 21 Jan 2005 18:14:55 -0000
*************** Software Foundation, 59 Temple Place - S
*** 76,83 ****
#define IS_M INSN_MULT
! #define WR_MACC INSN_WRITE_MDMX_ACC
! #define RD_MACC INSN_READ_MDMX_ACC
#define I1 INSN_ISA1
#define I2 INSN_ISA2
--- 76,83 ----
#define IS_M INSN_MULT
! #define WR_MACC INSN2_WRITE_MDMX_ACC
! #define RD_MACC INSN2_READ_MDMX_ACC
#define I1 INSN_ISA1
#define I2 INSN_ISA2
*************** const struct mips_opcode mips_builtin_op
*** 140,158 ****
/* name, args, match, mask, pinfo, pinfo2, membership */
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4 },
! {"nop", "", 0x00000000, 0xffffffff, 0, INSN_ALIAS, I1 }, /* sll */
! {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN_ALIAS, I32|N55 }, /* sll */
! {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN_ALIAS, I33 }, /* sll */
! {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN_ALIAS, I1 }, /* addiu */
! {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN_ALIAS, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
! {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN_ALIAS, I3 },/* daddu */
! {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN_ALIAS, I1 },/* addu */
! {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN_ALIAS, I1 },/* or */
! {"b", "p", 0x10000000, 0xffff0000, UBD, INSN_ALIAS, I1 },/* beq 0,0 */
! {"b", "p", 0x04010000, 0xffff0000, UBD, INSN_ALIAS, I1 },/* bgez 0 */
! {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN_ALIAS, I1 },/* bgezal 0*/
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
--- 140,158 ----
/* name, args, match, mask, pinfo, pinfo2, membership */
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4 },
! {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
! {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */
! {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */
! {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
! {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
! {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */
! {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */
! {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */
! {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */
! {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */
! {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },