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Address sizes on 64-bit MIPS targets
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: binutils at sources dot redhat dot com
- Date: Tue, 01 Mar 2005 20:08:49 +0000
- Subject: Address sizes on 64-bit MIPS targets
This patch paves the way for the -msym32 switch that was discussed
a while back. Its main purpose is to audit all existing uses of
HAVE_{32,64}BIT_ADDRESSES, and as a result, it tweaks the choice
between 32- and 64-bit address arithmetic, particularly in the
case of the o64/n32 linux hack. I hope it isn't too controversial...
First the problem. Suppose the following sequence is assembled with -n32:
dla $2,0xa8000000000000
lw $2,0x1000($2)
Thanks to the linux hack, the dla will load the full constant address
into $2 without complaint, so the sequence as a whole will load the
contents of address 0xa8000000001000 into $2. This is good.
Now consider:
li $2,0x100000
lw $2,0xa8000000000000($2)
Again because of the linux hack, the lw will compute the full 64-bit
sum of $2 and 0xa8000000000000 and will therefore load the contents
of address 0xa8000000100000 into $2. This too is good.
However, if the sequence is:
dla $2,0xa8000000000000
lw $2,0x100000($2)
then the lw will use 32-bit address arithmetic:
lui $1,0x10
addu $1,$1,$2
lw $2,0($1)
and the behaviour will be unpredictable. The existing dejagnu testcase
explicitly tests for this, so I assume it's deliberate, but it seems
pretty dangerous to me.
I suppose one justification for using "addu" might be that addresses
should stay within the 32-bit address space for n32 and o64, even if
the calculation overflows. But suppose we have a (non-macro) instruction
with a 16-bit offset:
lw $2,0x1000($2)
The behaviour of this instruction is unpredicatable for 32-bit address
spaces on 64-bit targets if $2 + 0x1000 overflows (for example, if
$2 == 0x7ffffff0). It doesn't seem very important to make it defined
for 32-bit offsets when it isn't defined for 16-bit offsets.
(FWIW, MIPSpro uses 64-bit arithmetic in all three cases.)
Another, more minor, problem is that the linux hack doesn't extend
to macros that use load_address(). E.g.:
uld $4,0xa8000000000001
will be rejected, even though:
ld $4,0xa8000000000000
works OK.
I'd like to change things so that:
- "dla"s with no symbolic component use 64-bit arithmetic
- "la"s with no symbolic component use 32-bit arithmetic
- "la"s and "dla"s with a symbolic component use 64-bit arithmetic
iff HAVE_64BIT_ADDRESSES (i.e. they use whatever the ABI dictates). [*]
- loads and stores with no symbolic component use 64-bit arithmetic
iff HAVE_64BIT_GPRS.
- loads and stores with a symbolic component use 64-bit arithmetic
iff HAVE_64BIT_ADDRESSES. [*]
[*] already true
The patch below implements this. There are a couple of other tweaks too:
- HAVE_32BIT_ADDRESSES contains a now-redundant check:
bfd_arch_bits_per_address (stdoutput) == 32
Since the arch is set from the command-line architecture, and since
we reject any attempt to use -mabi=64 with a 32-bit architecture,
all 32-bit-only archs are already covered by the !HAVE_64BIT_OBJECTS
check.
- macro_build_ldst_constoffset takes a "dbl" argument, but its
only effect is to decide whether a non-32bit offset gives
the error "constant too large" or "operand overflow".
At the moment, this function only handles 32-bit offsets
and is only used to implement saves and restores of $gp
for o32 & o64. All the callers pass HAVE_64BIT_ADDRESSES
as "dbl", so it will always be false anyway. The patch
simply removes this argument.
Tested on mips64{,el}-elf and mips64{,el}-linux-gnu. Also tested by
building linux with explicit relocs disabled and with (a variant of)
the !CONFIG_BUILD_ELF64 option. OK to install?
Richard
gas/
* config/tc-mips.c (HAVE_32BIT_ADDRESSES): Remove stdoutput check.
(macro_build_ldst_constoffset): Remove DBL parameter.
(load_address): Use HAVE_64BIT_GPRS rather than HAVE_64BIT_ADDRESSES
when deciding whether to use 64-bit arithmetic for constant addresses.
(macro): Likewise in the handling of "ld_st:". Always use 64-bit
arithmetic for dla if no relocations are involved. Adjust calls
to macro_build_ldst_constoffset.
(s_cprestore): Adjust further call here.
gas/testsuite/
* gas/mips/ldstla-n32.s: Add tests for uld.
* gas/mips/ldstla-n32.d, gas/mips/ldstla-n32-shared.d: Adjust
accordingly. Expect address arithmetic involving 32-bit constants
to use daddu rather than addu.
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.287
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.287 tc-mips.c
--- gas/config/tc-mips.c 23 Feb 2005 12:28:04 -0000 1.287
+++ gas/config/tc-mips.c 28 Feb 2005 21:31:40 -0000
@@ -287,11 +287,7 @@ #define HAVE_64BIT_OBJECTS (mips_abi ==
#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
/* We can only have 64bit addresses if the object file format supports it. */
-#define HAVE_32BIT_ADDRESSES \
- (HAVE_32BIT_GPRS \
- || (bfd_arch_bits_per_address (stdoutput) == 32 \
- || ! HAVE_64BIT_OBJECTS)) \
-
+#define HAVE_32BIT_ADDRESSES (HAVE_32BIT_GPRS || ! HAVE_64BIT_OBJECTS)
#define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
/* Addresses are loaded in different ways, depending on the address size
@@ -3415,16 +3411,17 @@ macro_build_lui (expressionS *ep, int re
/* Generate a sequence of instructions to do a load or store from a constant
offset off of a base register (breg) into/from a target register (treg),
- using AT if necessary. */
+ using AT if necessary. This function only works for 32-bit offsets
+ at present. */
+
static void
macro_build_ldst_constoffset (expressionS *ep, const char *op,
- int treg, int breg, int dbl)
+ int treg, int breg)
{
assert (ep->X_op == O_constant);
/* Sign-extending 32-bit constants makes their handling easier. */
- if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
- == ~((bfd_vma) 0x7fffffff)))
+ if ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) != ~((bfd_vma) 0x7fffffff))
{
if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
as_bad (_("constant too large"));
@@ -3433,7 +3430,6 @@ macro_build_ldst_constoffset (expression
- 0x80000000);
}
- /* Right now, this routine can only handle signed 32-bit constants. */
if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
as_warn (_("operand overflow"));
@@ -3832,7 +3828,7 @@ load_address (int reg, expressionS *ep,
if (ep->X_op == O_constant)
{
- load_register (reg, ep, HAVE_64BIT_ADDRESSES);
+ load_register (reg, ep, HAVE_64BIT_GPRS);
return;
}
@@ -4908,12 +4904,19 @@ macro (struct mips_cl_insn *ip)
if (! dbl && HAVE_64BIT_OBJECTS)
as_warn (_("la used to load 64-bit address"));
+ /* If we need to use relocations to calculate the address,
+ the size of the result is dictated by the ABI. Note that we
+ allow "dla" to be used to load a 32-bit symbolic address into
+ a 64-bit register, so changing the value of DBL does not
+ always need a warning. */
+ if (offset_expr.X_op != O_constant)
+ dbl = HAVE_64BIT_ADDRESSES;
+
if (offset_expr.X_op == O_constant
&& offset_expr.X_add_number >= -0x8000
&& offset_expr.X_add_number < 0x8000)
{
- macro_build (&offset_expr,
- (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
+ macro_build (&offset_expr, dbl ? "daddiu" : "addiu",
"t,r,j", treg, sreg, BFD_RELOC_LO16);
break;
}
@@ -4936,10 +4939,7 @@ macro (struct mips_cl_insn *ip)
}
if (offset_expr.X_op == O_constant)
- load_register (tempreg, &offset_expr,
- (mips_pic == NO_PIC
- ? (dbl || HAVE_64BIT_ADDRESSES)
- : HAVE_64BIT_ADDRESSES));
+ load_register (tempreg, &offset_expr, dbl);
else if (mips_pic == NO_PIC)
{
/* If this is a reference to a GP relative symbol, we want
@@ -5484,16 +5484,8 @@ macro (struct mips_cl_insn *ip)
abort ();
if (breg != 0)
- {
- char *s;
-
- if (mips_pic == NO_PIC)
- s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
- else
- s = ADDRESS_ADD_INSN;
-
- macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
- }
+ macro_build (NULL, dbl ? "daddu" : "addu", "d,v,t",
+ treg, tempreg, breg);
break;
case M_J_A:
@@ -5542,8 +5534,7 @@ macro (struct mips_cl_insn *ip)
expr1.X_add_number = mips_cprestore_offset;
macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
mips_gp_register,
- mips_frame_reg,
- HAVE_64BIT_ADDRESSES);
+ mips_frame_reg);
}
}
}
@@ -5679,8 +5670,7 @@ macro (struct mips_cl_insn *ip)
expr1.X_add_number = mips_cprestore_offset;
macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
mips_gp_register,
- mips_frame_reg,
- HAVE_64BIT_ADDRESSES);
+ mips_frame_reg);
}
}
}
@@ -5862,12 +5852,17 @@ macro (struct mips_cl_insn *ip)
else
fmt = "t,o(b)";
- /* Sign-extending 32-bit constants makes their handling easier.
- The HAVE_64BIT_GPRS... part is due to the linux kernel hack
- described below. */
- if ((! HAVE_64BIT_ADDRESSES
- && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
- && (offset_expr.X_op == O_constant)
+ /* Set DBL to true if we should use 64-bit arithmetic to calculate
+ the address. The size of relocatable addresses depends on the
+ ABI. */
+ if (offset_expr.X_op == O_constant)
+ dbl = HAVE_64BIT_GPRS;
+ else
+ dbl = HAVE_64BIT_ADDRESSES;
+
+ /* Sign-extending 32-bit constants makes their handling easier. */
+ if (! dbl
+ && offset_expr.X_op == O_constant
&& ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
== ~((bfd_vma) 0x7fffffff)))
{
@@ -5950,30 +5945,10 @@ macro (struct mips_cl_insn *ip)
the signed offset used by memory operations, the 32-bit
range is shifted down by 32768 here. This code should
probably attempt to generate 64-bit constants more
- efficiently in general.
-
- As an extension for architectures with 64-bit registers,
- we don't truncate 64-bit addresses given as literal
- constants down to 32 bits, to support existing practice
- in the mips64 Linux (the kernel), that compiles source
- files with -mabi=64, assembling them as o32 or n32 (with
- -Wa,-32 or -Wa,-n32). This is not beautiful, but since
- the whole kernel is loaded into a memory region that is
- addressable with sign-extended 32-bit addresses, it is
- wasteful to compute the upper 32 bits of every
- non-literal address, that takes more space and time.
- Some day this should probably be implemented as an
- assembler option, such that the kernel doesn't have to
- use such ugly hacks, even though it will still have to
- end up converting the binary to ELF32 for a number of
- platforms whose boot loaders don't support ELF64
- binaries. */
- if ((HAVE_64BIT_ADDRESSES
- && ! (offset_expr.X_op == O_constant
- && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
- || (HAVE_64BIT_GPRS
- && offset_expr.X_op == O_constant
- && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
+ efficiently in general. */
+ if (dbl
+ && ! (offset_expr.X_op == O_constant
+ && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
{
/* ??? We don't provide a GP-relative alternative for
these macros. It used not to be possible with the
@@ -6047,7 +6022,7 @@ macro (struct mips_cl_insn *ip)
relax_switch ();
}
macro_build_lui (&offset_expr, tempreg);
- macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, dbl ? "daddu" : "addu", "d,v,t",
tempreg, tempreg, breg);
macro_build (&offset_expr, s, fmt, treg,
BFD_RELOC_LO16, tempreg);
@@ -12000,8 +11975,7 @@ s_cprestore (int ignore ATTRIBUTE_UNUSED
ex.X_add_number = mips_cprestore_offset;
macro_start ();
- macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
- SP, HAVE_64BIT_ADDRESSES);
+ macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, SP);
macro_end ();
demand_empty_rest_of_line ();
Index: gas/testsuite/gas/mips/ldstla-n32.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/ldstla-n32.d,v
retrieving revision 1.1
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.1 ldstla-n32.d
--- gas/testsuite/gas/mips/ldstla-n32.d 1 Oct 2003 02:07:48 -0000 1.1
+++ gas/testsuite/gas/mips/ldstla-n32.d 28 Feb 2005 21:31:40 -0000
@@ -23,7 +23,7 @@ 00000000 <\.text>:
30: 0041102d daddu v0,v0,at
34: dc426789 ld v0,26505\(v0\)
38: 3c028000 lui v0,0x8000
- 3c: 00431021 addu v0,v0,v1
+ 3c: 0043102d daddu v0,v0,v1
40: dc420000 ld v0,0\(v0\)
44: 3c020000 lui v0,0x0
48: 3c010000 lui at,0x0
@@ -40,7 +40,7 @@ 00000000 <\.text>:
74: 0041102d daddu v0,v0,at
78: dc42ef01 ld v0,-4351\(v0\)
7c: 3c020123 lui v0,0x123
- 80: 00431021 addu v0,v0,v1
+ 80: 0043102d daddu v0,v0,v1
84: dc424567 ld v0,17767\(v0\)
88: 3c010123 lui at,0x123
8c: 64214568 daddiu at,at,17768
@@ -57,7 +57,7 @@ 00000000 <\.text>:
b8: 0023082d daddu at,at,v1
bc: fc226789 sd v0,26505\(at\)
c0: 3c018000 lui at,0x8000
- c4: 00230821 addu at,at,v1
+ c4: 0023082d daddu at,at,v1
c8: fc220000 sd v0,0\(at\)
cc: 3c010000 lui at,0x0
d0: 6421ffff daddiu at,at,-1
@@ -74,7 +74,7 @@ 00000000 <\.text>:
fc: 0023082d daddu at,at,v1
100: fc22ef01 sd v0,-4351\(at\)
104: 3c010123 lui at,0x123
- 108: 00230821 addu at,at,v1
+ 108: 0023082d daddu at,at,v1
10c: fc224567 sd v0,17767\(at\)
110: 3c020123 lui v0,0x123
114: 3c0189ac lui at,0x89ac
@@ -91,7 +91,7 @@ 00000000 <\.text>:
140: 0041102d daddu v0,v0,at
144: 8c426789 lw v0,26505\(v0\)
148: 3c028000 lui v0,0x8000
- 14c: 00431021 addu v0,v0,v1
+ 14c: 0043102d daddu v0,v0,v1
150: 8c420000 lw v0,0\(v0\)
154: 3c020000 lui v0,0x0
158: 3c010000 lui at,0x0
@@ -108,7 +108,7 @@ 00000000 <\.text>:
184: 0041102d daddu v0,v0,at
188: 8c42ef01 lw v0,-4351\(v0\)
18c: 3c020123 lui v0,0x123
- 190: 00431021 addu v0,v0,v1
+ 190: 0043102d daddu v0,v0,v1
194: 8c424567 lw v0,17767\(v0\)
198: 3c010123 lui at,0x123
19c: 64214568 daddiu at,at,17768
@@ -125,7 +125,7 @@ 00000000 <\.text>:
1c8: 0023082d daddu at,at,v1
1cc: ac226789 sw v0,26505\(at\)
1d0: 3c018000 lui at,0x8000
- 1d4: 00230821 addu at,at,v1
+ 1d4: 0023082d daddu at,at,v1
1d8: ac220000 sw v0,0\(at\)
1dc: 3c010000 lui at,0x0
1e0: 6421ffff daddiu at,at,-1
@@ -142,7 +142,7 @@ 00000000 <\.text>:
20c: 0023082d daddu at,at,v1
210: ac22ef01 sw v0,-4351\(at\)
214: 3c010123 lui at,0x123
- 218: 00230821 addu at,at,v1
+ 218: 0023082d daddu at,at,v1
21c: ac224567 sw v0,17767\(at\)
220: 3c028000 lui v0,0x8000
224: 3c020123 lui v0,0x123
@@ -151,4 +151,42 @@ 00000000 <\.text>:
230: 3442ffff ori v0,v0,0xffff
234: 3c020123 lui v0,0x123
238: 34424567 ori v0,v0,0x4567
+ 23c: 3c010123 lui at,0x123
+ 240: 34214567 ori at,at,0x4567
+ 244: 00010c38 dsll at,at,0x10
+ 248: 342189ab ori at,at,0x89ab
+ 24c: 00010c38 dsll at,at,0x10
+ 250: 3421cdef ori at,at,0xcdef
+ 254: 00230821 addu at,at,v1
+ 258: 68220007 ldl v0,7\(at\)
+ 25c: 6c220000 ldr v0,0\(at\)
+ 260: 3c01abcd lui at,0xabcd
+ 264: 3421ef01 ori at,at,0xef01
+ 268: 00010c38 dsll at,at,0x10
+ 26c: 34212345 ori at,at,0x2345
+ 270: 00010c38 dsll at,at,0x10
+ 274: 34216789 ori at,at,0x6789
+ 278: 00230821 addu at,at,v1
+ 27c: 68220007 ldl v0,7\(at\)
+ 280: 6c220000 ldr v0,0\(at\)
+ 284: 3c018000 lui at,0x8000
+ 288: 00230821 addu at,at,v1
+ 28c: 68220007 ldl v0,7\(at\)
+ 290: 6c220000 ldr v0,0\(at\)
+ 294: 2401ffff li at,-1
+ 298: 0001083c dsll32 at,at,0x0
+ 29c: 00230821 addu at,at,v1
+ 2a0: 68220007 ldl v0,7\(at\)
+ 2a4: 6c220000 ldr v0,0\(at\)
+ 2a8: 3401abcd li at,0xabcd
+ 2ac: 00010c38 dsll at,at,0x10
+ 2b0: 3421ef01 ori at,at,0xef01
+ 2b4: 00230821 addu at,at,v1
+ 2b8: 68220007 ldl v0,7\(at\)
+ 2bc: 6c220000 ldr v0,0\(at\)
+ 2c0: 3c010123 lui at,0x123
+ 2c4: 34214567 ori at,at,0x4567
+ 2c8: 00230821 addu at,at,v1
+ 2cc: 68220007 ldl v0,7\(at\)
+ 2d0: 6c220000 ldr v0,0\(at\)
\.\.\.
Index: gas/testsuite/gas/mips/ldstla-n32.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/ldstla-n32.s,v
retrieving revision 1.1
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.1 ldstla-n32.s
--- gas/testsuite/gas/mips/ldstla-n32.s 1 Oct 2003 02:07:48 -0000 1.1
+++ gas/testsuite/gas/mips/ldstla-n32.s 28 Feb 2005 21:31:40 -0000
@@ -32,4 +32,11 @@
la $2, 0x7fffffff
la $2, 0x01234567
+ uld $2, 0x0123456789abcdef($3)
+ uld $2, 0xabcdef0123456789($3)
+ uld $2, 0xffffffff80000000($3)
+ uld $2, 0xffffffff00000000($3)
+ uld $2, 0xabcdef01($3)
+ uld $2, 0x01234567($3)
+
.space 8
Index: gas/testsuite/gas/mips/ldstla-n32-shared.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/ldstla-n32-shared.d,v
retrieving revision 1.1
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.1 ldstla-n32-shared.d
--- gas/testsuite/gas/mips/ldstla-n32-shared.d 1 Oct 2003 02:07:48 -0000 1.1
+++ gas/testsuite/gas/mips/ldstla-n32-shared.d 28 Feb 2005 21:31:40 -0000
@@ -23,7 +23,7 @@ 00000000 <\.text>:
30: 0041102d daddu v0,v0,at
34: dc426789 ld v0,26505\(v0\)
38: 3c028000 lui v0,0x8000
- 3c: 00431021 addu v0,v0,v1
+ 3c: 0043102d daddu v0,v0,v1
40: dc420000 ld v0,0\(v0\)
44: 3c020000 lui v0,0x0
48: 3c010000 lui at,0x0
@@ -40,7 +40,7 @@ 00000000 <\.text>:
74: 0041102d daddu v0,v0,at
78: dc42ef01 ld v0,-4351\(v0\)
7c: 3c020123 lui v0,0x123
- 80: 00431021 addu v0,v0,v1
+ 80: 0043102d daddu v0,v0,v1
84: dc424567 ld v0,17767\(v0\)
88: 3c010123 lui at,0x123
8c: 64214568 daddiu at,at,17768
@@ -57,7 +57,7 @@ 00000000 <\.text>:
b8: 0023082d daddu at,at,v1
bc: fc226789 sd v0,26505\(at\)
c0: 3c018000 lui at,0x8000
- c4: 00230821 addu at,at,v1
+ c4: 0023082d daddu at,at,v1
c8: fc220000 sd v0,0\(at\)
cc: 3c010000 lui at,0x0
d0: 6421ffff daddiu at,at,-1
@@ -74,7 +74,7 @@ 00000000 <\.text>:
fc: 0023082d daddu at,at,v1
100: fc22ef01 sd v0,-4351\(at\)
104: 3c010123 lui at,0x123
- 108: 00230821 addu at,at,v1
+ 108: 0023082d daddu at,at,v1
10c: fc224567 sd v0,17767\(at\)
110: 3c020123 lui v0,0x123
114: 3c0189ac lui at,0x89ac
@@ -91,7 +91,7 @@ 00000000 <\.text>:
140: 0041102d daddu v0,v0,at
144: 8c426789 lw v0,26505\(v0\)
148: 3c028000 lui v0,0x8000
- 14c: 00431021 addu v0,v0,v1
+ 14c: 0043102d daddu v0,v0,v1
150: 8c420000 lw v0,0\(v0\)
154: 3c020000 lui v0,0x0
158: 3c010000 lui at,0x0
@@ -108,7 +108,7 @@ 00000000 <\.text>:
184: 0041102d daddu v0,v0,at
188: 8c42ef01 lw v0,-4351\(v0\)
18c: 3c020123 lui v0,0x123
- 190: 00431021 addu v0,v0,v1
+ 190: 0043102d daddu v0,v0,v1
194: 8c424567 lw v0,17767\(v0\)
198: 3c010123 lui at,0x123
19c: 64214568 daddiu at,at,17768
@@ -125,7 +125,7 @@ 00000000 <\.text>:
1c8: 0023082d daddu at,at,v1
1cc: ac226789 sw v0,26505\(at\)
1d0: 3c018000 lui at,0x8000
- 1d4: 00230821 addu at,at,v1
+ 1d4: 0023082d daddu at,at,v1
1d8: ac220000 sw v0,0\(at\)
1dc: 3c010000 lui at,0x0
1e0: 6421ffff daddiu at,at,-1
@@ -142,7 +142,7 @@ 00000000 <\.text>:
20c: 0023082d daddu at,at,v1
210: ac22ef01 sw v0,-4351\(at\)
214: 3c010123 lui at,0x123
- 218: 00230821 addu at,at,v1
+ 218: 0023082d daddu at,at,v1
21c: ac224567 sw v0,17767\(at\)
220: 3c028000 lui v0,0x8000
224: 3c020123 lui v0,0x123
@@ -151,4 +151,42 @@ 00000000 <\.text>:
230: 3442ffff ori v0,v0,0xffff
234: 3c020123 lui v0,0x123
238: 34424567 ori v0,v0,0x4567
+ 23c: 3c010123 lui at,0x123
+ 240: 34214567 ori at,at,0x4567
+ 244: 00010c38 dsll at,at,0x10
+ 248: 342189ab ori at,at,0x89ab
+ 24c: 00010c38 dsll at,at,0x10
+ 250: 3421cdef ori at,at,0xcdef
+ 254: 00230821 addu at,at,v1
+ 258: 68220007 ldl v0,7\(at\)
+ 25c: 6c220000 ldr v0,0\(at\)
+ 260: 3c01abcd lui at,0xabcd
+ 264: 3421ef01 ori at,at,0xef01
+ 268: 00010c38 dsll at,at,0x10
+ 26c: 34212345 ori at,at,0x2345
+ 270: 00010c38 dsll at,at,0x10
+ 274: 34216789 ori at,at,0x6789
+ 278: 00230821 addu at,at,v1
+ 27c: 68220007 ldl v0,7\(at\)
+ 280: 6c220000 ldr v0,0\(at\)
+ 284: 3c018000 lui at,0x8000
+ 288: 00230821 addu at,at,v1
+ 28c: 68220007 ldl v0,7\(at\)
+ 290: 6c220000 ldr v0,0\(at\)
+ 294: 2401ffff li at,-1
+ 298: 0001083c dsll32 at,at,0x0
+ 29c: 00230821 addu at,at,v1
+ 2a0: 68220007 ldl v0,7\(at\)
+ 2a4: 6c220000 ldr v0,0\(at\)
+ 2a8: 3401abcd li at,0xabcd
+ 2ac: 00010c38 dsll at,at,0x10
+ 2b0: 3421ef01 ori at,at,0xef01
+ 2b4: 00230821 addu at,at,v1
+ 2b8: 68220007 ldl v0,7\(at\)
+ 2bc: 6c220000 ldr v0,0\(at\)
+ 2c0: 3c010123 lui at,0x123
+ 2c4: 34214567 ori at,at,0x4567
+ 2c8: 00230821 addu at,at,v1
+ 2cc: 68220007 ldl v0,7\(at\)
+ 2d0: 6c220000 ldr v0,0\(at\)
\.\.\.