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Thumb32 assembler (51/69)
- From: Zack Weinberg <zack at codesourcery dot com>
- To: binutils <binutils at sourceware dot org>
- Date: Tue, 26 Apr 2005 02:57:15 -0700
- Subject: Thumb32 assembler (51/69)
I promised back in patch #17 that the horrible OP_ and OPS_ macros
would go away; it is now possible to eliminate them, because we no
longer need the OPERANDSn macros to expand to string constants. The
OP_* codes can now be an enum instead of a lot of #defines (in octal,
even!), too. Nor do the OPERANDSn macros need to be visible anywhere
but in insns and tinsns. I also adjusted some of the operand parse
codes' names, to make them more consistent, and removed one that was
unused.
* config/tc-arm.c (struct asm_opcode): Make operands an array of
unsigned char.
(operand parse codes): Make into an enum; remove explicit values for
most constants; rename some constants for clarity; remove unused I0.
(OP_, OP__, OP___, OPS_, OPS__, OPS___): Delete.
(OPERANDS0, OPERANDS1, OPERANDS2, OPERANDS3, OPERANDS4)
(OPERANDS5, OPERANDS6): Rename OPS0-6 respectively. Limit visibility
to insns and tinsns tables. Adjust expansions.
(parse_operands, insns, tinsns, CE, CM, UE, UF, TI): Update to match.
===================================================================
Index: gas/config/tc-arm.c
--- gas/config/tc-arm.c (revision 53)
+++ gas/config/tc-arm.c (revision 54)
@@ -362,7 +362,7 @@
unsigned long variant;
/* Parameters to instruction. */
- const char *operands;
+ unsigned char operands[8];
/* Function to call to encode instruction. */
void (* encode) (void);
@@ -3748,113 +3748,88 @@
{ 0, 0, 0 }
};
-/* Matcher codes for operand_parse. These are in octal, because of
- the macros below. Never refer to these constants except via the
- macros below. */
+/* Matcher codes for operand_parse. */
+enum operand_parse_code
+{
+ OP_stop, /* end of line */
-#define OP_stop 000 /* end of line */
+ OP_RR, /* ARM register */
+ OP_RRnpc, /* ARM register, not r15 */
+ OP_RRnpcb, /* ARM register, not r15, in square brackets */
+ OP_RRw, /* ARM register, not r15, optional trailing ! */
+ OP_RL, /* Thumb low register */
+ OP_RLw, /* Thumb low register, optional trailing ! */
+ OP_RCP, /* Coprocessor number */
+ OP_RCN, /* Coprocessor register */
+ OP_RF, /* FPA register */
+ OP_RVS, /* VFP single precision register */
+ OP_RVD, /* VFP double precision register */
+ OP_RVC, /* VFP control register */
+ OP_RMF, /* Maverick F register */
+ OP_RMD, /* Maverick D register */
+ OP_RMFX, /* Maverick FX register */
+ OP_RMDX, /* Maverick DX register */
+ OP_RMAX, /* Maverick AX register */
+ OP_RMDS, /* Maverick DSPSC register */
+ OP_RIWR, /* iWMMXt wR register */
+ OP_RIWC, /* iWMMXt wC register */
+ OP_RIWG, /* iWMMXt wCG register */
+ OP_RXA, /* XScale accumulator register */
-#define OP_RR 001 /* ARM register */
-#define OP_RRnpc 002 /* ARM register, not r15 */
-#define OP_bRRnpc 003 /* ARM register, not r15, in square brackets */
-#define OP_RCP 004 /* Coprocessor number */
-#define OP_RCN 005 /* Coprocessor register */
-#define OP_RF 006 /* FPA register */
-#define OP_RVS 007 /* VFP single precision register */
-#define OP_RVD 010 /* VFP double precision register */
-#define OP_RVC 011 /* VFP control register */
-#define OP_RMF 012 /* Maverick F register */
-#define OP_RMD 013 /* Maverick D register */
-#define OP_RMFX 014 /* Maverick FX register */
-#define OP_RMDX 015 /* Maverick DX register */
-#define OP_RMAX 016 /* Maverick AX register */
-#define OP_RMDS 017 /* Maverick DSPSC register */
-#define OP_RIWR 020 /* iWMMXt wR register */
-#define OP_RIWC 021 /* iWMMXt wC register */
-#define OP_RIWG 022 /* iWMMXt wCG register */
-#define OP_RXA 023 /* XScale accumulator register */
+ OP_REGLST, /* ARM register list */
+ OP_VRSLST, /* VFP single-precision register list */
+ OP_VRDLST, /* VFP double-precision register list */
-#define OP_EXP 024 /* arbitrary expression */
-#define OP_iEXP 025 /* same, with optional immediate prefix */
-#define OP_EXPr 026 /* same, with optional relocation suffix */
+ OP_I7, /* immediate value 0 .. 7 */
+ OP_I15, /* 0 .. 15 */
+ OP_I16, /* 1 .. 16 */
+ OP_I31, /* 0 .. 31 */
+ OP_I31w, /* 0 .. 31, optional trailing ! */
+ OP_I32, /* 1 .. 32 */
+ OP_I63s, /* -64 .. 63 */
+ OP_I255, /* 0 .. 255 */
+ OP_Iffff, /* 0 .. 65535 */
-#define OP_I0 027 /* immediate value 0 */
-#define OP_I7 031 /* 0 .. 7 */
-#define OP_I15 032 /* 0 .. 15 */
-#define OP_I16 033 /* 1 .. 16 */
-#define OP_I31 034 /* 0 .. 31 */
-#define OP_I32 035 /* 1 .. 32 */
-#define OP_Is63 036 /* -64 .. 63 */
-#define OP_I255 037 /* 0 .. 255 */
-#define OP_Iffff 040 /* 0 .. 65535 */
+ OP_I4b, /* immediate, prefix optional, 1 .. 4 */
+ OP_I7b, /* 0 .. 7 */
+ OP_I15b, /* 0 .. 15 */
+ OP_I31b, /* 0 .. 31 */
-#define OP_bI7 041 /* immediate, prefix optional, 0 .. 7 */
-#define OP_bI15 042 /* 0 .. 15 */
-#define OP_bI31 043 /* 0 .. 31 */
-#define OP_bI4 030 /* 1 .. 4 */
+ OP_SH, /* shifter operand */
+ OP_ADDR, /* Memory address expression (any mode) */
+ OP_EXP, /* arbitrary expression */
+ OP_EXPi, /* same, with optional immediate prefix */
+ OP_EXPr, /* same, with optional relocation suffix */
-#define OP_I31w 050 /* 0 .. 31, optional trailing ! */
-#define OP_RRw 051 /* ARM register, not the PC, optional trailing ! */
+ OP_CPSF, /* CPS flags */
+ OP_ENDI, /* Endianness specifier */
+ OP_PSR, /* CPSR/SPSR mask for msr */
-#define OP_RL 052 /* Thumb low register */
-#define OP_RLw 055 /* Thumb low register, optional trailing ! */
+ OP_RR_EX, /* ARM register or expression */
+ OP_RL_EXi, /* Thumb low register or expression with imm prefix */
+ OP_RRnpc_I0, /* ARM register or literal 0 */
+ OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
+ OP_RR_EXi, /* ARM register or expression with imm prefix */
+ OP_RF_IF, /* FPA register or immediate */
+ OP_RIWR_RIWC, /* iWMMXt R or C reg */
-#define OP_CPSF 060 /* CPS flags */
-#define OP_ENDI 061 /* Endianness specifier */
-#define OP_PSR 062 /* CPSR/SPSR mask for msr */
-#define OP_REGLST 063 /* ARM register list */
-#define OP_VRSLST 064 /* VFP single-precision register list */
-#define OP_VRDLST 065 /* VFP double-precision register list */
+ /* Optional operands. All have the high bit set. */
+ OP_oI7b = 128, /* immediate, prefix optional, 0 .. 7 */
+ OP_oI31b, /* 0 .. 31 */
+ OP_oI255b, /* 0 .. 255 */
+ OP_oIffffb, /* 0 .. 65535 */
+ OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
-#define OP_ADDR 072 /* Memory address expression (any mode) */
-#define OP_SHOP 073 /* shifter_operand */
+ OP_oRL, /* Thumb low register */
+ OP_oRL_EXi, /* Thumb low register or expression */
+ OP_oRR_EXi, /* ARM register or expression */
-/* This-or-that operands. All have bit 7 set. */
-#define OP_RR_EX 100 /* ARM register or expression */
-#define OP_RL_iEX 101 /* Thumb low register or expression with imm prefix */
-#define OP_RRnpc_I0 102 /* ARM register or literal 0 */
-#define OP_RR_EXr 103 /* ARM register or expression with opt. reloc suff. */
-#define OP_RR_iEX 104 /* ARM register or expression with imm prefix */
-#define OP_RF_IF 105 /* FPA register or immediate */
-#define OP_RIWR_RIWC 106 /* iWMMXt R or C reg */
+ OP_oSHll, /* LSL immediate */
+ OP_oSHar, /* ASR immediate */
+ OP_oSHllar, /* LSL or ASR immediate */
+ OP_oROR /* ROR 0/8/16/24 */
+};
-/* Optional operands. All have the high bit set. */
-#define OP_obI7 200 /* optional, prefix optional, immediate 0 .. 7 */
-#define OP_obI31 201 /* 0 .. 31 */
-#define OP_obI255 202 /* 0 .. 255 */
-#define OP_obIffff 203 /* 0 .. 65535 */
-#define OP_ocI255 204 /* optional, curly-brace enclosed, imm 0 .. 255 */
-
-#define OP_oROR 210 /* optional rotate right 0/8/16/24 */
-#define OP_oRL 211 /* optional Thumb low register */
-#define OP_oSHll 212 /* bare LSL immediate */
-#define OP_oSHar 213 /* bare ASR immediate */
-#define OP_oSHllar 214 /* bare LSL or ASR immediate */
-
-#define OP_oRL_iEX 300 /* optional Thumb low reg or expression */
-#define OP_oRR_iEX 301 /* optional ARM reg or expression */
-
-/* Macro for referring to one of the above constants as a number.
- Should appear solely in parse_operands(). */
-#define OP_(x) OP__(OP_##x)
-#define OP__(x) OP___(x)
-#define OP___(x) 0##x
-
-/* Macro for referring to one of the above constants as a 1-character
- string. Used by OPERANDSn(). */
-#define OPS_(x) OPS__(\OP_##x)
-#define OPS__(x) OPS___(x)
-#define OPS___(x) #x
-
-/* Macros for gluing together operand strings. */
-#define OPERANDS0() ""
-#define OPERANDS1(a) OPS_(a)
-#define OPERANDS2(a,b) OPS_(a) OPS_(b)
-#define OPERANDS3(a,b,c) OPS_(a) OPS_(b) OPS_(c)
-#define OPERANDS4(a,b,c,d) OPS_(a) OPS_(b) OPS_(c) OPS_(d)
-#define OPERANDS5(a,b,c,d,e) OPS_(a) OPS_(b) OPS_(c) OPS_(d) OPS_(e)
-#define OPERANDS6(a,b,c,d,e,f) OPS_(a) OPS_(b) OPS_(c) OPS_(d) OPS_(e) OPS_(f)
-
/* Generic instruction operand parser. This does no encoding and no
semantic validation; it merely squirrels values away in the inst
structure. Returns SUCCESS or FAIL depending on whether the
@@ -3901,7 +3876,7 @@
/* Check for a no-operand instruction, or an instruction with only
optional operands given none, and bypass the loop if so. */
- if (*p == OP_(stop) || ((*p & 0200) && *str == 0))
+ if (*p == OP_stop || ((*p & 0200) && *str == 0))
goto done;
for (i = 0; ; i++)
@@ -3909,72 +3884,67 @@
switch (*p)
{
/* Registers */
- case OP_(RRnpc):
- case OP_(oRL):
- case OP_(RL):
- case OP_(RR): po_reg_or_fail (REG_TYPE_RN); break;
- case OP_(RCP): po_reg_or_fail (REG_TYPE_CP); break;
- case OP_(RCN): po_reg_or_fail (REG_TYPE_CN); break;
- case OP_(RF): po_reg_or_fail (REG_TYPE_FN); break;
- case OP_(RVS): po_reg_or_fail (REG_TYPE_VFS); break;
- case OP_(RVD): po_reg_or_fail (REG_TYPE_VFD); break;
- case OP_(RVC): po_reg_or_fail (REG_TYPE_VFC); break;
- case OP_(RMF): po_reg_or_fail (REG_TYPE_MVF); break;
- case OP_(RMD): po_reg_or_fail (REG_TYPE_MVD); break;
- case OP_(RMFX): po_reg_or_fail (REG_TYPE_MVFX); break;
- case OP_(RMDX): po_reg_or_fail (REG_TYPE_MVDX); break;
- case OP_(RMAX): po_reg_or_fail (REG_TYPE_MVAX); break;
- case OP_(RMDS): po_reg_or_fail (REG_TYPE_DSPSC); break;
- case OP_(RIWR): po_reg_or_fail (REG_TYPE_MMXWR); break;
- case OP_(RIWC): po_reg_or_fail (REG_TYPE_MMXWC); break;
- case OP_(RIWG): po_reg_or_fail (REG_TYPE_MMXWCG); break;
- case OP_(RXA): po_reg_or_fail (REG_TYPE_XSCALE); break;
+ case OP_RRnpc:
+ case OP_oRL:
+ case OP_RL:
+ case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
+ case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
+ case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
+ case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
+ case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
+ case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
+ case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
+ case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
+ case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
+ case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
+ case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
+ case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
+ case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
+ case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
+ case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
+ case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
+ case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
- case OP_(bRRnpc):
+ case OP_RRnpcb:
po_char_or_fail ('[');
po_reg_or_fail (REG_TYPE_RN);
po_char_or_fail (']');
break;
- case OP_(RLw):
- case OP_(RRw):
+ case OP_RLw:
+ case OP_RRw:
po_reg_or_fail (REG_TYPE_RN);
- if (*str == '!')
- {
- inst.operands[i].writeback = 1;
- str++;
- }
+ if (skip_past_char (&str, '!') == SUCCESS)
+ inst.operands[i].writeback = 1;
break;
/* Immediates */
- I0:
- case OP_(I0): po_imm_or_fail ( 0, 0, FALSE); break;
- case OP_(I7): po_imm_or_fail ( 0, 7, FALSE); break;
- case OP_(I15): po_imm_or_fail ( 0, 15, FALSE); break;
- case OP_(I16): po_imm_or_fail ( 1, 16, FALSE); break;
- case OP_(I31): po_imm_or_fail ( 0, 31, FALSE); break;
- case OP_(I32): po_imm_or_fail ( 1, 32, FALSE); break;
- case OP_(Is63): po_imm_or_fail (-64, 63, FALSE); break;
- case OP_(I255): po_imm_or_fail ( 0, 255, FALSE); break;
- case OP_(Iffff): po_imm_or_fail ( 0, 0xffff, FALSE); break;
+ case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
+ case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
+ case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
+ case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
+ case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
+ case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
+ case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
+ case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
- case OP_(bI4): po_imm_or_fail ( 1, 4, TRUE); break;
- case OP_(obI7):
- case OP_(bI7): po_imm_or_fail ( 0, 7, TRUE); break;
- case OP_(bI15): po_imm_or_fail ( 0, 15, TRUE); break;
- case OP_(obI31):
- case OP_(bI31): po_imm_or_fail ( 0, 31, TRUE); break;
- case OP_(obI255): po_imm_or_fail ( 0, 255, TRUE); break;
- case OP_(obIffff): po_imm_or_fail (0, 0xffff, TRUE); break;
+ case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
+ case OP_oI7b:
+ case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
+ case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
+ case OP_oI31b:
+ case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
+ case OP_oI255b: po_imm_or_fail ( 0, 255, TRUE); break;
+ case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
/* Immediate variants */
- case OP_(ocI255):
+ case OP_oI255c:
po_char_or_fail ('{');
po_imm_or_fail (0, 255, TRUE);
po_char_or_fail ('}');
break;
- case OP_(I31w):
+ case OP_I31w:
/* The expression parser chokes on a trailing !, so we have
to find it first and zap it. */
{
@@ -3993,20 +3963,17 @@
break;
/* Expressions */
- case OP_(iEXP):
- iEXP:
+ case OP_EXPi: EXPi:
if (my_get_expression (&inst.reloc.exp, &str, GE_OPT_PREFIX))
return FAIL;
break;
- case OP_(EXP):
- EXP:
+ case OP_EXP: EXP:
if (my_get_expression (&inst.reloc.exp, &str, GE_NO_PREFIX))
return FAIL;
break;
- case OP_(EXPr):
- EXPr:
+ case OP_EXPr: EXPr:
if (my_get_expression (&inst.reloc.exp, &str, GE_NO_PREFIX))
return FAIL;
if (inst.reloc.exp.X_op == O_symbol)
@@ -4026,17 +3993,19 @@
break;
/* Register or expression */
- case OP_(RR_EX): po_reg_or_goto (REG_TYPE_RN, EXP); break;
- case OP_(RR_EXr): po_reg_or_goto (REG_TYPE_RN, EXPr); break;
- case OP_(oRL_iEX):
- case OP_(oRR_iEX):
- case OP_(RL_iEX):
- case OP_(RR_iEX): po_reg_or_goto (REG_TYPE_RN, iEXP); break;
+ case OP_RR_EX: po_reg_or_goto (REG_TYPE_RN, EXP); break;
+ case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
+ case OP_oRL_EXi:
+ case OP_oRR_EXi:
+ case OP_RL_EXi:
+ case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
/* Register or immediate */
- case OP_(RRnpc_I0): po_reg_or_goto (REG_TYPE_RN, I0); break;
+ case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
+ I0: po_imm_or_fail (0, 0, FALSE); break;
- case OP_(RF_IF):
+
+ case OP_RF_IF:
if (!is_immediate_prefix (*str))
po_reg_or_fail (REG_TYPE_FN);
else
@@ -4053,7 +4022,7 @@
break;
/* Two kinds of register */
- case OP_(RIWR_RIWC):
+ case OP_RIWR_RIWC:
{
struct reg_entry *rege = arm_reg_parse_multi (&str);
if (rege->type != REG_TYPE_MMXWR && rege->type != REG_TYPE_MMXWC)
@@ -4067,13 +4036,13 @@
break;
/* Misc */
- case OP_(CPSF): val = parse_cps_flags (&str); break;
- case OP_(ENDI): val = parse_endian_specifier (&str); break;
- case OP_(oROR): val = parse_ror (&str); break;
- case OP_(PSR): val = parse_psr (&str); break;
+ case OP_CPSF: val = parse_cps_flags (&str); break;
+ case OP_ENDI: val = parse_endian_specifier (&str); break;
+ case OP_oROR: val = parse_ror (&str); break;
+ case OP_PSR: val = parse_psr (&str); break;
/* Register lists */
- case OP_(REGLST):
+ case OP_REGLST:
val = reg_list (&str);
if (*str == '^')
{
@@ -4082,36 +4051,36 @@
}
break;
- case OP_(VRSLST):
+ case OP_VRSLST:
val = vfp_parse_reg_list (&str, &inst.operands[i].reg, 0);
break;
- case OP_(VRDLST):
+ case OP_VRDLST:
val = vfp_parse_reg_list (&str, &inst.operands[i].reg, 1);
break;
/* Addressing modes */
- case OP_(ADDR):
+ case OP_ADDR:
if (parse_address (&str, i))
return FAIL;
break;
- case OP_(SHOP):
+ case OP_SH:
if (parse_shifter_operand (&str, i))
return FAIL;
break;
- case OP_(oSHll):
+ case OP_oSHll:
if (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE))
return FAIL;
break;
- case OP_(oSHar):
+ case OP_oSHar:
if (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE))
return FAIL;
break;
- case OP_(oSHllar):
+ case OP_oSHllar:
if (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE))
return FAIL;
break;
@@ -4125,30 +4094,30 @@
this allows a syntax error to take precedence. */
switch (*p)
{
- case OP_(RRnpc):
- case OP_(bRRnpc):
- case OP_(RRw):
- case OP_(RRnpc_I0):
+ case OP_RRnpc:
+ case OP_RRnpcb:
+ case OP_RRw:
+ case OP_RRnpc_I0:
if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
inst.error = BAD_PC;
break;
- case OP_(oRL):
- case OP_(RL):
- case OP_(RLw):
- case OP_(oRL_iEX):
- case OP_(RL_iEX):
+ case OP_oRL:
+ case OP_RL:
+ case OP_RLw:
+ case OP_oRL_EXi:
+ case OP_RL_EXi:
if (inst.operands[i].isreg && inst.operands[i].reg > 7)
inst.error = BAD_HIREG;
break;
- case OP_(CPSF):
- case OP_(ENDI):
- case OP_(oROR):
- case OP_(PSR):
- case OP_(REGLST):
- case OP_(VRSLST):
- case OP_(VRDLST):
+ case OP_CPSF:
+ case OP_ENDI:
+ case OP_oROR:
+ case OP_PSR:
+ case OP_REGLST:
+ case OP_VRSLST:
+ case OP_VRDLST:
if (val == FAIL)
return FAIL;
inst.operands[i].imm = val;
@@ -4161,7 +4130,7 @@
/* If we get here, this operand was successfully parsed. */
inst.operands[i].present = 1;
- if (*++p == OP_(stop))
+ if (*++p == OP_stop)
break;
/* If this is an optional argument, and we have no further
@@ -6709,98 +6678,109 @@
{"al", 0xe0000000}
};
-/* Table of ARM-format instructions. These macros assemble the conditional
- variants of each instruction from its bare form. */
+/* Table of ARM-format instructions. */
-#define CE(mnem, opc, nops, ops, aenc) \
- { #mnem, 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "eq", 0x0 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "ne", 0x1 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "cs", 0x2 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "hs", 0x2 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "cc", 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "ul", 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "lo", 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "mi", 0x4 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "pl", 0x5 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "vs", 0x6 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "vc", 0x7 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "hi", 0x8 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "ls", 0x9 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "ge", 0xa ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "lt", 0xb ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "gt", 0xc ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "le", 0xd ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #mnem "al", 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }
+/* Macros for gluing together operand strings. */
+#define OPS0() { OP_stop, }
+#define OPS1(a) { OP_##a, }
+#define OPS2(a,b) { OP_##a,OP_##b, }
+#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
+#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
+#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
+#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
-#define CM(m1, m2, opc, nops, ops, aenc) \
- { #m1 #m2, 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "eq" #m2, 0x0 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "ne" #m2, 0x1 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "cs" #m2, 0x2 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "hs" #m2, 0x2 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "cc" #m2, 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "ul" #m2, 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "lo" #m2, 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "mi" #m2, 0x4 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "pl" #m2, 0x5 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "vs" #m2, 0x6 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "vc" #m2, 0x7 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "hi" #m2, 0x8 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "ls" #m2, 0x9 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "ge" #m2, 0xa ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "lt" #m2, 0xb ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "gt" #m2, 0xc ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "le" #m2, 0xd ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
- { #m1 "al" #m2, 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }
+/* These macros assemble the conditional variants of each instruction
+ from its bare form. */
+#define CE(mnem, opc, nops, ops, aenc) \
+ { #mnem, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "eq", 0x0 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "ne", 0x1 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "cs", 0x2 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "hs", 0x2 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "cc", 0x3 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "ul", 0x3 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "lo", 0x3 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "mi", 0x4 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "pl", 0x5 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "vs", 0x6 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "vc", 0x7 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "hi", 0x8 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "ls", 0x9 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "ge", 0xa ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "lt", 0xb ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "gt", 0xc ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "le", 0xd ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem "al", 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
+
+#define CM(m1, m2, opc, nops, ops, aenc) \
+ { #m1 #m2, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "eq" #m2, 0x0 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "ne" #m2, 0x1 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "cs" #m2, 0x2 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "hs" #m2, 0x2 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "cc" #m2, 0x3 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "ul" #m2, 0x3 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "lo" #m2, 0x3 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "mi" #m2, 0x4 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "pl" #m2, 0x5 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "vs" #m2, 0x6 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "vc" #m2, 0x7 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "hi" #m2, 0x8 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "ls" #m2, 0x9 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "ge" #m2, 0xa ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "lt" #m2, 0xb ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "gt" #m2, 0xc ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "le" #m2, 0xd ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 "al" #m2, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
+
#define UE(mnem, opc, nops, ops, aenc) \
- { #mnem, 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }
+ { #mnem, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
#define UF(mnem, opc, nops, ops, aenc) \
- { #mnem, 0xf ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }
+ { #mnem, 0xf ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
static const struct asm_opcode insns[] =
{
#define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
- CE(and, 0000000, 3, (RR, RR, SHOP), arit),
- CM(and,s, 0100000, 3, (RR, RR, SHOP), arit),
- CE(eor, 0200000, 3, (RR, RR, SHOP), arit),
- CM(eor,s, 0300000, 3, (RR, RR, SHOP), arit),
- CE(sub, 0400000, 3, (RR, RR, SHOP), arit),
- CM(sub,s, 0500000, 3, (RR, RR, SHOP), arit),
- CE(rsb, 0600000, 3, (RR, RR, SHOP), arit),
- CM(rsb,s, 0700000, 3, (RR, RR, SHOP), arit),
- CE(add, 0800000, 3, (RR, RR, SHOP), arit),
- CM(add,s, 0900000, 3, (RR, RR, SHOP), arit),
- CE(adc, 0a00000, 3, (RR, RR, SHOP), arit),
- CM(adc,s, 0b00000, 3, (RR, RR, SHOP), arit),
- CE(sbc, 0c00000, 3, (RR, RR, SHOP), arit),
- CM(sbc,s, 0d00000, 3, (RR, RR, SHOP), arit),
- CE(rsc, 0e00000, 3, (RR, RR, SHOP), arit),
- CM(rsc,s, 0f00000, 3, (RR, RR, SHOP), arit),
- CE(orr, 1800000, 3, (RR, RR, SHOP), arit),
- CM(orr,s, 1900000, 3, (RR, RR, SHOP), arit),
- CE(bic, 1c00000, 3, (RR, RR, SHOP), arit),
- CM(bic,s, 1d00000, 3, (RR, RR, SHOP), arit),
+ CE(and, 0000000, 3, (RR, RR, SH), arit),
+ CM(and,s, 0100000, 3, (RR, RR, SH), arit),
+ CE(eor, 0200000, 3, (RR, RR, SH), arit),
+ CM(eor,s, 0300000, 3, (RR, RR, SH), arit),
+ CE(sub, 0400000, 3, (RR, RR, SH), arit),
+ CM(sub,s, 0500000, 3, (RR, RR, SH), arit),
+ CE(rsb, 0600000, 3, (RR, RR, SH), arit),
+ CM(rsb,s, 0700000, 3, (RR, RR, SH), arit),
+ CE(add, 0800000, 3, (RR, RR, SH), arit),
+ CM(add,s, 0900000, 3, (RR, RR, SH), arit),
+ CE(adc, 0a00000, 3, (RR, RR, SH), arit),
+ CM(adc,s, 0b00000, 3, (RR, RR, SH), arit),
+ CE(sbc, 0c00000, 3, (RR, RR, SH), arit),
+ CM(sbc,s, 0d00000, 3, (RR, RR, SH), arit),
+ CE(rsc, 0e00000, 3, (RR, RR, SH), arit),
+ CM(rsc,s, 0f00000, 3, (RR, RR, SH), arit),
+ CE(orr, 1800000, 3, (RR, RR, SH), arit),
+ CM(orr,s, 1900000, 3, (RR, RR, SH), arit),
+ CE(bic, 1c00000, 3, (RR, RR, SH), arit),
+ CM(bic,s, 1d00000, 3, (RR, RR, SH), arit),
- CE(tst, 1100000, 2, (RR, SHOP), cmp),
- CM(tst,s, 1100000, 2, (RR, SHOP), cmp),
- CM(tst,p, 110f000, 2, (RR, SHOP), cmp),
- CE(teq, 1300000, 2, (RR, SHOP), cmp),
- CM(teq,s, 1300000, 2, (RR, SHOP), cmp),
- CM(teq,p, 130f000, 2, (RR, SHOP), cmp),
- CE(cmp, 1500000, 2, (RR, SHOP), cmp),
- CM(cmp,s, 1500000, 2, (RR, SHOP), cmp),
- CM(cmp,p, 150f000, 2, (RR, SHOP), cmp),
- CE(cmn, 1700000, 2, (RR, SHOP), cmp),
- CM(cmn,s, 1700000, 2, (RR, SHOP), cmp),
- CM(cmn,p, 170f000, 2, (RR, SHOP), cmp),
+ CE(tst, 1100000, 2, (RR, SH), cmp),
+ CM(tst,s, 1100000, 2, (RR, SH), cmp),
+ CM(tst,p, 110f000, 2, (RR, SH), cmp),
+ CE(teq, 1300000, 2, (RR, SH), cmp),
+ CM(teq,s, 1300000, 2, (RR, SH), cmp),
+ CM(teq,p, 130f000, 2, (RR, SH), cmp),
+ CE(cmp, 1500000, 2, (RR, SH), cmp),
+ CM(cmp,s, 1500000, 2, (RR, SH), cmp),
+ CM(cmp,p, 150f000, 2, (RR, SH), cmp),
+ CE(cmn, 1700000, 2, (RR, SH), cmp),
+ CM(cmn,s, 1700000, 2, (RR, SH), cmp),
+ CM(cmn,p, 170f000, 2, (RR, SH), cmp),
- CE(mov, 1a00000, 2, (RR, SHOP), mov),
- CM(mov,s, 1b00000, 2, (RR, SHOP), mov),
- CE(mvn, 1e00000, 2, (RR, SHOP), mov),
- CM(mvn,s, 1f00000, 2, (RR, SHOP), mov),
+ CE(mov, 1a00000, 2, (RR, SH), mov),
+ CM(mov,s, 1b00000, 2, (RR, SH), mov),
+ CE(mvn, 1e00000, 2, (RR, SH), mov),
+ CM(mvn,s, 1f00000, 2, (RR, SH), mov),
CE(ldr, 4100000, 2, (RR, ADDR), ldst),
CM(ldr,b, 4500000, 2, (RR, ADDR), ldst),
@@ -6829,7 +6809,7 @@
CM(ldm,ea, 9100000, 2, (RRw, REGLST), ldmstm),
CM(ldm,ed, 9900000, 2, (RRw, REGLST), ldmstm),
- CE(swi, f000000, 1, (iEXP), swi),
+ CE(swi, f000000, 1, (EXPi), swi),
#ifdef TE_WINCE
/* XXX This is the wrong place to do this. Think multi-arch. */
CE(b, a000000, 1, (EXPr), branch),
@@ -6842,7 +6822,7 @@
/* Pseudo ops. */
CE(adr, 28f0000, 2, (RR, EXP), adr),
CM(adr,l, 28f0000, 2, (RR, EXP), adrl),
- CE(nop, 1a00000, 1, (ocI255), nop),
+ CE(nop, 1a00000, 1, (oI255c), nop),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
@@ -6852,23 +6832,23 @@
CM(mla,s, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
/* Generic coprocessor instructions. */
- CE(cdp, e000000, 6, (RCP, bI15, RCN, RCN, RCN, obI7), cdp),
+ CE(cdp, e000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp),
CE(ldc, c100000, 3, (RCP, RCN, ADDR), lstc),
CM(ldc,l, c500000, 3, (RCP, RCN, ADDR), lstc),
CE(stc, c000000, 3, (RCP, RCN, ADDR), lstc),
CM(stc,l, c400000, 3, (RCP, RCN, ADDR), lstc),
- CE(mcr, e000010, 6, (RCP, bI7, RR, RCN, RCN, obI7), co_reg),
- CE(mrc, e100010, 6, (RCP, bI7, RR, RCN, RCN, obI7), co_reg),
+ CE(mcr, e000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
+ CE(mrc, e100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
- CE(swp, 1000090, 3, (RRnpc, RRnpc, bRRnpc), swap),
- CM(swp,b, 1400090, 3, (RRnpc, RRnpc, bRRnpc), swap),
+ CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), swap),
+ CM(swp,b, 1400090, 3, (RRnpc, RRnpc, RRnpcb), swap),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
CE(mrs, 10f0000, 2, (RR, PSR), mrs),
- CE(msr, 120f000, 2, (PSR, RR_iEX), msr),
+ CE(msr, 120f000, 2, (PSR, RR_EXi), msr),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
@@ -6901,14 +6881,14 @@
BLX(2). Only this variant has conditional execution. */
CE(blx, 12fff30, 1, (RR_EXr), blx),
CE(clz, 16f0f10, 2, (RRnpc, RRnpc), clz),
- UE(bkpt, 1200070, 1, (obIffff), bkpt),
+ UE(bkpt, 1200070, 1, (oIffffb), bkpt),
UF(ldc2, c100000, 3, (RCP, RCN, ADDR), lstc),
UF(ldc2l, c500000, 3, (RCP, RCN, ADDR), lstc),
UF(stc2, c000000, 3, (RCP, RCN, ADDR), lstc),
UF(stc2l, c400000, 3, (RCP, RCN, ADDR), lstc),
- UF(cdp2, e000000, 6, (RCP, bI15, RCN, RCN, RCN, obI7), cdp),
- UF(mcr2, e000010, 6, (RCP, bI7, RR, RCN, RCN, obI7), co_reg),
- UF(mrc2, e100010, 6, (RCP, bI7, RR, RCN, RCN, obI7), co_reg),
+ UF(cdp2, e000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp),
+ UF(mcr2, e000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
+ UF(mrc2, e100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
@@ -6944,8 +6924,8 @@
CM(ldr,d, 00000d0, 2, (RR, ADDR), ldrd),
CM(str,d, 00000f0, 2, (RR, ADDR), ldrd),
- CE(mcrr, c400000, 5, (RCP, bI15, RRnpc, RRnpc, RCN), co_reg2c),
- CE(mrrc, c500000, 5, (RCP, bI15, RRnpc, RRnpc, RCN), co_reg2c),
+ CE(mcrr, c400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
+ CE(mrrc, c500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
@@ -6953,12 +6933,12 @@
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
- UF(cps, 1020000, 1, (bI31), cps),
- UF(cpsie, 1080000, 2, (CPSF, obI31), cpsi),
- UF(cpsid, 10c0000, 2, (CPSF, obI31), cpsi),
- CE(ldrex, 1900f9f, 2, (RRnpc, bRRnpc), ldrex),
- UF(mcrr2, c400000, 5, (RCP, bI15, RRnpc, RRnpc, RCN), co_reg2c),
- UF(mrrc2, c500000, 5, (RCP, bI15, RRnpc, RRnpc, RCN), co_reg2c),
+ UF(cps, 1020000, 1, (I31b), cps),
+ UF(cpsie, 1080000, 2, (CPSF, oI31b), cpsi),
+ UF(cpsid, 10c0000, 2, (CPSF, oI31b), cpsi),
+ CE(ldrex, 1900f9f, 2, (RRnpc, RRnpcb), ldrex),
+ UF(mcrr2, c400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
+ UF(mrrc2, c500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
CE(pkhbt, 6800010, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt),
CE(pkhtb, 6800050, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb),
CE(qadd16, 6200f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
@@ -7046,7 +7026,7 @@
UF(srsdb, 94d0500, 1, (I31w), srs),
CE(ssat, 6a00010, 4, (RRnpc, I32, RRnpc, oSHllar), ssat),
CE(ssat16, 6a00f30, 3, (RRnpc, I16, RRnpc), ssat16),
- CE(strex, 1800f90, 3, (RRnpc, RRnpc, bRRnpc), strex),
+ CE(strex, 1800f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
CE(umaal, 0400090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
CE(usad8, 780f010, 3, (RRnpc, RRnpc, RRnpc), smul),
CE(usada8, 7800010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
@@ -7055,12 +7035,12 @@
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6K
- CE(ldrexb, 1d00f9f, 2, (RRnpc, bRRnpc), ldrex),
- CE(ldrexd, 1b00f9f, 2, (RRnpc, bRRnpc), ldrex),
- CE(ldrexh, 1f00f9f, 2, (RRnpc, bRRnpc), ldrex),
- CE(strexb, 1c00f90, 3, (RRnpc, RRnpc, bRRnpc), strex),
- CE(strexd, 1a00f90, 3, (RRnpc, RRnpc, bRRnpc), strex),
- CE(strexh, 1e00f90, 3, (RRnpc, RRnpc, bRRnpc), strex),
+ CE(ldrexb, 1d00f9f, 2, (RRnpc, RRnpcb), ldrex),
+ CE(ldrexd, 1b00f9f, 2, (RRnpc, RRnpcb), ldrex),
+ CE(ldrexh, 1f00f9f, 2, (RRnpc, RRnpcb), ldrex),
+ CE(strexb, 1c00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
+ CE(strexd, 1a00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
+ CE(strexh, 1e00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
UF(clrex, 57ff01f, 0, (), empty),
CE(wfe, 320f002, 0, (), empty),
CE(wfi, 320f003, 0, (), empty),
@@ -7069,7 +7049,7 @@
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6Z
- CE(smi, 1600070, 1, (iEXP), smi),
+ CE(smi, 1600070, 1, (EXPi), smi),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6T2
@@ -7527,12 +7507,12 @@
/* Instructions that were new with the real FPA, call them V2. */
#undef ARM_VARIANT
#define ARM_VARIANT FPU_FPA_EXT_V2
- CE(lfm, c100200, 3, (RF, bI4, ADDR), fpa_ldmstm),
- CM(lfm,fd, c900200, 3, (RF, bI4, ADDR), fpa_ldmstm),
- CM(lfm,ea, d100200, 3, (RF, bI4, ADDR), fpa_ldmstm),
- CE(sfm, c000200, 3, (RF, bI4, ADDR), fpa_ldmstm),
- CM(sfm,fd, d000200, 3, (RF, bI4, ADDR), fpa_ldmstm),
- CM(sfm,ea, c800200, 3, (RF, bI4, ADDR), fpa_ldmstm),
+ CE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CM(lfm,fd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CM(lfm,ea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CM(sfm,fd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CM(sfm,ea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
@@ -7872,8 +7852,8 @@
CE(cftruncd32,e1005e0, 2, (RMFX, RMD), mav_binops_1),
CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple_1),
CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple_1),
- CE(cfsh32, e000500, 3, (RMFX, RMFX, Is63), mav_shift),
- CE(cfsh64, e200500, 3, (RMDX, RMDX, Is63), mav_shift),
+ CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
+ CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
CE(cfcmps, e100490, 3, (RR, RMF, RMF), mav_triple_2),
CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), mav_triple_2),
CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), mav_triple_2),
@@ -7914,15 +7894,15 @@
/* Thumb instructions are substantially simpler, there being no conditional
suffix or infix. */
#define TI(mnem, opc, nops, ops, tenc) \
- { #mnem, 0x ## opc, THUMB_VARIANT, OPERANDS##nops ops, do_ ## tenc }
+ { #mnem, 0x ## opc, THUMB_VARIANT, OPS##nops ops, do_ ## tenc }
static const struct asm_opcode tinsns[] =
{
#define THUMB_VARIANT ARM_EXT_V4T /* Thumb v1 (ARMv4T). */
TI(adc, 4140, 3, (RL, RL, oRL), t_arit),
- TI(add, 0000, 3, (RR, RR_iEX, oRR_iEX), t_add_sub),
+ TI(add, 0000, 3, (RR, RR_EXi, oRR_EXi), t_add_sub),
TI(and, 4000, 3, (RL, RL, oRL), t_arit),
- TI(asr, 4100, 3, (RL, RL_iEX, oRL_iEX), t_shift),
+ TI(asr, 4100, 3, (RL, RL_EXi, oRL_EXi), t_shift),
TI(b, e7fe, 1, (EXP), t_branch12),
TI(beq, d0fe, 1, (EXP), t_branch9),
TI(bne, d1fe, 1, (EXP), t_branch9),
@@ -7946,7 +7926,7 @@
TI(bl, f7fffffe, 1, (EXP), t_branch23),
TI(bx, 4700, 1, (RR), t_bx),
TI(cmn, 42c0, 3, (RL, RL, oRL), t_arit),
- TI(cmp, 4280, 2, (RR, RR_iEX), t_mov_cmp),
+ TI(cmp, 4280, 2, (RR, RR_EXi), t_mov_cmp),
TI(eor, 4040, 3, (RL, RL, oRL), t_arit),
TI(ldmia, c800, 2, (RLw, REGLST), t_ldmstm),
TI(ldr, 5800, 2, (RL, ADDR), t_ldst),
@@ -7956,9 +7936,9 @@
TI(ldrsh, 5e00, 2, (RL, ADDR), t_lds),
TI(ldsb, 5600, 2, (RL, ADDR), t_lds),
TI(ldsh, 5e00, 2, (RL, ADDR), t_lds),
- TI(lsl, 4080, 3, (RL, RL_iEX, oRL_iEX), t_shift),
- TI(lsr, 40c0, 3, (RL, RL_iEX, oRL_iEX), t_shift),
- TI(mov, 4600, 2, (RR, RR_iEX), t_mov_cmp),
+ TI(lsl, 4080, 3, (RL, RL_EXi, oRL_EXi), t_shift),
+ TI(lsr, 40c0, 3, (RL, RL_EXi, oRL_EXi), t_shift),
+ TI(mov, 4600, 2, (RR, RR_EXi), t_mov_cmp),
TI(mul, 4340, 3, (RL, RL, oRL), t_arit),
TI(mvn, 43c0, 3, (RL, RL, oRL), t_arit),
TI(neg, 4240, 3, (RL, RL, oRL), t_arit),
@@ -7972,7 +7952,7 @@
TI(strb, 5400, 2, (RL, ADDR), t_ldst),
TI(strh, 5200, 2, (RL, ADDR), t_ldst),
TI(swi, df00, 1, (EXP), t_swi),
- TI(sub, 8000, 3, (RR, RR_iEX, oRR_iEX), t_add_sub),
+ TI(sub, 8000, 3, (RR, RR_EXi, oRR_EXi), t_add_sub),
TI(tst, 4200, 3, (RL, RL, oRL), t_arit),
/* Pseudo ops: */
TI(adr, 000f, 2, (RL, EXP), t_adr),
@@ -7981,7 +7961,7 @@
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V5T /* Thumb v2 (ARMv5T). */
TI(blx, 4780, 1, (RR_EX), t_blx),
- TI(bkpt, be00, 1, (obI255), t_bkpt),
+ TI(bkpt, be00, 1, (oI255b), t_bkpt),
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V6
@@ -8006,6 +7986,13 @@
};
#undef THUMB_VARIANT
#undef TI
+#undef OPS0
+#undef OPS1
+#undef OPS2
+#undef OPS3
+#undef OPS4
+#undef OPS5
+#undef OPS6
/* MD interface: bits in the object file. */