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Thumb32 assembler (53/69)
- From: Zack Weinberg <zack at codesourcery dot com>
- To: binutils <binutils at sourceware dot org>
- Date: Tue, 26 Apr 2005 03:00:09 -0700
- Subject: Thumb32 assembler (53/69)
More tidying: quite a few of the encoding functions have identical
bodies, and can be collapsed together. So can some structs down in
the command-line processor. Thanks to Nathaniel Smith for writing me
a script to find all of the duplicates.
zw
* config/tc-arm.c (do_empty): Rename do_noargs.
(do_mav_triple_1): Rename do_mav_triple.
(do_mav_dspsc_1): Rename do_mav_dspsc.
(do_rd, do_rd_rm, do_rd_rn, do_rn_rd, do_rd_rm_rn, do_rd_rn_rm)
(do_rm_rd_rn, do_imm0, do_rd_cpaddr): New functions.
(insns, tinsns): Use new generic encoding functions wherever possible.
Update for renames.
(struct arm_arch_extension_table): Rename arm_option_value_table.
(arm_extensions, arm_fpus, arm_float_abis, arm_eabis): Use type
arm_option_value_table.
(arm_parse_extension, arm_parse_fpu, arm_parse_float_abi)
(arm_parse_eabi): Update to match.
(do_clz, do_cps, do_ldrex, do_qadd, do_qadd16, do_rbit, do_rev)
(do_swap, do_t_bkpt, do_t_cps, do_vfp_dp_monadic, do_vfp_dp_dyadic)
(do_vfp_dp_compare_z, do_vfp_reg_from_dp, do_vfp_reg2_from_dp)
(do_vfp_dp_from_reg, do_vfp_dp_from_reg2, do_vfp_reg_from_ctrl)
(do_vfp_ctrl_from_reg, do_fpa_ctrl, do_fpa_monadic, do_fpa_dyadic)
(do_fpa_from_reg, do_fpa_to_reg, do_fpa_ldst, do_iwmmxt_tbcst)
(do_iwmmxt_tmcr, do_iwmmxt_tmcrr, do_iwmmxt_tmovmsk, do_iwmmxt_tmrc)
(do_iwmmxt_tmrrc, do_iwmmxt_wrwr, do_iwmmxt_wrwrwr, do_iwmmxt_wrwrwcg)
(do_mav_binops_1, do_mav_binops_2, do_mav_triple_2, do_mav_dspsc_0)
(do_mav_ldst, struct arm_fpu_option_table, struct arm_eabi_option_table)
(struct arm_float_abi_option_table): Delete.
===================================================================
Index: gas/config/tc-arm.c
--- gas/config/tc-arm.c (revision 55)
+++ gas/config/tc-arm.c (revision 56)
@@ -4175,13 +4175,79 @@
}
-/* Functions for instruction parsing, sorted by subarchitecture. */
+/* Functions for instruction encoding, sorted by subarchitecture.
+ First some generics; their names are taken from the conventional
+ bit positions for register arguments in ARM format instructions. */
static void
-do_empty (void)
+do_noargs (void)
{
}
+static void
+do_rd (void)
+{
+ inst.instruction |= inst.operands[0].reg << 12;
+}
+
+static void
+do_rd_rm (void)
+{
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
+}
+
+static void
+do_rd_rn (void)
+{
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+}
+
+static void
+do_rn_rd (void)
+{
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg << 12;
+}
+
+static void
+do_rd_rm_rn (void)
+{
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 16;
+}
+
+static void
+do_rd_rn_rm (void)
+{
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
+}
+
+static void
+do_rm_rd_rn (void)
+{
+ inst.instruction |= inst.operands[0].reg;
+ inst.instruction |= inst.operands[1].reg << 12;
+ inst.instruction |= inst.operands[2].reg << 16;
+}
+
+static void
+do_imm0 (void)
+{
+ inst.instruction |= inst.operands[0].imm;
+}
+
+static void
+do_rd_cpaddr (void)
+{
+ inst.instruction |= inst.operands[0].reg << 12;
+ encode_cp_address_arm (1, TRUE, TRUE, 0);
+}
+
/* ARM instructions, in alphabetical order by function name (except
that wrapper functions appear immediately after the function they
wrap). */
@@ -4399,19 +4465,7 @@
inst.instruction |= inst.operands[5].imm << 5;
}
-/* ARM V5 count-leading-zeroes instruction (argument parse)
- CLZ{<cond>} <Rd>, <Rm>
- Condition defaults to COND_ALWAYS.
- Error if Rd or Rm are R15. */
-
static void
-do_clz (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg;
-}
-
-static void
do_cmp (void)
{
inst.instruction |= inst.operands[0].reg << 16;
@@ -4460,16 +4514,7 @@
inst.instruction |= inst.operands[4].reg;
}
-/* ARM V6 change processor state instruction (argument parse)
- CPS, CPSIE, CSPID . */
-
static void
-do_cps (void)
-{
- inst.instruction |= inst.operands[0].imm;
-}
-
-static void
do_cpsi (void)
{
inst.instruction |= inst.operands[0].imm << 6;
@@ -4564,20 +4609,7 @@
encode_addr_mode_3_arm (1, /*is_t=*/FALSE);
}
-/* ARM V6 Load Register Exclusive instruction (argument parse).
- LDREX{,B,D,H}{<cond>} <Rd>, [<Rn>]
- Condition defaults to COND_ALWAYS.
- Error if Rd or Rn are R15.
- See ARMARMv6 A4.1.27: LDREX. */
-
static void
-do_ldrex (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
-}
-
-static void
do_ldst (void)
{
inst.instruction |= inst.operands[0].reg << 12;
@@ -4835,51 +4867,6 @@
encode_addr_mode_2_arm (0, /*is_t=*/FALSE);
}
-/* ARM V5E (El Segundo) saturating-add/subtract (argument parse)
- Q[D]{ADD,SUB}{cond} Rd,Rm,Rn
- Error if any register is R15. */
-
-static void
-do_qadd (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg;
- inst.instruction |= inst.operands[2].reg << 16;
-}
-
-/* ARM V6 Perform Two Sixteen Bit Integer Additions. (argument parse).
- QADD16{<cond>} <Rd>, <Rn>, <Rm>
- Condition defaults to COND_ALWAYS.
- Error if Rd, Rn or Rm are R15. */
-
-static void
-do_qadd16 (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
-}
-
-static void
-do_rbit (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg;
-}
-
-/* ARM V6 REV (Byte Reverse Word) reverses the byte order in a 32-bit
- register (argument parse).
- REV{<cond>} Rd, Rm.
- Condition defaults to COND_ALWAYS.
- Error if Rd or Rm are R15. */
-
-static void
-do_rev (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg;
-}
-
/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
word at the specified address and the following word
respectively.
@@ -5031,14 +5018,6 @@
inst.instruction |= inst.operands[2].reg << 16;
}
-static void
-do_swap (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg;
- inst.instruction |= inst.operands[2].reg << 16;
-}
-
/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
extends it to 32-bits, and adds the result to a value in another
register. You can specify a rotation by 0, 8, 16, or 24 bits
@@ -5187,15 +5166,6 @@
inst.instruction |= inst.operands[1].reg << 3;
}
-/* THUMB V5 breakpoint instruction (argument parse)
- BKPT <immed_8>. */
-
-static void
-do_t_bkpt (void)
-{
- inst.instruction |= inst.operands[0].imm;
-}
-
/* ARM V5 Thumb BLX (argument parse)
BLX <target_addr> which is BLX(1)
BLX <Rm> which is BLX(2)
@@ -5260,14 +5230,6 @@
because BX PC only works if the instruction is word aligned. */
}
-/* THUMB CPS instruction (argument parse). */
-
-static void
-do_t_cps (void)
-{
- inst.instruction |= inst.operands[0].imm;
-}
-
/* THUMB CPY instruction (argument parse). */
static void
@@ -5567,13 +5529,6 @@
}
static void
-do_vfp_dp_monadic (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg;
-}
-
-static void
do_vfp_sp_dyadic (void)
{
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sd);
@@ -5582,26 +5537,12 @@
}
static void
-do_vfp_dp_dyadic (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
-}
-
-static void
do_vfp_sp_compare_z (void)
{
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sd);
}
static void
-do_vfp_dp_compare_z (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
-}
-
-static void
do_vfp_dp_sp_cvt (void)
{
inst.instruction |= inst.operands[0].reg << 12;
@@ -5658,50 +5599,6 @@
}
static void
-do_vfp_reg_from_dp (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
-}
-
-static void
-do_vfp_reg2_from_dp (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
-}
-
-static void
-do_vfp_dp_from_reg (void)
-{
- inst.instruction |= inst.operands[0].reg << 16;
- inst.instruction |= inst.operands[1].reg << 12;
-}
-
-static void
-do_vfp_dp_from_reg2 (void)
-{
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 12;
- inst.instruction |= inst.operands[2].reg << 16;
-}
-
-static void
-do_vfp_reg_from_ctrl (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
-}
-
-static void
-do_vfp_ctrl_from_reg (void)
-{
- inst.instruction |= inst.operands[0].reg << 16;
- inst.instruction |= inst.operands[1].reg << 12;
-}
-
-static void
do_vfp_sp_ldst (void)
{
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sd);
@@ -5794,16 +5691,7 @@
/* FPA instructions. Also in a logical order. */
-/* FP control register read/write.
- Format: <WFS|RFS|WFC|RFC>{cond} Rn */
-
static void
-do_fpa_ctrl (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
-}
-
-static void
do_fpa_cmp (void)
{
inst.instruction |= inst.operands[0].reg << 16;
@@ -5811,42 +5699,6 @@
}
static void
-do_fpa_monadic (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg;
-}
-
-static void
-do_fpa_dyadic (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
-}
-
-static void
-do_fpa_from_reg (void)
-{
- inst.instruction |= inst.operands[0].reg << 16;
- inst.instruction |= inst.operands[1].reg << 12;
-}
-
-static void
-do_fpa_to_reg (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg;
-}
-
-static void
-do_fpa_ldst (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- encode_cp_address_arm (1, TRUE, TRUE, 0);
-}
-
-static void
do_fpa_ldmstm (void)
{
inst.instruction |= inst.operands[0].reg << 12;
@@ -5898,13 +5750,6 @@
}
static void
-do_iwmmxt_tbcst (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
-}
-
-static void
do_iwmmxt_textrc (void)
{
inst.instruction |= inst.operands[0].reg << 12;
@@ -5928,21 +5773,6 @@
}
static void
-do_iwmmxt_tmcr (void)
-{
- inst.instruction |= inst.operands[0].reg << 16;
- inst.instruction |= inst.operands[1].reg << 12;
-}
-
-static void
-do_iwmmxt_tmcrr (void)
-{
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 12;
- inst.instruction |= inst.operands[2].reg << 16;
-}
-
-static void
do_iwmmxt_tmia (void)
{
inst.instruction |= inst.operands[0].reg << 5;
@@ -5951,28 +5781,6 @@
}
static void
-do_iwmmxt_tmovmsk (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
-}
-
-static void
-do_iwmmxt_tmrc (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
-}
-
-static void
-do_iwmmxt_tmrrc (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
-}
-
-static void
do_iwmmxt_waligni (void)
{
inst.instruction |= inst.operands[0].reg << 12;
@@ -6017,29 +5825,6 @@
}
static void
-do_iwmmxt_wrwr (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
-}
-
-static void
-do_iwmmxt_wrwrwcg (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
-}
-
-static void
-do_iwmmxt_wrwrwr (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
-}
-
-static void
do_iwmmxt_wshufh (void)
{
inst.instruction |= inst.operands[0].reg << 12;
@@ -6060,40 +5845,16 @@
/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
operations first, then control, shift, and load/store. */
-/* Insn like "foo X,Y". */
-
-static void
-do_mav_binops_1 (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
-}
-
-static void
-do_mav_binops_2 (void)
-{
- inst.instruction |= inst.operands[0].reg << 16;
- inst.instruction |= inst.operands[1].reg << 12;
-}
-
/* Insns like "foo X,Y,Z". */
static void
-do_mav_triple_1 (void)
+do_mav_triple (void)
{
inst.instruction |= inst.operands[0].reg << 16;
inst.instruction |= inst.operands[1].reg;
inst.instruction |= inst.operands[2].reg << 12;
}
-static void
-do_mav_triple_2 (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
-}
-
/* Insns like "foo W,X,Y,Z".
where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
@@ -6108,18 +5869,11 @@
/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
static void
-do_mav_dspsc_1 (void)
+do_mav_dspsc (void)
{
inst.instruction |= inst.operands[1].reg << 12;
}
-/* cfmv32sc<cond> MVDX[15:0],DSPSC. */
-static void
-do_mav_dspsc_0 (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
-}
-
/* Maverick shift immediate instructions.
cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
@@ -6139,17 +5893,6 @@
inst.instruction |= imm;
}
-
-/* Maverick load/store instructions.
- <insn><cond> CRd,[Rn,<offset>]{!}.
- <insn><cond> CRd,[Rn],<offset>. */
-
-static void
-do_mav_ldst (void)
-{
- inst.instruction |= inst.operands[0].reg << 12;
- encode_cp_address_arm (1, TRUE, TRUE, 0);
-}
/* XScale instructions. Also sorted arithmetic before move. */
@@ -6829,8 +6572,8 @@
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
- CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), swap),
- CM(swp,b, 1400090, 3, (RRnpc, RRnpc, RRnpcb), swap),
+ CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
+ CM(swp,b, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
@@ -6867,7 +6610,7 @@
/* Note: blx has 2 variants; the .value coded here is for
BLX(2). Only this variant has conditional execution. */
CE(blx, 12fff30, 1, (RR_EXr), blx),
- CE(clz, 16f0f10, 2, (RRnpc, RRnpc), clz),
+ CE(clz, 16f0f10, 2, (RRnpc, RRnpc), rd_rm),
UE(bkpt, 1200070, 1, (oIffffb), bkpt),
UF(ldc2, c100000, 3, (RCP, RCN, ADDR), lstc),
UF(ldc2l, c500000, 3, (RCP, RCN, ADDR), lstc),
@@ -6900,10 +6643,10 @@
CE(smulwb, 12000a0, 3, (RRnpc, RRnpc, RRnpc), smul),
CE(smulwt, 12000e0, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(qadd, 1000050, 3, (RRnpc, RRnpc, RRnpc), qadd),
- CE(qdadd, 1400050, 3, (RRnpc, RRnpc, RRnpc), qadd),
- CE(qsub, 1200050, 3, (RRnpc, RRnpc, RRnpc), qadd),
- CE(qdsub, 1600050, 3, (RRnpc, RRnpc, RRnpc), qadd),
+ CE(qadd, 1000050, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn),
+ CE(qdadd, 1400050, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn),
+ CE(qsub, 1200050, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn),
+ CE(qdsub, 1600050, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
@@ -6920,53 +6663,53 @@
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
- UF(cps, 1020000, 1, (I31b), cps),
+ UF(cps, 1020000, 1, (I31b), imm0),
UF(cpsie, 1080000, 2, (CPSF, oI31b), cpsi),
UF(cpsid, 10c0000, 2, (CPSF, oI31b), cpsi),
- CE(ldrex, 1900f9f, 2, (RRnpc, RRnpcb), ldrex),
+ CE(ldrex, 1900f9f, 2, (RRnpc, RRnpcb), rd_rn),
UF(mcrr2, c400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
UF(mrrc2, c500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
CE(pkhbt, 6800010, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt),
CE(pkhtb, 6800050, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb),
- CE(qadd16, 6200f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qadd8, 6200f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qaddsubx, 6200f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qsub16, 6200f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qsub8, 6200ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qsubaddx, 6200f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(sadd16, 6100f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(sadd8, 6100f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(saddsubx, 6100f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shadd16, 6300f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shadd8, 6300f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shaddsubx, 6300f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shsub16, 6300f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shsub8, 6300ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shsubaddx, 6300f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(ssub16, 6100f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(ssub8, 6100ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(ssubaddx, 6100f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uadd16, 6500f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uadd8, 6500f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uaddsubx, 6500f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhadd16, 6700f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhadd8, 6700f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhaddsubx, 6700f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhsub16, 6700f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhsub8, 6700ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhsubaddx, 6700f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqadd16, 6600f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqadd8, 6600f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqaddsubx, 6600f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqsub16, 6600f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqsub8, 6600ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqsubaddx, 6600f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(usub16, 6500f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(usub8, 6500ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(usubaddx, 6500f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(rev, 6bf0f30, 2, (RRnpc, RRnpc), rev),
- CE(rev16, 6bf0fb0, 2, (RRnpc, RRnpc), rev),
- CE(revsh, 6ff0fb0, 2, (RRnpc, RRnpc), rev),
+ CE(qadd16, 6200f10, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(qadd8, 6200f90, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(qaddsubx, 6200f30, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(qsub16, 6200f70, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(qsub8, 6200ff0, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(qsubaddx, 6200f50, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(sadd16, 6100f10, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(sadd8, 6100f90, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(saddsubx, 6100f30, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(shadd16, 6300f10, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(shadd8, 6300f90, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(shaddsubx, 6300f30, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(shsub16, 6300f70, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(shsub8, 6300ff0, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(shsubaddx, 6300f50, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(ssub16, 6100f70, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(ssub8, 6100ff0, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(ssubaddx, 6100f50, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uadd16, 6500f10, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uadd8, 6500f90, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uaddsubx, 6500f30, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uhadd16, 6700f10, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uhadd8, 6700f90, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uhaddsubx, 6700f30, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uhsub16, 6700f70, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uhsub8, 6700ff0, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uhsubaddx, 6700f50, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uqadd16, 6600f10, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uqadd8, 6600f90, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uqaddsubx, 6600f30, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uqsub16, 6600f70, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uqsub8, 6600ff0, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(uqsubaddx, 6600f50, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(usub16, 6500f70, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(usub8, 6500ff0, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(usubaddx, 6500f50, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
+ CE(rev, 6bf0f30, 2, (RRnpc, RRnpc), rd_rm),
+ CE(rev16, 6bf0fb0, 2, (RRnpc, RRnpc), rd_rm),
+ CE(revsh, 6ff0fb0, 2, (RRnpc, RRnpc), rd_rm),
UF(rfeia, 8900a00, 1, (RRw), rfe),
UF(rfeib, 9900a00, 1, (RRw), rfe),
UF(rfeda, 8100a00, 1, (RRw), rfe),
@@ -6987,7 +6730,7 @@
CE(uxth, 6ff0070, 3, (RRnpc, RRnpc, oROR), sxth),
CE(uxtb16, 6cf0070, 3, (RRnpc, RRnpc, oROR), sxth),
CE(uxtb, 6ef0070, 3, (RRnpc, RRnpc, oROR), sxth),
- CE(sel, 68000b0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(sel, 68000b0, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm),
UF(setend, 1010000, 1, (ENDI), setend),
CE(smlad, 7000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
CE(smladx, 7000030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
@@ -7022,17 +6765,17 @@
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6K
- CE(ldrexb, 1d00f9f, 2, (RRnpc, RRnpcb), ldrex),
- CE(ldrexd, 1b00f9f, 2, (RRnpc, RRnpcb), ldrex),
- CE(ldrexh, 1f00f9f, 2, (RRnpc, RRnpcb), ldrex),
+ CE(ldrexb, 1d00f9f, 2, (RRnpc, RRnpcb), rd_rn),
+ CE(ldrexd, 1b00f9f, 2, (RRnpc, RRnpcb), rd_rn),
+ CE(ldrexh, 1f00f9f, 2, (RRnpc, RRnpcb), rd_rn),
CE(strexb, 1c00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
CE(strexd, 1a00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
CE(strexh, 1e00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
- UF(clrex, 57ff01f, 0, (), empty),
- CE(wfe, 320f002, 0, (), empty),
- CE(wfi, 320f003, 0, (), empty),
- CE(yield, 320f001, 0, (), empty),
- CE(sev, 320f004, 0, (), empty),
+ UF(clrex, 57ff01f, 0, (), noargs),
+ CE(wfe, 320f002, 0, (), noargs),
+ CE(wfi, 320f003, 0, (), noargs),
+ CE(yield, 320f001, 0, (), noargs),
+ CE(sev, 320f004, 0, (), noargs),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6Z
@@ -7048,7 +6791,7 @@
CE(mls, 0600090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
CE(movw, 3000000, 2, (RRnpc, Iffff), mov16),
CE(movt, 3400000, 2, (RRnpc, Iffff), mov16),
- CE(rbit, 3ff0f30, 2, (RR, RR), rbit),
+ CE(rbit, 3ff0f30, 2, (RR, RR), rd_rm),
CM(ldr,ht, 03000b0, 2, (RR, ADDR), ldsttv4),
CM(ldr,sht, 03000f0, 2, (RR, ADDR), ldsttv4),
@@ -7057,397 +6800,397 @@
#undef ARM_VARIANT
#define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
- CE(wfs, e200110, 1, (RR), fpa_ctrl),
- CE(rfs, e300110, 1, (RR), fpa_ctrl),
- CE(wfc, e400110, 1, (RR), fpa_ctrl),
- CE(rfc, e500110, 1, (RR), fpa_ctrl),
+ CE(wfs, e200110, 1, (RR), rd),
+ CE(rfs, e300110, 1, (RR), rd),
+ CE(wfc, e400110, 1, (RR), rd),
+ CE(rfc, e500110, 1, (RR), rd),
- CM(ldf,s, c100100, 2, (RF, ADDR), fpa_ldst),
- CM(ldf,d, c108100, 2, (RF, ADDR), fpa_ldst),
- CM(ldf,e, c500100, 2, (RF, ADDR), fpa_ldst),
- CM(ldf,p, c508100, 2, (RF, ADDR), fpa_ldst),
+ CM(ldf,s, c100100, 2, (RF, ADDR), rd_cpaddr),
+ CM(ldf,d, c108100, 2, (RF, ADDR), rd_cpaddr),
+ CM(ldf,e, c500100, 2, (RF, ADDR), rd_cpaddr),
+ CM(ldf,p, c508100, 2, (RF, ADDR), rd_cpaddr),
- CM(stf,s, c000100, 2, (RF, ADDR), fpa_ldst),
- CM(stf,d, c008100, 2, (RF, ADDR), fpa_ldst),
- CM(stf,e, c400100, 2, (RF, ADDR), fpa_ldst),
- CM(stf,p, c408100, 2, (RF, ADDR), fpa_ldst),
+ CM(stf,s, c000100, 2, (RF, ADDR), rd_cpaddr),
+ CM(stf,d, c008100, 2, (RF, ADDR), rd_cpaddr),
+ CM(stf,e, c400100, 2, (RF, ADDR), rd_cpaddr),
+ CM(stf,p, c408100, 2, (RF, ADDR), rd_cpaddr),
- CM(mvf,s, e008100, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,sp, e008120, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,sm, e008140, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,sz, e008160, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,d, e008180, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,dp, e0081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,dm, e0081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,dz, e0081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,e, e088100, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,ep, e088120, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,em, e088140, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,ez, e088160, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,s, e008100, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,sp, e008120, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,sm, e008140, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,sz, e008160, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,d, e008180, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,dp, e0081a0, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,dm, e0081c0, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,dz, e0081e0, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,e, e088100, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,ep, e088120, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,em, e088140, 2, (RF, RF_IF), rd_rm),
+ CM(mvf,ez, e088160, 2, (RF, RF_IF), rd_rm),
- CM(mnf,s, e108100, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,sp, e108120, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,sm, e108140, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,sz, e108160, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,d, e108180, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,dp, e1081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,dm, e1081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,dz, e1081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,e, e188100, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,ep, e188120, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,em, e188140, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,ez, e188160, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,s, e108100, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,sp, e108120, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,sm, e108140, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,sz, e108160, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,d, e108180, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,dp, e1081a0, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,dm, e1081c0, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,dz, e1081e0, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,e, e188100, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,ep, e188120, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,em, e188140, 2, (RF, RF_IF), rd_rm),
+ CM(mnf,ez, e188160, 2, (RF, RF_IF), rd_rm),
- CM(abs,s, e208100, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,sp, e208120, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,sm, e208140, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,sz, e208160, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,d, e208180, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,dp, e2081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,dm, e2081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,dz, e2081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,e, e288100, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,ep, e288120, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,em, e288140, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,ez, e288160, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,s, e208100, 2, (RF, RF_IF), rd_rm),
+ CM(abs,sp, e208120, 2, (RF, RF_IF), rd_rm),
+ CM(abs,sm, e208140, 2, (RF, RF_IF), rd_rm),
+ CM(abs,sz, e208160, 2, (RF, RF_IF), rd_rm),
+ CM(abs,d, e208180, 2, (RF, RF_IF), rd_rm),
+ CM(abs,dp, e2081a0, 2, (RF, RF_IF), rd_rm),
+ CM(abs,dm, e2081c0, 2, (RF, RF_IF), rd_rm),
+ CM(abs,dz, e2081e0, 2, (RF, RF_IF), rd_rm),
+ CM(abs,e, e288100, 2, (RF, RF_IF), rd_rm),
+ CM(abs,ep, e288120, 2, (RF, RF_IF), rd_rm),
+ CM(abs,em, e288140, 2, (RF, RF_IF), rd_rm),
+ CM(abs,ez, e288160, 2, (RF, RF_IF), rd_rm),
- CM(rnd,s, e308100, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,sp, e308120, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,sm, e308140, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,sz, e308160, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,d, e308180, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,dp, e3081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,dm, e3081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,dz, e3081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,e, e388100, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,ep, e388120, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,em, e388140, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,ez, e388160, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,s, e308100, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,sp, e308120, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,sm, e308140, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,sz, e308160, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,d, e308180, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,dp, e3081a0, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,dm, e3081c0, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,dz, e3081e0, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,e, e388100, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,ep, e388120, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,em, e388140, 2, (RF, RF_IF), rd_rm),
+ CM(rnd,ez, e388160, 2, (RF, RF_IF), rd_rm),
- CM(sqt,s, e408100, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,sp, e408120, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,sm, e408140, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,sz, e408160, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,d, e408180, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,dp, e4081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,dm, e4081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,dz, e4081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,e, e488100, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,ep, e488120, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,em, e488140, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,ez, e488160, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,s, e408100, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,sp, e408120, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,sm, e408140, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,sz, e408160, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,d, e408180, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,dp, e4081a0, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,dm, e4081c0, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,dz, e4081e0, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,e, e488100, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,ep, e488120, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,em, e488140, 2, (RF, RF_IF), rd_rm),
+ CM(sqt,ez, e488160, 2, (RF, RF_IF), rd_rm),
- CM(log,s, e508100, 2, (RF, RF_IF), fpa_monadic),
- CM(log,sp, e508120, 2, (RF, RF_IF), fpa_monadic),
- CM(log,sm, e508140, 2, (RF, RF_IF), fpa_monadic),
- CM(log,sz, e508160, 2, (RF, RF_IF), fpa_monadic),
- CM(log,d, e508180, 2, (RF, RF_IF), fpa_monadic),
- CM(log,dp, e5081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(log,dm, e5081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(log,dz, e5081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(log,e, e588100, 2, (RF, RF_IF), fpa_monadic),
- CM(log,ep, e588120, 2, (RF, RF_IF), fpa_monadic),
- CM(log,em, e588140, 2, (RF, RF_IF), fpa_monadic),
- CM(log,ez, e588160, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,s, e508100, 2, (RF, RF_IF), rd_rm),
+ CM(log,sp, e508120, 2, (RF, RF_IF), rd_rm),
+ CM(log,sm, e508140, 2, (RF, RF_IF), rd_rm),
+ CM(log,sz, e508160, 2, (RF, RF_IF), rd_rm),
+ CM(log,d, e508180, 2, (RF, RF_IF), rd_rm),
+ CM(log,dp, e5081a0, 2, (RF, RF_IF), rd_rm),
+ CM(log,dm, e5081c0, 2, (RF, RF_IF), rd_rm),
+ CM(log,dz, e5081e0, 2, (RF, RF_IF), rd_rm),
+ CM(log,e, e588100, 2, (RF, RF_IF), rd_rm),
+ CM(log,ep, e588120, 2, (RF, RF_IF), rd_rm),
+ CM(log,em, e588140, 2, (RF, RF_IF), rd_rm),
+ CM(log,ez, e588160, 2, (RF, RF_IF), rd_rm),
- CM(lgn,s, e608100, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,sp, e608120, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,sm, e608140, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,sz, e608160, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,d, e608180, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,dp, e6081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,dm, e6081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,dz, e6081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,e, e688100, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,ep, e688120, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,em, e688140, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,ez, e688160, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,s, e608100, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,sp, e608120, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,sm, e608140, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,sz, e608160, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,d, e608180, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,dp, e6081a0, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,dm, e6081c0, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,dz, e6081e0, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,e, e688100, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,ep, e688120, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,em, e688140, 2, (RF, RF_IF), rd_rm),
+ CM(lgn,ez, e688160, 2, (RF, RF_IF), rd_rm),
- CM(exp,s, e708100, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,sp, e708120, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,sm, e708140, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,sz, e708160, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,d, e708180, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,dp, e7081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,dm, e7081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,dz, e7081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,e, e788100, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,ep, e788120, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,em, e788140, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,dz, e788160, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,s, e708100, 2, (RF, RF_IF), rd_rm),
+ CM(exp,sp, e708120, 2, (RF, RF_IF), rd_rm),
+ CM(exp,sm, e708140, 2, (RF, RF_IF), rd_rm),
+ CM(exp,sz, e708160, 2, (RF, RF_IF), rd_rm),
+ CM(exp,d, e708180, 2, (RF, RF_IF), rd_rm),
+ CM(exp,dp, e7081a0, 2, (RF, RF_IF), rd_rm),
+ CM(exp,dm, e7081c0, 2, (RF, RF_IF), rd_rm),
+ CM(exp,dz, e7081e0, 2, (RF, RF_IF), rd_rm),
+ CM(exp,e, e788100, 2, (RF, RF_IF), rd_rm),
+ CM(exp,ep, e788120, 2, (RF, RF_IF), rd_rm),
+ CM(exp,em, e788140, 2, (RF, RF_IF), rd_rm),
+ CM(exp,dz, e788160, 2, (RF, RF_IF), rd_rm),
- CM(sin,s, e808100, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,sp, e808120, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,sm, e808140, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,sz, e808160, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,d, e808180, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,dp, e8081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,dm, e8081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,dz, e8081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,e, e888100, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,ep, e888120, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,em, e888140, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,ez, e888160, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,s, e808100, 2, (RF, RF_IF), rd_rm),
+ CM(sin,sp, e808120, 2, (RF, RF_IF), rd_rm),
+ CM(sin,sm, e808140, 2, (RF, RF_IF), rd_rm),
+ CM(sin,sz, e808160, 2, (RF, RF_IF), rd_rm),
+ CM(sin,d, e808180, 2, (RF, RF_IF), rd_rm),
+ CM(sin,dp, e8081a0, 2, (RF, RF_IF), rd_rm),
+ CM(sin,dm, e8081c0, 2, (RF, RF_IF), rd_rm),
+ CM(sin,dz, e8081e0, 2, (RF, RF_IF), rd_rm),
+ CM(sin,e, e888100, 2, (RF, RF_IF), rd_rm),
+ CM(sin,ep, e888120, 2, (RF, RF_IF), rd_rm),
+ CM(sin,em, e888140, 2, (RF, RF_IF), rd_rm),
+ CM(sin,ez, e888160, 2, (RF, RF_IF), rd_rm),
- CM(cos,s, e908100, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,sp, e908120, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,sm, e908140, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,sz, e908160, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,d, e908180, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,dp, e9081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,dm, e9081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,dz, e9081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,e, e988100, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,ep, e988120, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,em, e988140, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,ez, e988160, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,s, e908100, 2, (RF, RF_IF), rd_rm),
+ CM(cos,sp, e908120, 2, (RF, RF_IF), rd_rm),
+ CM(cos,sm, e908140, 2, (RF, RF_IF), rd_rm),
+ CM(cos,sz, e908160, 2, (RF, RF_IF), rd_rm),
+ CM(cos,d, e908180, 2, (RF, RF_IF), rd_rm),
+ CM(cos,dp, e9081a0, 2, (RF, RF_IF), rd_rm),
+ CM(cos,dm, e9081c0, 2, (RF, RF_IF), rd_rm),
+ CM(cos,dz, e9081e0, 2, (RF, RF_IF), rd_rm),
+ CM(cos,e, e988100, 2, (RF, RF_IF), rd_rm),
+ CM(cos,ep, e988120, 2, (RF, RF_IF), rd_rm),
+ CM(cos,em, e988140, 2, (RF, RF_IF), rd_rm),
+ CM(cos,ez, e988160, 2, (RF, RF_IF), rd_rm),
- CM(tan,s, ea08100, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,sp, ea08120, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,sm, ea08140, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,sz, ea08160, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,d, ea08180, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,dp, ea081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,dm, ea081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,dz, ea081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,e, ea88100, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,ep, ea88120, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,em, ea88140, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,ez, ea88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,s, ea08100, 2, (RF, RF_IF), rd_rm),
+ CM(tan,sp, ea08120, 2, (RF, RF_IF), rd_rm),
+ CM(tan,sm, ea08140, 2, (RF, RF_IF), rd_rm),
+ CM(tan,sz, ea08160, 2, (RF, RF_IF), rd_rm),
+ CM(tan,d, ea08180, 2, (RF, RF_IF), rd_rm),
+ CM(tan,dp, ea081a0, 2, (RF, RF_IF), rd_rm),
+ CM(tan,dm, ea081c0, 2, (RF, RF_IF), rd_rm),
+ CM(tan,dz, ea081e0, 2, (RF, RF_IF), rd_rm),
+ CM(tan,e, ea88100, 2, (RF, RF_IF), rd_rm),
+ CM(tan,ep, ea88120, 2, (RF, RF_IF), rd_rm),
+ CM(tan,em, ea88140, 2, (RF, RF_IF), rd_rm),
+ CM(tan,ez, ea88160, 2, (RF, RF_IF), rd_rm),
- CM(asn,s, eb08100, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,sp, eb08120, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,sm, eb08140, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,sz, eb08160, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,d, eb08180, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,dp, eb081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,dm, eb081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,dz, eb081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,e, eb88100, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,ep, eb88120, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,em, eb88140, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,ez, eb88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,s, eb08100, 2, (RF, RF_IF), rd_rm),
+ CM(asn,sp, eb08120, 2, (RF, RF_IF), rd_rm),
+ CM(asn,sm, eb08140, 2, (RF, RF_IF), rd_rm),
+ CM(asn,sz, eb08160, 2, (RF, RF_IF), rd_rm),
+ CM(asn,d, eb08180, 2, (RF, RF_IF), rd_rm),
+ CM(asn,dp, eb081a0, 2, (RF, RF_IF), rd_rm),
+ CM(asn,dm, eb081c0, 2, (RF, RF_IF), rd_rm),
+ CM(asn,dz, eb081e0, 2, (RF, RF_IF), rd_rm),
+ CM(asn,e, eb88100, 2, (RF, RF_IF), rd_rm),
+ CM(asn,ep, eb88120, 2, (RF, RF_IF), rd_rm),
+ CM(asn,em, eb88140, 2, (RF, RF_IF), rd_rm),
+ CM(asn,ez, eb88160, 2, (RF, RF_IF), rd_rm),
- CM(acs,s, ec08100, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,sp, ec08120, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,sm, ec08140, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,sz, ec08160, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,d, ec08180, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,dp, ec081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,dm, ec081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,dz, ec081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,e, ec88100, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,ep, ec88120, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,em, ec88140, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,ez, ec88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,s, ec08100, 2, (RF, RF_IF), rd_rm),
+ CM(acs,sp, ec08120, 2, (RF, RF_IF), rd_rm),
+ CM(acs,sm, ec08140, 2, (RF, RF_IF), rd_rm),
+ CM(acs,sz, ec08160, 2, (RF, RF_IF), rd_rm),
+ CM(acs,d, ec08180, 2, (RF, RF_IF), rd_rm),
+ CM(acs,dp, ec081a0, 2, (RF, RF_IF), rd_rm),
+ CM(acs,dm, ec081c0, 2, (RF, RF_IF), rd_rm),
+ CM(acs,dz, ec081e0, 2, (RF, RF_IF), rd_rm),
+ CM(acs,e, ec88100, 2, (RF, RF_IF), rd_rm),
+ CM(acs,ep, ec88120, 2, (RF, RF_IF), rd_rm),
+ CM(acs,em, ec88140, 2, (RF, RF_IF), rd_rm),
+ CM(acs,ez, ec88160, 2, (RF, RF_IF), rd_rm),
- CM(atn,s, ed08100, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,sp, ed08120, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,sm, ed08140, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,sz, ed08160, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,d, ed08180, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,dp, ed081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,dm, ed081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,dz, ed081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,e, ed88100, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,ep, ed88120, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,em, ed88140, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,ez, ed88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,s, ed08100, 2, (RF, RF_IF), rd_rm),
+ CM(atn,sp, ed08120, 2, (RF, RF_IF), rd_rm),
+ CM(atn,sm, ed08140, 2, (RF, RF_IF), rd_rm),
+ CM(atn,sz, ed08160, 2, (RF, RF_IF), rd_rm),
+ CM(atn,d, ed08180, 2, (RF, RF_IF), rd_rm),
+ CM(atn,dp, ed081a0, 2, (RF, RF_IF), rd_rm),
+ CM(atn,dm, ed081c0, 2, (RF, RF_IF), rd_rm),
+ CM(atn,dz, ed081e0, 2, (RF, RF_IF), rd_rm),
+ CM(atn,e, ed88100, 2, (RF, RF_IF), rd_rm),
+ CM(atn,ep, ed88120, 2, (RF, RF_IF), rd_rm),
+ CM(atn,em, ed88140, 2, (RF, RF_IF), rd_rm),
+ CM(atn,ez, ed88160, 2, (RF, RF_IF), rd_rm),
- CM(urd,s, ee08100, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,sp, ee08120, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,sm, ee08140, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,sz, ee08160, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,d, ee08180, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,dp, ee081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,dm, ee081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,dz, ee081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,e, ee88100, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,ep, ee88120, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,em, ee88140, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,ez, ee88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,s, ee08100, 2, (RF, RF_IF), rd_rm),
+ CM(urd,sp, ee08120, 2, (RF, RF_IF), rd_rm),
+ CM(urd,sm, ee08140, 2, (RF, RF_IF), rd_rm),
+ CM(urd,sz, ee08160, 2, (RF, RF_IF), rd_rm),
+ CM(urd,d, ee08180, 2, (RF, RF_IF), rd_rm),
+ CM(urd,dp, ee081a0, 2, (RF, RF_IF), rd_rm),
+ CM(urd,dm, ee081c0, 2, (RF, RF_IF), rd_rm),
+ CM(urd,dz, ee081e0, 2, (RF, RF_IF), rd_rm),
+ CM(urd,e, ee88100, 2, (RF, RF_IF), rd_rm),
+ CM(urd,ep, ee88120, 2, (RF, RF_IF), rd_rm),
+ CM(urd,em, ee88140, 2, (RF, RF_IF), rd_rm),
+ CM(urd,ez, ee88160, 2, (RF, RF_IF), rd_rm),
- CM(nrm,s, ef08100, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,sp, ef08120, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,sm, ef08140, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,sz, ef08160, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,d, ef08180, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,dp, ef081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,dm, ef081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,dz, ef081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,e, ef88100, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,ep, ef88120, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,em, ef88140, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,ez, ef88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,s, ef08100, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,sp, ef08120, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,sm, ef08140, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,sz, ef08160, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,d, ef08180, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,dp, ef081a0, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,dm, ef081c0, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,dz, ef081e0, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,e, ef88100, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,ep, ef88120, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,em, ef88140, 2, (RF, RF_IF), rd_rm),
+ CM(nrm,ez, ef88160, 2, (RF, RF_IF), rd_rm),
- CM(adf,s, e000100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,sp, e000120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,sm, e000140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,sz, e000160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,d, e000180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,dp, e0001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,dm, e0001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,dz, e0001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,e, e080100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,ep, e080120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,em, e080140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,ez, e080160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,s, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,sp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,sm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,sz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,d, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,dp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,dm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,dz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,e, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,ep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,em, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(adf,ez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(suf,s, e200100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,sp, e200120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,sm, e200140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,sz, e200160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,d, e200180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,dp, e2001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,dm, e2001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,dz, e2001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,e, e280100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,ep, e280120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,em, e280140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,ez, e280160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,s, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,sp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,sm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,sz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,d, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,dp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,dm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,dz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,e, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,ep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,em, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(suf,ez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(rsf,s, e300100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,sp, e300120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,sm, e300140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,sz, e300160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,d, e300180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,dp, e3001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,dm, e3001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,dz, e3001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,e, e380100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,ep, e380120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,em, e380140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,ez, e380160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,s, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,sp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,sm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,sz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,d, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,dp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,dm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,dz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,e, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,ep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,em, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rsf,ez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(muf,s, e100100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,sp, e100120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,sm, e100140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,sz, e100160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,d, e100180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,dp, e1001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,dm, e1001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,dz, e1001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,e, e180100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,ep, e180120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,em, e180140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,ez, e180160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,s, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,sp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,sm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,sz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,d, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,dp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,dm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,dz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,e, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,ep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,em, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(muf,ez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(dvf,s, e400100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,sp, e400120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,sm, e400140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,sz, e400160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,d, e400180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,dp, e4001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,dm, e4001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,dz, e4001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,e, e480100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,ep, e480120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,em, e480140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,ez, e480160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,s, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,sp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,sm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,sz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,d, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,dp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,dm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,dz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,e, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,ep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,em, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(dvf,ez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(rdf,s, e500100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,sp, e500120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,sm, e500140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,sz, e500160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,d, e500180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,dp, e5001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,dm, e5001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,dz, e5001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,e, e580100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,ep, e580120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,em, e580140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,ez, e580160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,s, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,sp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,sm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,sz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,d, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,dp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,dm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,dz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,e, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,ep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,em, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rdf,ez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(pow,s, e600100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,sp, e600120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,sm, e600140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,sz, e600160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,d, e600180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,dp, e6001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,dm, e6001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,dz, e6001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,e, e680100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,ep, e680120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,em, e680140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,ez, e680160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,s, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,sp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,sm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,sz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,d, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,dp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,dm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,dz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,e, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,ep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,em, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pow,ez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(rpw,s, e700100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,sp, e700120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,sm, e700140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,sz, e700160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,d, e700180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,dp, e7001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,dm, e7001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,dz, e7001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,e, e780100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,ep, e780120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,em, e780140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,ez, e780160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,s, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,sp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,sm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,sz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,d, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,dp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,dm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,dz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,e, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,ep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,em, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rpw,ez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(rmf,s, e800100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,sp, e800120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,sm, e800140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,sz, e800160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,d, e800180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,dp, e8001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,dm, e8001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,dz, e8001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,e, e880100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,ep, e880120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,em, e880140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,ez, e880160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,s, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,sp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,sm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,sz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,d, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,dp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,dm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,dz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,e, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,ep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,em, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(rmf,ez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(fml,s, e900100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,sp, e900120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,sm, e900140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,sz, e900160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,d, e900180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,dp, e9001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,dm, e9001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,dz, e9001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,e, e980100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,ep, e980120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,em, e980140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,ez, e980160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,s, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,sp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,sm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,sz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,d, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,dp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,dm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,dz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,e, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,ep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,em, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fml,ez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(fdv,s, ea00100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,sp, ea00120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,sm, ea00140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,sz, ea00160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,d, ea00180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,dp, ea001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,dm, ea001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,dz, ea001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,e, ea80100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,ep, ea80120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,em, ea80140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,ez, ea80160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,s, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,sp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,sm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,sz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,d, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,dp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,dm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,dz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,e, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,ep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,em, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(fdv,ez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(frd,s, eb00100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,sp, eb00120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,sm, eb00140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,sz, eb00160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,d, eb00180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,dp, eb001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,dm, eb001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,dz, eb001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,e, eb80100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,ep, eb80120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,em, eb80140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,ez, eb80160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,s, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,sp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,sm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,sz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,d, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,dp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,dm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,dz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,e, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,ep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,em, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(frd,ez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
- CM(pol,s, ec00100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,sp, ec00120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,sm, ec00140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,sz, ec00160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,d, ec00180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,dp, ec001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,dm, ec001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,dz, ec001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,e, ec80100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,ep, ec80120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,em, ec80140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,ez, ec80160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,s, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,sp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,sm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,sz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,d, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,dp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,dm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,dz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,e, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,ep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,em, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ CM(pol,ez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
CM(cmf,e, ed0f110, 2, (RF, RF_IF), fpa_cmp),
@@ -7459,37 +7202,37 @@
CE(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
CE(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
- CM(flt,s, e000110, 2, (RF, RR), fpa_from_reg),
- CM(flt,sp, e000130, 2, (RF, RR), fpa_from_reg),
- CM(flt,sm, e000150, 2, (RF, RR), fpa_from_reg),
- CM(flt,sz, e000170, 2, (RF, RR), fpa_from_reg),
- CM(flt,d, e000190, 2, (RF, RR), fpa_from_reg),
- CM(flt,dp, e0001b0, 2, (RF, RR), fpa_from_reg),
- CM(flt,dm, e0001d0, 2, (RF, RR), fpa_from_reg),
- CM(flt,dz, e0001f0, 2, (RF, RR), fpa_from_reg),
- CM(flt,e, e080110, 2, (RF, RR), fpa_from_reg),
- CM(flt,ep, e080130, 2, (RF, RR), fpa_from_reg),
- CM(flt,em, e080150, 2, (RF, RR), fpa_from_reg),
- CM(flt,ez, e080170, 2, (RF, RR), fpa_from_reg),
+ CM(flt,s, e000110, 2, (RF, RR), rn_rd),
+ CM(flt,sp, e000130, 2, (RF, RR), rn_rd),
+ CM(flt,sm, e000150, 2, (RF, RR), rn_rd),
+ CM(flt,sz, e000170, 2, (RF, RR), rn_rd),
+ CM(flt,d, e000190, 2, (RF, RR), rn_rd),
+ CM(flt,dp, e0001b0, 2, (RF, RR), rn_rd),
+ CM(flt,dm, e0001d0, 2, (RF, RR), rn_rd),
+ CM(flt,dz, e0001f0, 2, (RF, RR), rn_rd),
+ CM(flt,e, e080110, 2, (RF, RR), rn_rd),
+ CM(flt,ep, e080130, 2, (RF, RR), rn_rd),
+ CM(flt,em, e080150, 2, (RF, RR), rn_rd),
+ CM(flt,ez, e080170, 2, (RF, RR), rn_rd),
/* The implementation of the FIX instruction is broken on some
assemblers, in that it accepts a precision specifier as well as a
rounding specifier, despite the fact that this is meaningless.
To be more compatible, we accept it as well, though of course it
does not set any bits. */
- CE(fix, e100110, 2, (RR, RF), fpa_to_reg),
- CM(fix,p, e100130, 2, (RR, RF), fpa_to_reg),
- CM(fix,m, e100150, 2, (RR, RF), fpa_to_reg),
- CM(fix,z, e100170, 2, (RR, RF), fpa_to_reg),
- CM(fix,sp, e100130, 2, (RR, RF), fpa_to_reg),
- CM(fix,sm, e100150, 2, (RR, RF), fpa_to_reg),
- CM(fix,sz, e100170, 2, (RR, RF), fpa_to_reg),
- CM(fix,dp, e100130, 2, (RR, RF), fpa_to_reg),
- CM(fix,dm, e100150, 2, (RR, RF), fpa_to_reg),
- CM(fix,dz, e100170, 2, (RR, RF), fpa_to_reg),
- CM(fix,ep, e100130, 2, (RR, RF), fpa_to_reg),
- CM(fix,em, e100150, 2, (RR, RF), fpa_to_reg),
- CM(fix,ez, e100170, 2, (RR, RF), fpa_to_reg),
+ CE(fix, e100110, 2, (RR, RF), rd_rm),
+ CM(fix,p, e100130, 2, (RR, RF), rd_rm),
+ CM(fix,m, e100150, 2, (RR, RF), rd_rm),
+ CM(fix,z, e100170, 2, (RR, RF), rd_rm),
+ CM(fix,sp, e100130, 2, (RR, RF), rd_rm),
+ CM(fix,sm, e100150, 2, (RR, RF), rd_rm),
+ CM(fix,sz, e100170, 2, (RR, RF), rd_rm),
+ CM(fix,dp, e100130, 2, (RR, RF), rd_rm),
+ CM(fix,dm, e100150, 2, (RR, RF), rd_rm),
+ CM(fix,dz, e100170, 2, (RR, RF), rd_rm),
+ CM(fix,ep, e100130, 2, (RR, RF), rd_rm),
+ CM(fix,em, e100150, 2, (RR, RF), rd_rm),
+ CM(fix,ez, e100170, 2, (RR, RF), rd_rm),
/* Instructions that were new with the real FPA, call them V2. */
#undef ARM_VARIANT
@@ -7507,15 +7250,15 @@
CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
- CE(fmstat, ef1fa10, 0, (), empty),
+ CE(fmstat, ef1fa10, 0, (), noargs),
CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fmrx, ef00a10, 2, (RR, RVC), vfp_reg_from_ctrl),
- CE(fmxr, ee00a10, 2, (RVC, RR), vfp_ctrl_from_reg),
+ CE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
+ CE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
/* Memory operations. */
CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
@@ -7562,13 +7305,13 @@
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
/* Moves and type conversions. */
- CE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
- CE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_from_reg),
- CE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_from_reg),
- CE(fmrdh, e300b10, 2, (RR, RVD), vfp_reg_from_dp),
- CE(fmrdl, e100b10, 2, (RR, RVD), vfp_reg_from_dp),
+ CE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
+ CE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
+ CE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
+ CE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
@@ -7589,33 +7332,33 @@
CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
/* Monadic operations. */
- CE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_monadic),
- CE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_monadic),
- CE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
+ CE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
+ CE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
/* Dyadic operations. */
- CE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ CE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
+ CE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ CE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ CE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ CE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
+ CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
+ CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
/* Comparisons. */
- CE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_monadic),
- CE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_compare_z),
- CE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_monadic),
- CE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_compare_z),
+ CE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
+ CE(fcmpzd, eb50b40, 1, (RVD), rd),
+ CE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
+ CE(fcmpezd, eb50bc0, 1, (RVD), rd),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V2
CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
- CE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_from_reg2),
- CE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_reg2_from_dp),
+ CE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
+ CE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
@@ -7633,9 +7376,9 @@
CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
- CE(tbcstb, e400010, 2, (RR, RIWR), iwmmxt_tbcst),
- CE(tbcsth, e400050, 2, (RR, RIWR), iwmmxt_tbcst),
- CE(tbcstw, e400090, 2, (RR, RIWR), iwmmxt_tbcst),
+ CE(tbcstb, e400010, 2, (RR, RIWR), rd_rn),
+ CE(tbcsth, e400050, 2, (RR, RIWR), rd_rn),
+ CE(tbcstw, e400090, 2, (RR, RIWR), rd_rn),
CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
@@ -7648,225 +7391,225 @@
CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
- CE(tmcr, e000110, 2, (RIWC, RR), iwmmxt_tmcr),
- CE(tmcrr, c400000, 3, (RIWR, RR, RR), iwmmxt_tmcrr),
+ CE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
+ CE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmovmskb, e100030, 2, (RR, RIWR), iwmmxt_tmovmsk),
- CE(tmovmskh, e500030, 2, (RR, RIWR), iwmmxt_tmovmsk),
- CE(tmovmskw, e900030, 2, (RR, RIWR), iwmmxt_tmovmsk),
- CE(tmrc, e100110, 2, (RR, RIWC), iwmmxt_tmrc),
- CE(tmrrc, c500000, 3, (RR, RR, RIWR), iwmmxt_tmrrc),
+ CE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
+ CE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
+ CE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
+ CE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
+ CE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
CE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
- CE(waccb, e0001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wacch, e4001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(waccw, e8001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
+ CE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
+ CE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
+ CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
- CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wand, e200000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldst),
CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldst),
CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
- CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wor, e000000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
- CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldst),
CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldst),
CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
+ CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
- CE(cfldrs, c100400, 2, (RMF, ADDR), mav_ldst),
- CE(cfldrd, c500400, 2, (RMD, ADDR), mav_ldst),
- CE(cfldr32, c100500, 2, (RMFX, ADDR), mav_ldst),
- CE(cfldr64, c500500, 2, (RMDX, ADDR), mav_ldst),
- CE(cfstrs, c000400, 2, (RMF, ADDR), mav_ldst),
- CE(cfstrd, c400400, 2, (RMD, ADDR), mav_ldst),
- CE(cfstr32, c000500, 2, (RMFX, ADDR), mav_ldst),
- CE(cfstr64, c400500, 2, (RMDX, ADDR), mav_ldst),
- CE(cfmvsr, e000450, 2, (RMF, RR), mav_binops_2),
- CE(cfmvrs, e100450, 2, (RR, RMF), mav_binops_1),
- CE(cfmvdlr, e000410, 2, (RMD, RR), mav_binops_2),
- CE(cfmvrdl, e100410, 2, (RR, RMD), mav_binops_1),
- CE(cfmvdhr, e000430, 2, (RMD, RR), mav_binops_2),
- CE(cfmvrdh, e100430, 2, (RR, RMD), mav_binops_1),
- CE(cfmv64lr, e000510, 2, (RMDX, RR), mav_binops_2),
- CE(cfmvr64l, e100510, 2, (RR, RMDX), mav_binops_1),
- CE(cfmv64hr, e000530, 2, (RMDX, RR), mav_binops_2),
- CE(cfmvr64h, e100530, 2, (RR, RMDX), mav_binops_1),
- CE(cfmval32, e200440, 2, (RMAX, RMFX), mav_binops_1),
- CE(cfmv32al, e100440, 2, (RMFX, RMAX), mav_binops_1),
- CE(cfmvam32, e200460, 2, (RMAX, RMFX), mav_binops_1),
- CE(cfmv32am, e100460, 2, (RMFX, RMAX), mav_binops_1),
- CE(cfmvah32, e200480, 2, (RMAX, RMFX), mav_binops_1),
- CE(cfmv32ah, e100480, 2, (RMFX, RMAX), mav_binops_1),
- CE(cfmva32, e2004a0, 2, (RMAX, RMFX), mav_binops_1),
- CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), mav_binops_1),
- CE(cfmva64, e2004c0, 2, (RMAX, RMDX), mav_binops_1),
- CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), mav_binops_1),
- CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc_1),
- CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), mav_dspsc_0),
- CE(cfcpys, e000400, 2, (RMF, RMF), mav_binops_1),
- CE(cfcpyd, e000420, 2, (RMD, RMD), mav_binops_1),
- CE(cfcvtsd, e000460, 2, (RMD, RMF), mav_binops_1),
- CE(cfcvtds, e000440, 2, (RMF, RMD), mav_binops_1),
- CE(cfcvt32s, e000480, 2, (RMF, RMFX), mav_binops_1),
- CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), mav_binops_1),
- CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), mav_binops_1),
- CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), mav_binops_1),
- CE(cfcvts32, e100580, 2, (RMFX, RMF), mav_binops_1),
- CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), mav_binops_1),
- CE(cftruncs32,e1005c0, 2, (RMFX, RMF), mav_binops_1),
- CE(cftruncd32,e1005e0, 2, (RMFX, RMD), mav_binops_1),
- CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple_1),
- CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple_1),
+ CE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
+ CE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
+ CE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
+ CE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
+ CE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
+ CE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
+ CE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
+ CE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
+ CE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
+ CE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
+ CE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
+ CE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
+ CE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
+ CE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
+ CE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
+ CE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
+ CE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
+ CE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
+ CE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
+ CE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
+ CE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
+ CE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
+ CE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
+ CE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
+ CE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
+ CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
+ CE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
+ CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
+ CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
+ CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
+ CE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
+ CE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
+ CE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
+ CE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
+ CE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
+ CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
+ CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
+ CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
+ CE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
+ CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
+ CE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
+ CE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
+ CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
+ CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
- CE(cfcmps, e100490, 3, (RR, RMF, RMF), mav_triple_2),
- CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), mav_triple_2),
- CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), mav_triple_2),
- CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), mav_triple_2),
- CE(cfabss, e300400, 2, (RMF, RMF), mav_binops_1),
- CE(cfabsd, e300420, 2, (RMD, RMD), mav_binops_1),
- CE(cfnegs, e300440, 2, (RMF, RMF), mav_binops_1),
- CE(cfnegd, e300460, 2, (RMD, RMD), mav_binops_1),
- CE(cfadds, e300480, 3, (RMF, RMF, RMF), mav_triple_2),
- CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), mav_triple_2),
- CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), mav_triple_2),
- CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), mav_triple_2),
- CE(cfmuls, e100400, 3, (RMF, RMF, RMF), mav_triple_2),
- CE(cfmuld, e100420, 3, (RMD, RMD, RMD), mav_triple_2),
- CE(cfabs32, e300500, 2, (RMFX, RMFX), mav_binops_1),
- CE(cfabs64, e300520, 2, (RMDX, RMDX), mav_binops_1),
- CE(cfneg32, e300540, 2, (RMFX, RMFX), mav_binops_1),
- CE(cfneg64, e300560, 2, (RMDX, RMDX), mav_binops_1),
- CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), mav_triple_2),
- CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), mav_triple_2),
- CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), mav_triple_2),
- CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), mav_triple_2),
- CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), mav_triple_2),
- CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), mav_triple_2),
- CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), mav_triple_2),
- CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
+ CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
+ CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
+ CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
+ CE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
+ CE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
+ CE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
+ CE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
+ CE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
+ CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
+ CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
+ CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
+ CE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
+ CE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
+ CE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
+ CE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
+ CE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
+ CE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
+ CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
+ CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
+ CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
+ CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
+ CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
+ CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
+ CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
+ CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
CE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
@@ -7943,17 +7686,17 @@
TI(tst, 4200, 3, (RL, RL, oRL), t_arit),
/* Pseudo ops: */
TI(adr, 000f, 2, (RL, EXP), t_adr),
- TI(nop, 46c0, 0, (), empty), /* mov r8,r8 */
+ TI(nop, 46c0, 0, (), noargs), /* mov r8,r8 */
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V5T /* Thumb v2 (ARMv5T). */
TI(blx, 4780, 1, (RR_EX), t_blx),
- TI(bkpt, be00, 1, (oI255b), t_bkpt),
+ TI(bkpt, be00, 1, (oI255b), imm0),
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V6
- TI(cpsie, b660, 1, (CPSF), t_cps),
- TI(cpsid, b670, 1, (CPSF), t_cps),
+ TI(cpsie, b660, 1, (CPSF), imm0),
+ TI(cpsid, b670, 1, (CPSF), imm0),
TI(cpy, 4600, 2, (RR, RR), t_cpy),
TI(rev, ba00, 3, (RL, RL, oRL), t_arit),
TI(rev16, ba40, 3, (RL, RL, oRL), t_arit),
@@ -7966,10 +7709,10 @@
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V6K
- TI(sev, bf40, 0, (), empty),
- TI(wfe, bf20, 0, (), empty),
- TI(wfi, bf30, 0, (), empty),
- TI(yield, bf10, 0, (), empty),
+ TI(sev, bf40, 0, (), noargs),
+ TI(wfe, bf20, 0, (), noargs),
+ TI(wfi, bf30, 0, (), noargs),
+ TI(yield, bf10, 0, (), noargs),
};
#undef THUMB_VARIANT
#undef TI
@@ -10485,13 +10228,13 @@
};
/* ISA extensions in the co-processor space. */
-struct arm_arch_extension_table
+struct arm_option_value_table
{
char *name;
int value;
};
-static struct arm_arch_extension_table arm_extensions[] =
+static struct arm_option_value_table arm_extensions[] =
{
{"maverick", ARM_CEXT_MAVERICK},
{"xscale", ARM_CEXT_XSCALE},
@@ -10499,15 +10242,9 @@
{NULL, 0}
};
-struct arm_fpu_option_table
-{
- char *name;
- int value;
-};
-
/* This list should, at a minimum, contain all the fpu names
recognized by GCC. */
-static struct arm_fpu_option_table arm_fpus[] =
+static struct arm_option_value_table arm_fpus[] =
{
{"softfpa", FPU_NONE},
{"fpe", FPU_ARCH_FPE},
@@ -10532,29 +10269,17 @@
{NULL, 0}
};
-struct arm_float_abi_option_table
+static struct arm_option_value_table arm_float_abis[] =
{
- char *name;
- int value;
-};
-
-static struct arm_float_abi_option_table arm_float_abis[] =
-{
{"hard", ARM_FLOAT_ABI_HARD},
{"softfp", ARM_FLOAT_ABI_SOFTFP},
{"soft", ARM_FLOAT_ABI_SOFT},
{NULL, 0}
};
-struct arm_eabi_option_table
-{
- char *name;
- unsigned int value;
-};
-
#ifdef OBJ_ELF
/* We only know how to output GNU and ver 4 (AAELF) formats. */
-static struct arm_eabi_option_table arm_eabis[] =
+static struct arm_option_value_table arm_eabis[] =
{
{"gnu", EF_ARM_EABI_UNKNOWN},
{"4", EF_ARM_EABI_VER4},
@@ -10575,7 +10300,7 @@
{
while (str != NULL && *str != 0)
{
- struct arm_arch_extension_table * opt;
+ struct arm_option_value_table * opt;
char * ext;
int optlen;
@@ -10690,7 +10415,7 @@
static int
arm_parse_fpu (char * str)
{
- struct arm_fpu_option_table * opt;
+ struct arm_option_value_table * opt;
for (opt = arm_fpus; opt->name != NULL; opt++)
if (streq (opt->name, str))
@@ -10706,7 +10431,7 @@
static int
arm_parse_float_abi (char * str)
{
- struct arm_float_abi_option_table * opt;
+ struct arm_option_value_table * opt;
for (opt = arm_float_abis; opt->name != NULL; opt++)
if (streq (opt->name, str))
@@ -10723,7 +10448,7 @@
static int
arm_parse_eabi (char * str)
{
- struct arm_eabi_option_table *opt;
+ struct arm_option_value_table *opt;
for (opt = arm_eabis; opt->name != NULL; opt++)
if (streq (opt->name, str))