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Re: ARM: Improved IT disassembly
- From: Richard Earnshaw <Richard dot Earnshaw at arm dot com>
- To: Zack Weinberg <zack at codesourcery dot com>
- Cc: binutils <binutils at sourceware dot org>, Nick Clifton <nickc at redhat dot com>
- Date: Thu, 09 Jun 2005 17:29:31 +0100
- Subject: Re: ARM: Improved IT disassembly
- References: <878y1k455h.fsf@codesourcery.com>
On Thu, 2005-06-09 at 03:48, Zack Weinberg wrote:
> This patch brings the disassembly of IT "blocks" more in line with the
> "unified assembly syntax" spec. IT now causes the production of
> conditional suffixes on the subsequent instructions, and suppresses
> the 's' suffix on 16-bit instructions (which don't set the condition
> code when they are in the shadow of an IT - funky rule, yes).
> Instructions that are not allowed in IT print "; unpredictable
> (IT:cond)" at the end instead.
>
> I've hand-spot-checked the output; proper testing, alas, will have to
> wait for the next patch, which adds IT validation to the assembler
> (however, that patch will not be submitted until both this and the
> GAS-bugfixes patch are in - sorry, i'm juggling too many eggs right
> now).
>
> zw
>
> opcodes:
> * arm-dis.c (ifthen_state, new_ifthen_state): New statics.
> (IFTHEN_ACTIVE, IFTHEN_COND, IFTHEN_TAG, IFTHEN_MASK, IFTHEN_BASE):
> New macros.
> (ifthen_step): New function.
> (print_insn_thumb16): Add %c, %C, %X, and %I formatters.
> (print_insn_thumb32): Add %c and %X formatters.
> (thumb_opcodes, thumb32_opcodes): Add %c, %C, %X, or %I to
> instructions as appropriate. Consolidate IT entries.
> gas/testsuite:
> * gas/arm/thumb32.d: Update expected output.
I'm not very keen on the abort in ifthen_step. It seems likely to me
that disassembling random single instructions from within GDB would
likely hit that without trying too hard. It's one thing to cache known
state and try to reuse it to accelerate object disassembly, but we must
recover cleanly if a user does, say,
(gdb) x/i $pc
.... iteee eq
(gdb) x/5i $pc-32
etc.
R.