[PATCH, Committed] Check register type for load immediate instruction in the bfin port of gas

[Jie Zhang <jzhang918 at gmail dot com>]

The load immediate instruction for Blackfin does not allow any one of
the sysregs (ASTAT, SEQSTAT, SYSCFG, RETI, RETX, RETN, RETE, RETS, LC0
and LC1, LT0 and LT1, LB0 and LB1, CYCLES, CYCLES2, and EMUDAT) as its
destination register. Previously Blackfin assembler would silently
accept the following illegal instructions and generate incorrect
result:

ASTAT=0;
SEQSTAT=0;
SYSCFG=0;
RETI=0;
RETX=0;
RETN=0;
RETE=0;
RETS=0;
LC0=0;
LC1=0;
LT0=0;
LT1=0;
LB0=0;
LB1=0;
CYCLES=0;
CYCLES2=0;
EMUDAT=0;

I have committed this patch to check the register type for load
immediate instruction. The assembler now should give errors on these
instructions.

Jie

	* config/bfin-defs.h (IS_BREG, IS_LREG): New macros.
	* config/bfin-parse.y (asm_1): Check register type for load immediate
	instruction.

Index: config/bfin-defs.h
===================================================================
RCS file: /cvsroot/gcc3/binutils/binutils-2.15/gas/config/bfin-defs.h,v
retrieving revision 1.12
diff -u -r1.12 bfin-defs.h
--- config/bfin-defs.h	9 Aug 2005 15:44:03 -0000	1.12
+++ config/bfin-defs.h	18 Nov 2005 06:13:05 -0000
@@ -213,6 +213,8 @@
 #define IS_PREG(r)       _TYPECHECK(r, P)
 #define IS_IREG(r)       (((r).regno & 0xf4) == T_REG_I)
 #define IS_MREG(r)       (((r).regno & 0xf4) == T_REG_M)
+#define IS_BREG(r)       (((r).regno & 0xf4) == T_REG_B)
+#define IS_LREG(r)       (((r).regno & 0xf4) == T_REG_L)
 #define IS_CREG(r)       ((r).regno == REG_LC0 || (r).regno == REG_LC1)
 #define IS_ALLREG(r)     ((r).regno < T_NOGROUP)
 
Index: config/bfin-parse.y
===================================================================
RCS file: /cvsroot/gcc3/binutils/binutils-2.15/gas/config/bfin-parse.y,v
retrieving revision 1.33
diff -u -r1.33 bfin-parse.y
--- config/bfin-parse.y	9 Aug 2005 15:44:03 -0000	1.33
+++ config/bfin-parse.y	18 Nov 2005 06:13:07 -0000
@@ -1204,8 +1204,14 @@
 	| HALF_REG ASSIGN expr
 	{
 	  notethat ("LDIMMhalf: pregs_half = imm16\n");
+
+	  if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
+	      && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
+	    return yyerror ("Wrong register for load immediate");
+
 	  if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
 	    return yyerror ("Constant out of range");
+
 	  $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
 	}
 
@@ -1222,6 +1228,10 @@
 /* 2 rules compacted */
 	| REG ASSIGN expr xpmod1
 	{
+	  if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
+	      && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
+	    return yyerror ("Wrong register for load immediate");
+
 	  if ($4.r0 == 0)
 	    {
 	      // Default: (x)