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[patch] Incorect encodig of ARM VFP fconst

From: Paul Brook <paul at codesourcery dot com>
To: binutils at sourceware dot org
Date: Wed, 25 Oct 2006 23:06:43 +0100
Subject: [patch] Incorect encodig of ARM VFP fconst
The patch below fixes incorrect encoding of the ARM VFP fconst instructions. 
The disassembler was using the same incorrect encoding, so I fixed that too.

Tested with cross to arm-none-eabi.
Ok?

Paul

2006-10-25  Paul Brook  <paul@codesourcery.com>

	gas/
	* config/tc-arm.c (do_vfp_sp_const, do_vfp_dp_const): Fix operans
	encoding.

	gas/testsuite/
	* gas/arm/vfpv3-const-conv.s: Improve test coverage.
	* gas/arm/vfpv3-const-conv.d: Adjust expected output.
	* gas/arm/vfp-neon-syntax_t2.d: Ditto.
	* gas/arm/vfp-neon-syntax.d: Ditto.

	opcodes/
	* arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd.

Index: gas/config/tc-arm.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/config/tc-arm.c,v
retrieving revision 1.250.2.37
diff -u -p -r1.250.2.37 tc-arm.c
--- gas/config/tc-arm.c	19 Sep 2006 18:44:37 -0000	1.250.2.37
+++ gas/config/tc-arm.c	25 Oct 2006 20:30:42 -0000
@@ -7716,16 +7724,16 @@ static void
 do_vfp_sp_const (void)
 {
   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
-  inst.instruction |= (inst.operands[1].imm & 15) << 16;
-  inst.instruction |= (inst.operands[1].imm >> 4);
+  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
+  inst.instruction |= (inst.operands[1].imm & 0x0f);
 }
 
 static void
 do_vfp_dp_const (void)
 {
   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
-  inst.instruction |= (inst.operands[1].imm & 15) << 16;
-  inst.instruction |= (inst.operands[1].imm >> 4);
+  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
+  inst.instruction |= (inst.operands[1].imm & 0x0f);
 }
 
 static void
Index: gas/testsuite/gas/arm/vfp-neon-syntax.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/vfp-neon-syntax.d,v
retrieving revision 1.1.2.2
diff -u -p -r1.1.2.2 vfp-neon-syntax.d
--- gas/testsuite/gas/arm/vfp-neon-syntax.d	20 Jul 2006 14:16:42 -0000	1.1.2.2
+++ gas/testsuite/gas/arm/vfp-neon-syntax.d	25 Oct 2006 21:08:17 -0000
@@ -7,16 +7,16 @@
 Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> eeb00a60 	fcpys	s0, s1
 0[0-9a-f]+ <[^>]+> eeb00b41 	fcpyd	d0, d1
-0[0-9a-f]+ <[^>]+> eeb00a05 	fconsts	s0, #80
-0[0-9a-f]+ <[^>]+> eeb00b07 	fconstd	d0, #112
+0[0-9a-f]+ <[^>]+> eeb50a00 	fconsts	s0, #80
+0[0-9a-f]+ <[^>]+> eeb70b00 	fconstd	d0, #112
 0[0-9a-f]+ <[^>]+> ee100a90 	fmrs	r0, s1
 0[0-9a-f]+ <[^>]+> ee001a10 	fmsr	s0, r1
 0[0-9a-f]+ <[^>]+> ec510a11 	fmrrs	r0, r1, {s2, s3}
 0[0-9a-f]+ <[^>]+> ec442a10 	fmsrr	{s0, s1}, r2, r4
 0[0-9a-f]+ <[^>]+> 0eb00a60 	fcpyseq	s0, s1
 0[0-9a-f]+ <[^>]+> 0eb00b41 	fcpydeq	d0, d1
-0[0-9a-f]+ <[^>]+> 0eb00a05 	fconstseq	s0, #80
-0[0-9a-f]+ <[^>]+> 0eb00b07 	fconstdeq	d0, #112
+0[0-9a-f]+ <[^>]+> 0eb50a00 	fconstseq	s0, #80
+0[0-9a-f]+ <[^>]+> 0eb70b00 	fconstdeq	d0, #112
 0[0-9a-f]+ <[^>]+> 0e100a90 	fmrseq	r0, s1
 0[0-9a-f]+ <[^>]+> 0e001a10 	fmsreq	s0, r1
 0[0-9a-f]+ <[^>]+> 0c510a11 	fmrrseq	r0, r1, {s2, s3}
Index: gas/testsuite/gas/arm/vfp-neon-syntax_t2.d
===================================================================
RCS 
file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d,v
retrieving revision 1.1.2.2
diff -u -p -r1.1.2.2 vfp-neon-syntax_t2.d
--- gas/testsuite/gas/arm/vfp-neon-syntax_t2.d	20 Jul 2006 14:16:42 -0000	
1.1.2.2
+++ gas/testsuite/gas/arm/vfp-neon-syntax_t2.d	25 Oct 2006 21:08:38 -0000
@@ -7,8 +7,8 @@
 Disassembly of section \.text:
 0[0-9a-f]+ <[^>]+> eeb0 0a60 	fcpys	s0, s1
 0[0-9a-f]+ <[^>]+> eeb0 0b41 	fcpyd	d0, d1
-0[0-9a-f]+ <[^>]+> eeb0 0a05 	fconsts	s0, #80
-0[0-9a-f]+ <[^>]+> eeb0 0b07 	fconstd	d0, #112
+0[0-9a-f]+ <[^>]+> eeb5 0a00 	fconsts	s0, #80
+0[0-9a-f]+ <[^>]+> eeb7 0b00 	fconstd	d0, #112
 0[0-9a-f]+ <[^>]+> ee10 0a90 	fmrs	r0, s1
 0[0-9a-f]+ <[^>]+> ee00 1a10 	fmsr	s0, r1
 0[0-9a-f]+ <[^>]+> ec51 0a11 	fmrrs	r0, r1, {s2, s3}
@@ -16,8 +16,8 @@ Disassembly of section \.text:
 0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
 0[0-9a-f]+ <[^>]+> eeb0 0a60 	fcpyseq	s0, s1
 0[0-9a-f]+ <[^>]+> eeb0 0b41 	fcpydeq	d0, d1
-0[0-9a-f]+ <[^>]+> eeb0 0a05 	fconstseq	s0, #80
-0[0-9a-f]+ <[^>]+> eeb0 0b07 	fconstdeq	d0, #112
+0[0-9a-f]+ <[^>]+> eeb5 0a00 	fconstseq	s0, #80
+0[0-9a-f]+ <[^>]+> eeb7 0b00 	fconstdeq	d0, #112
 0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
 0[0-9a-f]+ <[^>]+> ee10 0a90 	fmrseq	r0, s1
 0[0-9a-f]+ <[^>]+> ee00 1a10 	fmsreq	s0, r1
Index: gas/testsuite/gas/arm/vfpv3-const-conv.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/vfpv3-const-conv.d,v
retrieving revision 1.1.2.1
diff -u -p -r1.1.2.1 vfpv3-const-conv.d
--- gas/testsuite/gas/arm/vfpv3-const-conv.d	3 Apr 2006 00:03:34 -0000	1.1.2.1
+++ gas/testsuite/gas/arm/vfpv3-const-conv.d	25 Oct 2006 21:09:48 -0000
@@ -5,12 +5,12 @@
 .*: +file format .*arm.*
 
 Disassembly of section \.text:
-0[0-9a-f]+ <[^>]+> eef48a00 	fconsts	s17, #4
-0[0-9a-f]+ <[^>]+> eeb59a00 	fconsts	s18, #5
-0[0-9a-f]+ <[^>]+> eef69a00 	fconsts	s19, #6
-0[0-9a-f]+ <[^>]+> eef41b00 	fconstd	d17, #4
-0[0-9a-f]+ <[^>]+> eef52b00 	fconstd	d18, #5
-0[0-9a-f]+ <[^>]+> eef63b00 	fconstd	d19, #6
+0[0-9a-f]+ <[^>]+> eef08a04 	fconsts	s17, #4
+0[0-9a-f]+ <[^>]+> eeba9a05 	fconsts	s18, #165
+0[0-9a-f]+ <[^>]+> eef49a00 	fconsts	s19, #64
+0[0-9a-f]+ <[^>]+> eef01b04 	fconstd	d17, #4
+0[0-9a-f]+ <[^>]+> eefa2b05 	fconstd	d18, #165
+0[0-9a-f]+ <[^>]+> eef43b00 	fconstd	d19, #64
 0[0-9a-f]+ <[^>]+> eefa8a63 	fshtos	s17, #9
 0[0-9a-f]+ <[^>]+> eefa1b63 	fshtod	d17, #9
 0[0-9a-f]+ <[^>]+> eefa8aeb 	fsltos	s17, #9
Index: gas/testsuite/gas/arm/vfpv3-const-conv.s
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/vfpv3-const-conv.s,v
retrieving revision 1.1.2.1
diff -u -p -r1.1.2.1 vfpv3-const-conv.s
--- gas/testsuite/gas/arm/vfpv3-const-conv.s	3 Apr 2006 00:03:34 -0000	1.1.2.1
+++ gas/testsuite/gas/arm/vfpv3-const-conv.s	25 Oct 2006 20:28:33 -0000
@@ -1,11 +1,11 @@
 .arm
 .syntax unified
 	fconsts s17, #4
-	fconsts s18, #5
-	fconsts s19, #6
+	fconsts s18, #0xa5
+	fconsts s19, #0x40
 	fconstd d17, #4
-	fconstd d18, #5
-	fconstd d19, #6
+	fconstd d18, #0xa5
+	fconstd d19, #0x40
 	fshtos s17, 9
 	fshtod d17, 9
 	fsltos s17, 9
Index: opcodes/arm-dis.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/opcodes/arm-dis.c,v
retrieving revision 1.62.2.9
diff -u -p -r1.62.2.9 arm-dis.c
--- opcodes/arm-dis.c	19 Sep 2006 18:44:37 -0000	1.62.2.9
+++ opcodes/arm-dis.c	25 Oct 2006 20:30:11 -0000
@@ -308,8 +308,8 @@ static const struct opcode32 coprocessor
   {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, 
#%5,0-3k"},
   {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, 
#%5,0-3k"},
   {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
-  {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%16-19,0-3d"},
-  {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%16-19,0-3d"},
+  {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"},
+  {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"},
   {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"},
   {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
   {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
Follow-Ups:
- Re: [patch] Incorect encodig of ARM VFP fconst
  - From: Nick Clifton
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