This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
binutils xc163/xc165 SFR patch
- From: Matthias Wenzel <binutils-list at mazzoo dot de>
- To: binutils at sourceware dot org
- Date: Wed, 20 Dec 2006 13:06:20 +0100
- Subject: binutils xc163/xc165 SFR patch
hi list,
the support for SFRs in xc16x binutils is somewhat limited. Many SFRs
are unknown, and are replaced by "???" during (dis)assembly.
So I created a patch to support all C163/C165 SFRs. But there's a
problem: I patch opcodes/xc16x-desc.c which starts with a big spoiler
saying "THIS FILE IS MACHINE GENERATED WITH CGEN" so I probably
shouldn't edit it.
But where are the sources for that file/ which are the steps to generate
it? I was digging for already supported SFRs like "stkov" but
opcodes/xc16x-desc.c is the only occurence...
nevertheless I attach the patch to get your comments.
Matthias
diff -Nur binutils-2.17-orig/config.sub binutils-2.17/config.sub
--- binutils-2.17-orig/config.sub 2006-01-16 18:34:37.000000000 +0100
+++ binutils-2.17/config.sub 2006-11-20 17:59:08.000000000 +0100
@@ -281,7 +281,7 @@
| tahoe | thumb | tic4x | tic80 | tron \
| v850 | v850e \
| we32k \
- | x86 | xscale | xscalee[bl] | xstormy16 | xtensa \
+ | x86 | xscale | xscalee[bl] | xstormy16 | xtensa | xc16x\
| z8k)
basic_machine=$basic_machine-unknown
;;
@@ -367,7 +367,7 @@
| v850-* | v850e-* | vax-* \
| we32k-* \
| x86-* | x86_64-* | xps100-* | xscale-* | xscalee[bl]-* \
- | xstormy16-* | xtensa-* \
+ | xstormy16-* | xtensa-* | xc16x-* \
| ymp-* \
| z8k-*)
;;
diff -Nur binutils-2.17-orig/opcodes/xc16x-desc.c binutils-2.17/opcodes/xc16x-desc.c
--- binutils-2.17-orig/opcodes/xc16x-desc.c 2006-02-17 15:36:28.000000000 +0100
+++ binutils-2.17/opcodes/xc16x-desc.c 2006-12-20 12:40:23.000000000 +0100
@@ -320,14 +320,14 @@
{ "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
{ "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
+/* { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, renamed to syscon */
{ "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
+/* { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel1 */
+/* { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel2 */
{ "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
{ "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
+/* { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, renamed to buscon0 */
{ "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
{ "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
{ "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
@@ -344,13 +344,83 @@
{ "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
{ "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
{ "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
- { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
+ { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 },
+
+ { "addrsel1", 0x0c, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel2", 0x0d, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel3", 0x0e, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel4", 0x0f, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon0", 0x86, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon1", 0x8a, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon2", 0x8b, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon3", 0x8c, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon4", 0x8d, {0, {{{0, 0}}}}, 0, 0 },
+ { "caprel", 0x25, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc8ic", 0xc4, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc9ic", 0xc5, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc10ic", 0xc6, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc11ic", 0xc7, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc12ic", 0xc8, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc13ic", 0xc9, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc14ic", 0xca, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc15ic", 0xcb, {0, {{{0, 0}}}}, 0, 0 },
+ { "cric", 0xb5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp2", 0xe1, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp3", 0xe3, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp4", 0xe5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp6", 0xe7, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0l", 0x80, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0h", 0x81, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1l", 0x82, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1h", 0x83, {0, {{{0, 0}}}}, 0, 0 },
+ { "p2", 0xe0, {0, {{{0, 0}}}}, 0, 0 },
+ { "p3", 0xe2, {0, {{{0, 0}}}}, 0, 0 },
+ { "p4", 0xe4, {0, {{{0, 0}}}}, 0, 0 },
+ { "p5", 0xd1, {0, {{{0, 0}}}}, 0, 0 },
+ { "p6", 0xe6, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc0", 0x60, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc1", 0x61, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc2", 0x62, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc3", 0x63, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc4", 0x64, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc5", 0x65, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc6", 0x66, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc7", 0x67, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0bg", 0x5a, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0con", 0xd8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0eic", 0xb8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0rbuf", 0x59, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0ric", 0xb7, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tbuf", 0xce, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tic", 0xb6, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssccon", 0xd9, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssceic", 0xbb, {0, {{{0, 0}}}}, 0, 0 },
+ { "sscric", 0xba, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssctic", 0xb9, {0, {{{0, 0}}}}, 0, 0 },
+ { "syscon", 0x89, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2", 0x20, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2con", 0xa0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2ic", 0xb0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3", 0x21, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3con", 0xa1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3ic", 0xb1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4", 0x22, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4con", 0xa2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4ic", 0xb2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5", 0x23, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5con", 0xa3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5ic", 0xb3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6", 0x24, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6con", 0xa4, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6ic", 0xb4, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdt", 0x57, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdtcon", 0xd7, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD xc16x_cgen_opval_grb8_names =
{
& xc16x_cgen_opval_grb8_names_entries[0],
- 36,
+ 101,
0, 0, 0, 0, ""
};
@@ -367,14 +437,14 @@
{ "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
{ "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
+/* { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, renamed to syscon */
{ "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
+/* { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel1 */
+/* { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel2 */
{ "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
{ "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
+/* { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, renamed to buscon0 */
{ "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
{ "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
{ "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
@@ -391,13 +461,83 @@
{ "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
{ "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
{ "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
- { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
+ { "r15", 255, {0, {{{0, 0}}}}, 0, 0 },
+
+ { "addrsel1", 0x0c, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel2", 0x0d, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel3", 0x0e, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel4", 0x0f, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon0", 0x86, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon1", 0x8a, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon2", 0x8b, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon3", 0x8c, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon4", 0x8d, {0, {{{0, 0}}}}, 0, 0 },
+ { "caprel", 0x25, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc8ic", 0xc4, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc9ic", 0xc5, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc10ic", 0xc6, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc11ic", 0xc7, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc12ic", 0xc8, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc13ic", 0xc9, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc14ic", 0xca, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc15ic", 0xcb, {0, {{{0, 0}}}}, 0, 0 },
+ { "cric", 0xb5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp2", 0xe1, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp3", 0xe3, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp4", 0xe5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp6", 0xe7, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0l", 0x80, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0h", 0x81, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1l", 0x82, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1h", 0x83, {0, {{{0, 0}}}}, 0, 0 },
+ { "p2", 0xe0, {0, {{{0, 0}}}}, 0, 0 },
+ { "p3", 0xe2, {0, {{{0, 0}}}}, 0, 0 },
+ { "p4", 0xe4, {0, {{{0, 0}}}}, 0, 0 },
+ { "p5", 0xd1, {0, {{{0, 0}}}}, 0, 0 },
+ { "p6", 0xe6, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc0", 0x60, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc1", 0x61, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc2", 0x62, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc3", 0x63, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc4", 0x64, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc5", 0x65, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc6", 0x66, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc7", 0x67, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0bg", 0x5a, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0con", 0xd8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0eic", 0xb8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0rbuf", 0x59, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0ric", 0xb7, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tbuf", 0xce, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tic", 0xb6, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssccon", 0xd9, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssceic", 0xbb, {0, {{{0, 0}}}}, 0, 0 },
+ { "sscric", 0xba, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssctic", 0xb9, {0, {{{0, 0}}}}, 0, 0 },
+ { "syscon", 0x89, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2", 0x20, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2con", 0xa0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2ic", 0xb0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3", 0x21, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3con", 0xa1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3ic", 0xb1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4", 0x22, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4con", 0xa2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4ic", 0xb2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5", 0x23, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5con", 0xa3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5ic", 0xb3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6", 0x24, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6con", 0xa4, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6ic", 0xb4, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdt", 0x57, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdtcon", 0xd7, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD xc16x_cgen_opval_r8_names =
{
& xc16x_cgen_opval_r8_names_entries[0],
- 36,
+ 101,
0, 0, 0, 0, ""
};
@@ -414,14 +554,14 @@
{ "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
{ "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
+/* { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, renamed to syscon */
{ "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
+/* { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel1 */
+/* { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel2 */
{ "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
{ "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
+/* { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, renamed to buscon0 */
{ "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
{ "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
{ "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
@@ -438,13 +578,83 @@
{ "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
{ "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
{ "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
- { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
+ { "r15", 255, {0, {{{0, 0}}}}, 0, 0 },
+
+ { "addrsel1", 0x0c, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel2", 0x0d, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel3", 0x0e, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel4", 0x0f, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon0", 0x86, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon1", 0x8a, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon2", 0x8b, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon3", 0x8c, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon4", 0x8d, {0, {{{0, 0}}}}, 0, 0 },
+ { "caprel", 0x25, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc8ic", 0xc4, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc9ic", 0xc5, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc10ic", 0xc6, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc11ic", 0xc7, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc12ic", 0xc8, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc13ic", 0xc9, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc14ic", 0xca, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc15ic", 0xcb, {0, {{{0, 0}}}}, 0, 0 },
+ { "cric", 0xb5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp2", 0xe1, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp3", 0xe3, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp4", 0xe5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp6", 0xe7, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0l", 0x80, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0h", 0x81, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1l", 0x82, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1h", 0x83, {0, {{{0, 0}}}}, 0, 0 },
+ { "p2", 0xe0, {0, {{{0, 0}}}}, 0, 0 },
+ { "p3", 0xe2, {0, {{{0, 0}}}}, 0, 0 },
+ { "p4", 0xe4, {0, {{{0, 0}}}}, 0, 0 },
+ { "p5", 0xd1, {0, {{{0, 0}}}}, 0, 0 },
+ { "p6", 0xe6, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc0", 0x60, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc1", 0x61, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc2", 0x62, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc3", 0x63, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc4", 0x64, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc5", 0x65, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc6", 0x66, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc7", 0x67, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0bg", 0x5a, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0con", 0xd8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0eic", 0xb8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0rbuf", 0x59, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0ric", 0xb7, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tbuf", 0xce, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tic", 0xb6, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssccon", 0xd9, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssceic", 0xbb, {0, {{{0, 0}}}}, 0, 0 },
+ { "sscric", 0xba, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssctic", 0xb9, {0, {{{0, 0}}}}, 0, 0 },
+ { "syscon", 0x89, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2", 0x20, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2con", 0xa0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2ic", 0xb0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3", 0x21, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3con", 0xa1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3ic", 0xb1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4", 0x22, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4con", 0xa2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4ic", 0xb2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5", 0x23, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5con", 0xa3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5ic", 0xb3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6", 0x24, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6con", 0xa4, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6ic", 0xb4, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdt", 0x57, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdtcon", 0xd7, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD xc16x_cgen_opval_regmem8_names =
{
& xc16x_cgen_opval_regmem8_names_entries[0],
- 36,
+ 101,
0, 0, 0, 0, ""
};
@@ -554,14 +764,14 @@
{ "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
{ "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
+/* { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, renamed to syscon */
{ "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
+/* { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel1 */
+/* { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel2 */
{ "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
{ "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
+/* { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, renamed to buscon0 */
{ "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
{ "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
{ "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
@@ -578,13 +788,83 @@
{ "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
{ "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
{ "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
- { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
+ { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 },
+
+ { "addrsel1", 0x0c, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel2", 0x0d, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel3", 0x0e, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel4", 0x0f, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon0", 0x86, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon1", 0x8a, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon2", 0x8b, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon3", 0x8c, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon4", 0x8d, {0, {{{0, 0}}}}, 0, 0 },
+ { "caprel", 0x25, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc8ic", 0xc4, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc9ic", 0xc5, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc10ic", 0xc6, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc11ic", 0xc7, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc12ic", 0xc8, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc13ic", 0xc9, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc14ic", 0xca, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc15ic", 0xcb, {0, {{{0, 0}}}}, 0, 0 },
+ { "cric", 0xb5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp2", 0xe1, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp3", 0xe3, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp4", 0xe5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp6", 0xe7, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0l", 0x80, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0h", 0x81, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1l", 0x82, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1h", 0x83, {0, {{{0, 0}}}}, 0, 0 },
+ { "p2", 0xe0, {0, {{{0, 0}}}}, 0, 0 },
+ { "p3", 0xe2, {0, {{{0, 0}}}}, 0, 0 },
+ { "p4", 0xe4, {0, {{{0, 0}}}}, 0, 0 },
+ { "p5", 0xd1, {0, {{{0, 0}}}}, 0, 0 },
+ { "p6", 0xe6, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc0", 0x60, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc1", 0x61, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc2", 0x62, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc3", 0x63, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc4", 0x64, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc5", 0x65, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc6", 0x66, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc7", 0x67, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0bg", 0x5a, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0con", 0xd8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0eic", 0xb8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0rbuf", 0x59, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0ric", 0xb7, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tbuf", 0xce, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tic", 0xb6, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssccon", 0xd9, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssceic", 0xbb, {0, {{{0, 0}}}}, 0, 0 },
+ { "sscric", 0xba, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssctic", 0xb9, {0, {{{0, 0}}}}, 0, 0 },
+ { "syscon", 0x89, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2", 0x20, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2con", 0xa0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2ic", 0xb0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3", 0x21, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3con", 0xa1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3ic", 0xb1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4", 0x22, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4con", 0xa2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4ic", 0xb2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5", 0x23, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5con", 0xa3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5ic", 0xb3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6", 0x24, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6con", 0xa4, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6ic", 0xb4, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdt", 0x57, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdtcon", 0xd7, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names =
{
& xc16x_cgen_opval_regbmem8_names_entries[0],
- 36,
+ 101,
0, 0, 0, 0, ""
};
@@ -601,21 +881,91 @@
{ "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 },
{ "sp", 65042, {0, {{{0, 0}}}}, 0, 0 },
{ "csp", 65032, {0, {{{0, 0}}}}, 0, 0 },
- { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 },
+/* { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 }, renamed to syscon */
{ "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 },
{ "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 },
- { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 },
+/* { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel1 */
+/* { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 }, renamed to addrsel2 */
{ "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 },
{ "ones", 65310, {0, {{{0, 0}}}}, 0, 0 },
- { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 },
- { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 }
+/* { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 }, renamed to buscon0 */
+ { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 },
+
+ { "addrsel1", 0xfe00+2*0x0c, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel2", 0xfe00+2*0x0d, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel3", 0xfe00+2*0x0e, {0, {{{0, 0}}}}, 0, 0 },
+ { "addrsel4", 0xfe00+2*0x0f, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon0", 0xfe00+2*0x86, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon1", 0xfe00+2*0x8a, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon2", 0xfe00+2*0x8b, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon3", 0xfe00+2*0x8c, {0, {{{0, 0}}}}, 0, 0 },
+ { "buscon4", 0xfe00+2*0x8d, {0, {{{0, 0}}}}, 0, 0 },
+ { "caprel", 0xfe00+2*0x25, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc8ic", 0xfe00+2*0xc4, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc9ic", 0xfe00+2*0xc5, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc10ic", 0xfe00+2*0xc6, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc11ic", 0xfe00+2*0xc7, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc12ic", 0xfe00+2*0xc8, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc13ic", 0xfe00+2*0xc9, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc14ic", 0xfe00+2*0xca, {0, {{{0, 0}}}}, 0, 0 },
+ { "cc15ic", 0xfe00+2*0xcb, {0, {{{0, 0}}}}, 0, 0 },
+ { "cric", 0xfe00+2*0xb5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp2", 0xfe00+2*0xe1, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp3", 0xfe00+2*0xe3, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp4", 0xfe00+2*0xe5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dp6", 0xfe00+2*0xe7, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0l", 0xfe00+2*0x80, {0, {{{0, 0}}}}, 0, 0 },
+ { "p0h", 0xfe00+2*0x81, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1l", 0xfe00+2*0x82, {0, {{{0, 0}}}}, 0, 0 },
+ { "p1h", 0xfe00+2*0x83, {0, {{{0, 0}}}}, 0, 0 },
+ { "p2", 0xfe00+2*0xe0, {0, {{{0, 0}}}}, 0, 0 },
+ { "p3", 0xfe00+2*0xe2, {0, {{{0, 0}}}}, 0, 0 },
+ { "p4", 0xfe00+2*0xe4, {0, {{{0, 0}}}}, 0, 0 },
+ { "p5", 0xfe00+2*0xd1, {0, {{{0, 0}}}}, 0, 0 },
+ { "p6", 0xfe00+2*0xe6, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc0", 0xfe00+2*0x60, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc1", 0xfe00+2*0x61, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc2", 0xfe00+2*0x62, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc3", 0xfe00+2*0x63, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc4", 0xfe00+2*0x64, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc5", 0xfe00+2*0x65, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc6", 0xfe00+2*0x66, {0, {{{0, 0}}}}, 0, 0 },
+ { "pecc7", 0xfe00+2*0x67, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0bg", 0xfe00+2*0x5a, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0con", 0xfe00+2*0xd8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0eic", 0xfe00+2*0xb8, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0rbuf", 0xfe00+2*0x59, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0ric", 0xfe00+2*0xb7, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tbuf", 0xfe00+2*0xce, {0, {{{0, 0}}}}, 0, 0 },
+ { "s0tic", 0xfe00+2*0xb6, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssccon", 0xfe00+2*0xd9, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssceic", 0xfe00+2*0xbb, {0, {{{0, 0}}}}, 0, 0 },
+ { "sscric", 0xfe00+2*0xba, {0, {{{0, 0}}}}, 0, 0 },
+ { "ssctic", 0xfe00+2*0xb9, {0, {{{0, 0}}}}, 0, 0 },
+ { "syscon", 0xfe00+2*0x89, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2", 0xfe00+2*0x20, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2con", 0xfe00+2*0xa0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t2ic", 0xfe00+2*0xb0, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3", 0xfe00+2*0x21, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3con", 0xfe00+2*0xa1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t3ic", 0xfe00+2*0xb1, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4", 0xfe00+2*0x22, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4con", 0xfe00+2*0xa2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t4ic", 0xfe00+2*0xb2, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5", 0xfe00+2*0x23, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5con", 0xfe00+2*0xa3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t5ic", 0xfe00+2*0xb3, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6", 0xfe00+2*0x24, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6con", 0xfe00+2*0xa4, {0, {{{0, 0}}}}, 0, 0 },
+ { "t6ic", 0xfe00+2*0xb4, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdt", 0xfe00+2*0x57, {0, {{{0, 0}}}}, 0, 0 },
+ { "wdtcon", 0xfe00+2*0xd7, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD xc16x_cgen_opval_memgr8_names =
{
& xc16x_cgen_opval_memgr8_names_entries[0],
- 20,
+ 85,
0, 0, 0, 0, ""
};