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[patch] ARM vclt broken
- From: Paul Brook <paul at codesourcery dot com>
- To: binutils at sourceware dot org
- Date: Thu, 4 Jan 2007 02:59:12 +0000
- Subject: [patch] ARM vclt broken
The ARM NEON vclt and vcle instructions are aliases for vcgt and vcge
respectively. Binutils currently gets this backwards. Likewise for
vaclt/vacle. Patch below fixes this.
Tested with cross to arm-none-eabi
Ok?
Paul
2007-01-04 Paul Brook <paul@codesourcery.com>
gas/
* config/tc-arm.c (NEON_ENC_TAB): Fix encoding of vclt, vcle, vaclt
and vacle.
gas/testsuite/
* gas/arm/neon-cov.d: Adjust expected output.
* gas/arm/neon-omit.s: Add tests for vcgt and vcle. Reorder vacle
and vacle.
* gas/arm/neon-omit.d: Adjust expected output.
Index: gas/config/tc-arm.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/config/tc-arm.c,v
retrieving revision 1.250.2.27
diff -u -p -r1.250.2.27 tc-arm.c
--- gas/config/tc-arm.c 5 Sep 2006 14:24:01 -0000 1.250.2.27
+++ gas/config/tc-arm.c 5 Sep 2006 17:16:13 -0000
@@ -10097,8 +10097,8 @@ struct neon_tab_entry
X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
/* Register variants of the following two instructions are encoded as
vcge / vcgt with the operands reversed. */ \
- X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \
- X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \
+ X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
+ X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
@@ -15546,10 +15546,10 @@ static const struct asm_opcode insns[] =
NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
- NUF(vaclt, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
- NUF(vacltq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
- NUF(vacle, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
- NUF(vacleq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
+ NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
+ NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
+ NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
+ NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
Index: gas/testsuite/gas/arm/neon-cov.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/neon-cov.d,v
retrieving revision 1.1.2.3
diff -u -p -r1.1.2.3 neon-cov.d
--- gas/testsuite/gas/arm/neon-cov.d 4 Sep 2006 15:55:36 -0000 1.1.2.3
+++ gas/testsuite/gas/arm/neon-cov.d 5 Sep 2006 17:47:56 -0000
@@ -488,27 +488,6 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e00 vcgt\.f32 d0, d0, d0
-0[0-9a-f]+ <[^>]+> f2000340 vcgt\.s8 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f2000340 vcgt\.s8 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f2000300 vcgt\.s8 d0, d0, d0
-0[0-9a-f]+ <[^>]+> f2100340 vcgt\.s16 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f2100340 vcgt\.s16 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f2100300 vcgt\.s16 d0, d0, d0
-0[0-9a-f]+ <[^>]+> f2200340 vcgt\.s32 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f2200340 vcgt\.s32 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f2200300 vcgt\.s32 d0, d0, d0
-0[0-9a-f]+ <[^>]+> f3000340 vcgt\.u8 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3000340 vcgt\.u8 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3000300 vcgt\.u8 d0, d0, d0
-0[0-9a-f]+ <[^>]+> f3100340 vcgt\.u16 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3100340 vcgt\.u16 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3100300 vcgt\.u16 d0, d0, d0
-0[0-9a-f]+ <[^>]+> f3200340 vcgt\.u32 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3200340 vcgt\.u32 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3200300 vcgt\.u32 d0, d0, d0
-0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3200e00 vcgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2000350 vcge\.s8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000350 vcge\.s8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000310 vcge\.s8 d0, d0, d0
@@ -530,6 +509,27 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> f3000e40 vcge\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000e40 vcge\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000e00 vcge\.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000340 vcgt\.s8 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000340 vcgt\.s8 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000300 vcgt\.s8 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100340 vcgt\.s16 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100340 vcgt\.s16 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100300 vcgt\.s16 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200340 vcgt\.s32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200340 vcgt\.s32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200300 vcgt\.s32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000340 vcgt\.u8 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000340 vcgt\.u8 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000300 vcgt\.u8 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100340 vcgt\.u16 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100340 vcgt\.u16 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100300 vcgt\.u16 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200340 vcgt\.u32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200340 vcgt\.u32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200300 vcgt\.u32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e00 vcgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3000850 vceq\.i8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000850 vceq\.i8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000810 vceq\.i8 d0, d0, d0
@@ -802,12 +802,12 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0
-0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
-0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000e10 vacge\.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000f10 vrecps\.f32 d0, d0, d0
Index: gas/testsuite/gas/arm/neon-omit.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/neon-omit.d,v
retrieving revision 1.1.2.1
diff -u -p -r1.1.2.1 neon-omit.d
--- gas/testsuite/gas/arm/neon-omit.d 3 Apr 2006 00:03:34 -0000 1.1.2.1
+++ gas/testsuite/gas/arm/neon-omit.d 5 Sep 2006 16:51:54 -0000
@@ -37,7 +37,9 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f30cae5a vacge\.f32 q5, q6, q5
0[0-9a-f]+ <[^>]+> f320eede vacgt\.f32 q7, q8, q7
0[0-9a-f]+ <[^>]+> f32ee370 vcge\.u32 q7, q7, q8
+0[0-9a-f]+ <[^>]+> f32ee360 vcgt\.u32 q7, q7, q8
0[0-9a-f]+ <[^>]+> f320e3de vcge\.u32 q7, q8, q7
+0[0-9a-f]+ <[^>]+> f320e3ce vcgt\.u32 q7, q8, q7
0[0-9a-f]+ <[^>]+> f3a22102 vaddw\.u32 q1, q1, d2
0[0-9a-f]+ <[^>]+> f2a66304 vsubw\.s32 q3, q3, d4
0[0-9a-f]+ <[^>]+> f2244856 vtst\.32 q2, q2, q3
Index: gas/testsuite/gas/arm/neon-omit.s
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/neon-omit.s,v
retrieving revision 1.1.2.1
diff -u -p -r1.1.2.1 neon-omit.s
--- gas/testsuite/gas/arm/neon-omit.s 3 Apr 2006 00:03:34 -0000 1.1.2.1
+++ gas/testsuite/gas/arm/neon-omit.s 5 Sep 2006 17:48:28 -0000
@@ -33,9 +33,11 @@
vmls.s32 q3,q4
vacge.f q1,q2
vacgt.f q3,q4
- vaclt.f q5,q6
- vacle.f q7,q8
+ vacle.f q5,q6
+ vaclt.f q7,q8
vcge.u32 q7,q8
+ vcgt.u32 q7,q8
+ vcle.u32 q7,q8
vclt.u32 q7,q8
vaddw.u32 q1,d2
vsubw.s32 q3,d4