This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
PATCH: Move SYSV386_COMPAT to config/tc-i386.c
- From: "H. J. Lu" <hjl at lucon dot org>
- To: binutils at sources dot redhat dot com
- Date: Tue, 13 Mar 2007 10:50:42 -0700
- Subject: PATCH: Move SYSV386_COMPAT to config/tc-i386.c
This patch moves SYSV386_COMPAT to config/tc-i386.c so that it is
easier to put include/opcode/i386.h in a separate file, indepedent
of gas.
H.J.
-----
gas/
2007-03-13 H.J. Lu <hjl@gnu.org>
* config/tc-i386.c (SYSV386_COMPAT): New macro and defaulted
to 1.
(match_template): Skip Intel i386 instructions when we are in
SystemV i386 compatible instruction mode and vice versa.
* config/tc-i386.h (ShortForm): Updated.
(SystemV386): New.
(Intel386): Likewise.
include/opcode/
2007-03-13 H.J. Lu <hjl@gnu.org>
* i386.h (SYSV386_COMPAT): Removed.
(OLDGCC_COMPAT): Removed.
(FloatDR): Likewise.
(i386_optab): Mark SystemV i386 compatible instructions with
SystemV386. Mark Intel i386 instructions with Intel386.
--- binutils/gas/config/tc-i386.c.att 2007-03-12 14:36:55.000000000 -0700
+++ binutils/gas/config/tc-i386.c 2007-03-13 10:47:02.000000000 -0700
@@ -284,6 +284,13 @@ static const char *flag_code_names[] =
"64"
};
+#ifndef SYSV386_COMPAT
+/* Set non-zero for broken, compatible instructions. Set to zero for
+ non-broken opcodes at your peril. gcc generates SystemV/386
+ compatible instructions. */
+#define SYSV386_COMPAT 1
+#endif
+
/* 1 for intel syntax,
0 if att syntax. */
static int intel_syntax = 0;
@@ -2549,6 +2556,22 @@ match_template (void)
if (i.operands != t->operands)
continue;
+ if (SYSV386_COMPAT)
+ {
+ /* Skip Intel i386 instructions when we are in SystemV i386
+ compatible instruction mode. */
+ if ((t->opcode_modifier & Intel386))
+ continue;
+ }
+ else
+ {
+ /* Skip SystemV i386 compatible instructions when we are in
+ Intel i386 instruction mode. */
+ if ((t->opcode_modifier & SystemV386))
+ continue;
+ }
+
+
/* Check the suffix, except for some instructions in intel mode. */
if ((t->opcode_modifier & suffix_check)
&& !(intel_syntax
--- binutils/gas/config/tc-i386.h.att 2007-03-12 14:36:55.000000000 -0700
+++ binutils/gas/config/tc-i386.h 2007-03-13 09:47:00.000000000 -0700
@@ -216,7 +216,9 @@ typedef struct
#define W 0x2 /* set if operands can be words or dwords
encoded the canonical way */
#define Modrm 0x4 /* insn has a modrm byte. */
-#define ShortForm 0x10 /* register is in low 3 bits of opcode */
+#define ShortForm 0x8 /* register is in low 3 bits of opcode */
+#define SystemV386 0x10 /* SystemV/386 compatible instructions */
+#define Intel386 0x20 /* Intel/386 instructions */
#define Jump 0x40 /* special case for jump insns. */
#define JumpDword 0x80 /* call and jump */
#define JumpByte 0x100 /* loop and jecxz */
--- binutils/include/opcode/i386.h.att 2007-02-13 17:26:42.000000000 -0800
+++ binutils/include/opcode/i386.h 2007-03-13 10:38:18.000000000 -0700
@@ -31,22 +31,11 @@
This happens with all the non-commutative arithmetic floating point
operations with two register operands, where the source register is
- %st, and destination register is %st(i). See FloatDR below.
+ %st, and destination register is %st(i).
- The affected opcode map is dceX, dcfX, deeX, defX. */
-
-#ifndef SYSV386_COMPAT
-/* Set non-zero for broken, compatible instructions. Set to zero for
- non-broken opcodes at your peril. gcc generates SystemV/386
- compatible instructions. */
-#define SYSV386_COMPAT 1
-#endif
-#ifndef OLDGCC_COMPAT
-/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
- generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
- reversed. */
-#define OLDGCC_COMPAT SYSV386_COMPAT
-#endif
+ The affected opcode map is dceX, dcfX, deeX, defX. The SystemV i386
+ compatible instructions have the SystemV386 set and the Intel i386
+ instructions have the Intel386 bit set. */
static const template i386_optab[] =
{
@@ -72,14 +61,6 @@ static const template i386_optab[] =
#define q_FP (q_Suf|NoRex64)
#define x_FP (x_Suf|FloatMF)
#define sl_FP (sl_Suf|FloatMF)
-#if SYSV386_COMPAT
-/* Someone forgot that the FloatR bit reverses the operation when not
- equal to the FloatD bit. ie. Changing only FloatD results in the
- destination being swapped *and* the direction being reversed. */
-#define FloatDR FloatD
-#else
-#define FloatDR (FloatD|FloatR)
-#endif
/* Move instructions. */
#define MOV_AX_DISP32 0xa0
@@ -669,10 +650,8 @@ static const template i386_optab[] =
{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
/* alias for fadd %st(i), %st */
{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-#if SYSV386_COMPAT
/* alias for faddp */
-{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} },
-#endif
+{"fadd", 0, 0xdec1, X, 0, FP|Ugh|SystemV386, { 0, 0, 0} },
{"fadd", 1, 0xd8, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
{"fiadd", 1, 0xde, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
@@ -683,58 +662,44 @@ static const template i386_optab[] =
{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
/* subtract */
-{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
+{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|SystemV386|FloatD, { FloatReg, FloatAcc, 0} },
+{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|Intel386|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-#if SYSV386_COMPAT
/* alias for fsubp */
-{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} },
-#endif
+{"fsub", 0, 0xdee1, X, 0, FP|Ugh|SystemV386, { 0, 0, 0} },
{"fsub", 1, 0xd8, 4, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
{"fisub", 1, 0xde, 4, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
-#if SYSV386_COMPAT
-{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
-{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
-#if OLDGCC_COMPAT
-{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
-#endif
-#else
-{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
-{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
-#endif
+{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|SystemV386, { FloatAcc, FloatReg, 0} },
+{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm|SystemV386, { FloatReg, 0, 0} },
+{"fsubp", 0, 0xdee1, X, 0, FP|SystemV386, { 0, 0, 0} },
+{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh|SystemV386, { FloatReg, FloatAcc, 0} },
+{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm|Intel386, { FloatAcc, FloatReg, 0} },
+{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm|Intel386, { FloatReg, 0, 0} },
+{"fsubp", 0, 0xdee9, X, 0, FP|Intel386, { 0, 0, 0} },
/* subtract reverse */
-{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
+{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|SystemV386|FloatD, { FloatReg, FloatAcc, 0} },
+{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|Intel386|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-#if SYSV386_COMPAT
/* alias for fsubrp */
-{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} },
-#endif
+{"fsubr", 0, 0xdee9, X, 0, FP|Ugh|SystemV386, { 0, 0, 0} },
{"fsubr", 1, 0xd8, 5, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
{"fisubr", 1, 0xde, 5, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
-#if SYSV386_COMPAT
-{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
-{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
-#if OLDGCC_COMPAT
-{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
-#endif
-#else
-{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
-{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
-#endif
+{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|SystemV386, { FloatAcc, FloatReg, 0} },
+{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm|SystemV386, { FloatReg, 0, 0} },
+{"fsubrp", 0, 0xdee9, X, 0, FP|SystemV386, { 0, 0, 0} },
+{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh|SystemV386, { FloatReg, FloatAcc, 0} },
+{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm|Intel386, { FloatAcc, FloatReg, 0} },
+{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm|Intel386, { FloatReg, 0, 0} },
+{"fsubrp", 0, 0xdee1, X, 0, FP|Intel386, { 0, 0, 0} },
/* multiply */
{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-#if SYSV386_COMPAT
/* alias for fmulp */
-{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} },
-#endif
+{"fmul", 0, 0xdec9, X, 0, FP|Ugh|SystemV386, { 0, 0, 0} },
{"fmul", 1, 0xd8, 1, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
{"fimul", 1, 0xde, 1, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
@@ -744,50 +709,38 @@ static const template i386_optab[] =
{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
/* divide */
-{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
+{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|SystemV386|FloatD, { FloatReg, FloatAcc, 0} },
+{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|Intel386|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-#if SYSV386_COMPAT
/* alias for fdivp */
-{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} },
-#endif
+{"fdiv", 0, 0xdef1, X, 0, FP|Ugh|SystemV386, { 0, 0, 0} },
{"fdiv", 1, 0xd8, 6, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
{"fidiv", 1, 0xde, 6, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
-#if SYSV386_COMPAT
-{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
-{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
-#if OLDGCC_COMPAT
-{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
-#endif
-#else
-{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
-{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
-#endif
+{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|SystemV386, { FloatAcc, FloatReg, 0} },
+{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm|SystemV386, { FloatReg, 0, 0} },
+{"fdivp", 0, 0xdef1, X, 0, FP|SystemV386, { 0, 0, 0} },
+{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh|SystemV386, { FloatReg, FloatAcc, 0} },
+{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm|Intel386, { FloatAcc, FloatReg, 0} },
+{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm|Intel386, { FloatReg, 0, 0} },
+{"fdivp", 0, 0xdef9, X, 0, FP|Intel386, { 0, 0, 0} },
/* divide reverse */
-{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
+{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|SystemV386|FloatD, { FloatReg, FloatAcc, 0} },
+{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|Intel386|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-#if SYSV386_COMPAT
/* alias for fdivrp */
-{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} },
-#endif
+{"fdivr", 0, 0xdef9, X, 0, FP|Ugh|SystemV386, { 0, 0, 0} },
{"fdivr", 1, 0xd8, 7, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
{"fidivr", 1, 0xde, 7, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
-#if SYSV386_COMPAT
-{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
-{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
-#if OLDGCC_COMPAT
-{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
-#endif
-#else
-{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
-{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
-#endif
+{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|SystemV386, { FloatAcc, FloatReg, 0} },
+{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm|SystemV386, { FloatReg, 0, 0} },
+{"fdivrp", 0, 0xdef9, X, 0, FP|SystemV386, { 0, 0, 0} },
+{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh|SystemV386, { FloatReg, FloatAcc, 0} },
+{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm|Intel386, { FloatAcc, FloatReg, 0} },
+{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm|Intel386, { FloatReg, 0, 0} },
+{"fdivrp", 0, 0xdef1, X, 0, FP|Intel386, { 0, 0, 0} },
{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} },
{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} },