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Thumb-2 unified asm


The patch below ensures that Thumb-2 instructions are not accepted when 
assembling for Thumb-1 cores.  Some of the error messages generated are 
fairly lame, but it's better than silently accepting/generating invalid code.

Tested on arm-none-eabi.
Applied ot CVS head.

Paul

2007-04-19  Paul Brook  <paul@codesourcery.com>

	gas/testsuite/
	* gas/arm/thumb1_unified.d: New test.
	* gas/arm/thumb1_unified.s: New test.

	gas/
	* config/tc-arm.c (md_assemble): Only allow 16-bit instructions on
	Thumb-1.  Add sanity check for bogus relaxations.

Index: gas/testsuite/gas/arm/thumb1_unified.d
===================================================================
--- gas/testsuite/gas/arm/thumb1_unified.d	(revision 0)
+++ gas/testsuite/gas/arm/thumb1_unified.d	(revision 0)
@@ -0,0 +1,20 @@
+# name: Thumb-1 unified
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> 200c      	movs	r0, #12
+0[0-9a-f]+ <[^>]+> 1cd1      	adds	r1, r2, #3
+0[0-9a-f]+ <[^>]+> 1ed1      	subs	r1, r2, #3
+0[0-9a-f]+ <[^>]+> 3364      	adds	r3, #100
+0[0-9a-f]+ <[^>]+> 3c83      	subs	r4, #131
+0[0-9a-f]+ <[^>]+> 2d27      	cmp	r5, #39
+0[0-9a-f]+ <[^>]+> a103      	add	r1, pc, #12	\(adr [^)]*\)
+0[0-9a-f]+ <[^>]+> 4a03      	ldr	r2, \[pc, #12\]	\([^)]*\)
+0[0-9a-f]+ <[^>]+> 6863      	ldr	r3, \[r4, #4\]
+0[0-9a-f]+ <[^>]+> 9d01      	ldr	r5, \[sp, #4\]
+0[0-9a-f]+ <[^>]+> b001      	add	sp, #4
+0[0-9a-f]+ <[^>]+> b081      	sub	sp, #4
+0[0-9a-f]+ <[^>]+> af01      	add	r7, sp, #4
+0[0-9a-f]+ <[^>]+> 4251      	negs	r1, r2
Index: gas/testsuite/gas/arm/thumb1_unified.s
===================================================================
--- gas/testsuite/gas/arm/thumb1_unified.s	(revision 0)
+++ gas/testsuite/gas/arm/thumb1_unified.s	(revision 0)
@@ -0,0 +1,25 @@
+.text
+.arch armv4t
+.syntax unified
+.thumb
+foo:
+movs r0, #12
+adds r1, r2, #3
+subs r1, r2, #3
+adds r3, r3, #0x64
+subs r4, r4, #0x83
+cmp r5, #0x27
+
+adr r1, bar
+ldr r2, bar
+ldr r3, [r4, #4]
+ldr r5, [sp, #4]
+add sp, sp, #4
+sub sp, sp, #4
+add r7, sp, #4
+
+rsbs r1, r2, #0
+
+.align 2
+bar:
+
Index: gas/config/tc-arm.c
===================================================================
--- gas/config/tc-arm.c	(revision 169208)
+++ gas/config/tc-arm.c	(working copy)
@@ -14077,6 +14077,14 @@ md_assemble (char *str)
 	  return;
 	}
 
+      if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
+	{
+	  /* Implicit require narrow instructions on Thumb-1.  This avoids
+	     relaxation accidentally introducing Thumb-2 instructions.  */
+	  if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
+	    inst.size_req = 2;
+	}
+
       /* Check conditional suffixes.  */
       if (current_it_mask)
 	{
@@ -14118,6 +14127,11 @@ md_assemble (char *str)
 	      return;
 	    }
 	}
+
+      /* Something has gone badly wrong if we try to relax a fixed size
+         instruction.  */
+      assert (inst.size_req == 0 || !inst.relax);
+
       ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
 			      *opcode->tvariant);
       /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly


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