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PATCH: Rename regKludge to RegKludge
- From: "H. J. Lu" <hjl at lucon dot org>
- To: binutils at sources dot redhat dot com
- Date: Mon, 25 Jun 2007 14:02:24 -0700
- Subject: PATCH: Rename regKludge to RegKludge
This patch changes regKludge in opcodes/i386-opc.h to RegKludge.
H.J.
----
gas/
2007-06-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Replace regKludge
with RegKludge.
opcodes/
2007-06-25 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (regKludge): Renamed to ...
(RegKludge): This.
* i386-opc.c (i386_optab): Replace regKludge with RegKludge.
--- binutils/gas/config/tc-i386.c.reg 2007-06-22 09:04:49.000000000 -0700
+++ binutils/gas/config/tc-i386.c 2007-06-25 13:54:40.000000000 -0700
@@ -3324,7 +3324,7 @@ process_operands (void)
/* The imul $imm, %reg instruction is converted into
imul $imm, %reg, %reg, and the clr %reg instruction
is converted into xor %reg, %reg. */
- if (i.tm.opcode_modifier & regKludge)
+ if (i.tm.opcode_modifier & RegKludge)
{
if ((i.tm.cpu_flags & CpuSSE4_1))
{
--- binutils/opcodes/i386-opc.c.reg 2007-05-03 17:57:24.000000000 -0700
+++ binutils/opcodes/i386-opc.c 2007-06-25 13:54:16.000000000 -0700
@@ -234,7 +234,7 @@ const template i386_optab[] =
{"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
/* clr with 1 operand is really xor with 2 operands. */
-{"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
+{"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|RegKludge, { Reg, 0, 0 } },
{"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
@@ -279,10 +279,10 @@ const template i386_optab[] =
{"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} },
{"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} },
/* imul with 2 operands mimics imul with 3 by putting the register in
- both i.rm.reg & i.rm.regmem fields. regKludge enables this
+ both i.rm.reg & i.rm.regmem fields. RegKludge enables this
transformation. */
-{"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
-{"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} },
+{"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|RegKludge,{ Imm8S, WordReg, 0} },
+{"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|RegKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} },
{"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
{"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
@@ -1388,8 +1388,8 @@ const template i386_optab[] =
{"blendpd", 3, 0x660f3a0d,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"blendps", 3, 0x660f3a0c,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
-{"blendvpd", 3, 0x660f3815,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
-{"blendvps", 3, 0x660f3814,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"blendvpd", 3, 0x660f3815,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|RegKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"blendvps", 3, 0x660f3814,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|RegKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
{"dppd", 3, 0x660f3a41,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"dpps", 3, 0x660f3a40,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"extractps",3, 0x660f3a17,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, Reg32|Reg64|LongMem } },
@@ -1397,7 +1397,7 @@ const template i386_optab[] =
{"movntdqa", 2, 0x660f382a,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
{"mpsadbw", 3, 0x660f3a42,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"packusdw", 2, 0x660f382b,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pblendvb", 3, 0x660f3810,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"pblendvb", 3, 0x660f3810,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|RegKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
{"pblendw", 3, 0x660f3a0e,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"pcmpeqq", 2, 0x660f3829,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"pextrb", 3, 0x660f3a14,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, Reg32|Reg64|ByteMem } },
--- binutils/opcodes/i386-opc.h.reg 2007-05-10 11:21:34.000000000 -0700
+++ binutils/opcodes/i386-opc.h 2007-06-25 13:54:21.000000000 -0700
@@ -116,7 +116,7 @@ typedef struct template
#define No_xSuf 0x200000 /* x suffix on instruction illegal */
#define FWait 0x400000 /* instruction needs FWAIT */
#define IsString 0x800000 /* quick test for string instructions */
-#define regKludge 0x1000000 /* fake an extra reg operand for clr, imul
+#define RegKludge 0x1000000 /* fake an extra reg operand for clr, imul
and special register processing for
some instructions. */
#define IsPrefix 0x2000000 /* opcode is a prefix */