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Re: Loongson-2E and -2F support for binutils
- From: Zhang Le <r0bertz at gentoo dot org>
- To: Mark Shinwell <shinwell at codesourcery dot com>
- Cc: binutils at sourceware dot org
- Date: Thu, 29 Nov 2007 14:23:04 +0800
- Subject: Re: Loongson-2E and -2F support for binutils
- Openpgp: id=1E4E2973
- References: <474D57E3.1090405@codesourcery.com>
Hi, Mark!
Glad to see your work! Actually I have received some advice from ths and I
have modified my patch accordingly. My patch(in the attachment) now looks like
your patch very much in many aspects. The only thing missing is the testsuite.
Moreover, we don't have 2f cores at hands, neither any handbooks about 2f. So
2f part is absent in our patch.
Mark Shinwell wrote:
> This patch provides binutils support for the Loongson 2E and 2F cores.
> (Zhang -- I see you've just posted support for the 2E as well; some
> coordination may be needed here. Your patch names the fixed point
> instructions differently; why is that?)
As I said before, I am not the author of the patch to mips-opc.c and I haven't
found the author yet. I posted the patch here just want to hear your advice
about it, let you know we have been working on it and if ever possible, accept
this patch. :) Since now you have come up with a better patch, we'd better
stick with yours.
However I have one question though. In include/elf/mips.h:
+#define E_MIPS_MACH_LS2E 0x00A00000
+#define E_MIPS_MACH_LS2F 0x00A10000
How about we define them as 0x00B00000 and 0x00B10000 respectively. Maybe
there will be loongson 1 coming in the future, so leave 0x00A00000 for them.
Thanks again for your work!
--
Zhang Le, Robert
GPG key ID: 1E4E2973
Fingerprint: 0260 C902 B8F8 6506 6586 2B90 BC51 C808 1E4E 2973
Index: bfd/ChangeLog
===================================================================
RCS file: /cvs/src/src/bfd/ChangeLog,v
retrieving revision 1.4073
diff -u -r1.4073 ChangeLog
--- bfd/ChangeLog 21 Nov 2007 12:06:24 -0000 1.4073
+++ bfd/ChangeLog 27 Nov 2007 16:36:57 -0000
@@ -1,3 +1,14 @@
+2007-11-26 Zhang Le <r0bertz@gentoo.org>
+ Ruan Beihong <ruanbeihong@gmail.com>
+ Liu Xinghua <yixiu@loongcore.org>
+
+ * aoutx.h (NAME (aout, machine_type)): Add support for loongson2.
+ * archures.c (bfd_architecture): Likewise.
+ * cpu-mips.c (arch_info_struct): Likewise.
+ * elfxx-mips.c (_bfd_elf_mips_mach): Likewise.
+ (mips_set_isa_flags): Likewise.
+ (mips_mach_extensions): Likewise.
+
2007-11-21 Nick Clifton <nickc@redhat.com>
* elf-m10300.c (mn10300_elf_relax_section): Allow for alignment
Index: bfd/aoutx.h
===================================================================
RCS file: /cvs/src/src/bfd/aoutx.h,v
retrieving revision 1.72
diff -u -r1.72 aoutx.h
--- bfd/aoutx.h 9 Aug 2007 23:14:55 -0000 1.72
+++ bfd/aoutx.h 27 Nov 2007 16:36:57 -0000
@@ -793,6 +793,7 @@
case bfd_mach_mipsisa64:
case bfd_mach_mipsisa64r2:
case bfd_mach_mips_sb1:
+ case bfd_mach_mips_ls2e:
/* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
arch_flags = M_MIPS2;
break;
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.128
diff -u -r1.128 archures.c
--- bfd/archures.c 11 Sep 2007 16:07:49 -0000 1.128
+++ bfd/archures.c 27 Nov 2007 16:36:57 -0000
@@ -170,6 +170,7 @@
.#define bfd_mach_mips16 16
.#define bfd_mach_mips5 5
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_ls2e 76835069 {* decimal 'LS2E' *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
.#define bfd_mach_mipsisa64 64
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.27
diff -u -r1.27 cpu-mips.c
--- bfd/cpu-mips.c 3 Jul 2007 14:26:40 -0000 1.27
+++ bfd/cpu-mips.c 27 Nov 2007 16:36:57 -0000
@@ -87,6 +87,7 @@
I_mipsisa64,
I_mipsisa64r2,
I_sb1,
+ I_ls2e,
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -119,7 +120,8 @@
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
+ N (64, 64, bfd_mach_mips_ls2e, "mips:ls2e", FALSE, 0),
};
/* The default architecture is mips:3000, but with a machine number of
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.222
diff -u -r1.222 elfxx-mips.c
--- bfd/elfxx-mips.c 17 Nov 2007 13:38:56 -0000 1.222
+++ bfd/elfxx-mips.c 27 Nov 2007 16:36:57 -0000
@@ -5221,6 +5221,9 @@
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
+ case E_MIPS_MACH_LS2E:
+ return bfd_mach_mips_ls2e;
+
default:
switch (flags & EF_MIPS_ARCH)
{
@@ -9418,6 +9421,10 @@
val = E_MIPS_ARCH_3;
break;
+ case bfd_mach_mips_ls2e:
+ val= E_MIPS_ARCH_3 | E_MIPS_MACH_LS2E;
+ break;
+
case bfd_mach_mips4010:
val = E_MIPS_ARCH_3 | E_MIPS_MACH_4010;
break;
@@ -11228,6 +11235,7 @@
{ bfd_mach_mips4111, bfd_mach_mips4100 },
/* MIPS III extensions. */
+ { bfd_mach_mips_ls2e, bfd_mach_mips4000 },
{ bfd_mach_mips8000, bfd_mach_mips4000 },
{ bfd_mach_mips4650, bfd_mach_mips4000 },
{ bfd_mach_mips4600, bfd_mach_mips4000 },
Index: binutils/ChangeLog
===================================================================
RCS file: /cvs/src/src/binutils/ChangeLog,v
retrieving revision 1.1271
diff -u -r1.1271 ChangeLog
--- binutils/ChangeLog 26 Nov 2007 01:53:59 -0000 1.1271
+++ binutils/ChangeLog 27 Nov 2007 16:36:58 -0000
@@ -1,3 +1,9 @@
+2007-11-26 Zhang Le <r0bertz@gentoo.org>
+ Ruan Beihong <ruanbeihong@gmail.com>
+ Liu Xinghua <yixiu@loongcore.org>
+
+ * readelf.c (get_machine_flags): Add support for loongson2
+
2007-11-26 Alan Modra <amodra@bigpond.net.au>
* cxxfilt.c (demangle_it): Don't call printf without format string.
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.391
diff -u -r1.391 readelf.c
--- binutils/readelf.c 19 Nov 2007 12:01:42 -0000 1.391
+++ binutils/readelf.c 27 Nov 2007 16:36:58 -0000
@@ -2193,6 +2193,7 @@
case E_MIPS_MACH_5400: strcat (buf, ", 5400"); break;
case E_MIPS_MACH_5500: strcat (buf, ", 5500"); break;
case E_MIPS_MACH_SB1: strcat (buf, ", sb1"); break;
+ case E_MIPS_MACH_LS2E: strcat (buf, ", ls2e"); break;
case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
case 0:
/* We simply ignore the field in this case to avoid confusion:
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.3427
diff -u -r1.3427 ChangeLog
--- gas/ChangeLog 26 Nov 2007 01:43:43 -0000 1.3427
+++ gas/ChangeLog 27 Nov 2007 16:36:59 -0000
@@ -1,3 +1,10 @@
+2007-11-26 Zhang Le <r0bertz@gentoo.org>
+ Ruan Beihong <ruanbeihong@gmail.com>
+ Liu Xinghua <yixiu@loongcore.org>
+
+ * doc/c-mips.texi: Add support for loongson2.
+ * config/tc-mips.c (mips_cpu_info_table): Likewise.
+
2007-11-26 Thomas Ogrisegg <tom-bugs@gas.fnord.at>
* config/tc-alpha.c (assemble_insn): Don't segv on NULL reloc_operand.
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.378
diff -u -r1.378 tc-mips.c
--- gas/config/tc-mips.c 17 Nov 2007 14:19:19 -0000 1.378
+++ gas/config/tc-mips.c 27 Nov 2007 16:37:00 -0000
@@ -14733,6 +14733,7 @@
{ "r4600", 0, ISA_MIPS3, CPU_R4600 },
{ "orion", 0, ISA_MIPS3, CPU_R4600 },
{ "r4650", 0, ISA_MIPS3, CPU_R4650 },
+ { "ls2e", 0, ISA_MIPS3, CPU_LS2E},
/* MIPS IV */
{ "r8000", 0, ISA_MIPS4, CPU_R8000 },
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.43
diff -u -r1.43 c-mips.texi
--- gas/doc/c-mips.texi 4 Jul 2007 19:55:18 -0000 1.43
+++ gas/doc/c-mips.texi 27 Nov 2007 16:37:00 -0000
@@ -270,7 +270,8 @@
20kc,
25kf,
sb1,
-sb1a
+sb1a,
+ls2e
@end quotation
For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.1261
diff -u -r1.1261 ChangeLog
--- gas/testsuite/ChangeLog 27 Nov 2007 15:31:58 -0000 1.1261
+++ gas/testsuite/ChangeLog 27 Nov 2007 16:37:00 -0000
@@ -1,3 +1,9 @@
+2007-11-27 Zhang Le <r0bertz@gentoo.org>
+ Ruan Beihong <ruanbeihong@gmail.com>
+ Liu Xinghua <yixiu@loongcore.org>
+
+ * gas/mips/mips.exp: Add support for loongson2.
+
2007-11-27 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z9-ec.d: ("tcet", "tcdt", "tcxt", "tget",
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.132
diff -u -r1.132 mips.exp
--- gas/testsuite/gas/mips/mips.exp 8 Oct 2007 16:41:34 -0000 1.132
+++ gas/testsuite/gas/mips/mips.exp 27 Nov 2007 16:37:00 -0000
@@ -360,7 +360,9 @@
{ -march=vr5400 -mtune=vr5400 } { -mmips:5400 }
mips_arch_create sb1 64 mips64 { mips3d } \
{ -march=sb1 -mtune=sb1 } { -mmips:sb1 } \
- { mipsisa64sb1-*-* mipsisa64sb1el-*-* }
+ { mipsisa64sb1-*-* mipsisa64sb1el-*-* } \
+mips_arch_create ls2e 64 mips3 {} \
+ { -march=ls2e -mtune=ls2e } { -mmips:ls2e }
#
# And now begin the actual tests! VxWorks uses RELA rather than REL
Index: include/elf/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/elf/ChangeLog,v
retrieving revision 1.309
diff -u -r1.309 ChangeLog
--- include/elf/ChangeLog 16 Nov 2007 15:36:21 -0000 1.309
+++ include/elf/ChangeLog 27 Nov 2007 16:37:02 -0000
@@ -1,3 +1,9 @@
+2007-11-26 Zhang Le <r0bertz@gentoo.org>
+ Ruan Beihong <ruanbeihong@gmail.com>
+ Liu Xinghua <yixiu@loongcore.org>
+
+ * mips.h: Add support for loongson2
+
2007-11-16 Nick Clifton <nickc@redhat.com>
* dwarf2.h: Mention the location of the DWARF3 spec on the web.
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.34
diff -u -r1.34 mips.h
--- include/elf/mips.h 17 Nov 2007 13:38:57 -0000 1.34
+++ include/elf/mips.h 27 Nov 2007 16:37:03 -0000
@@ -216,6 +216,7 @@
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
+#define E_MIPS_MACH_LS2E 0x00b20000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.351
diff -u -r1.351 ChangeLog
--- include/opcode/ChangeLog 24 Aug 2007 00:56:30 -0000 1.351
+++ include/opcode/ChangeLog 27 Nov 2007 16:37:03 -0000
@@ -1,3 +1,9 @@
+2007-11-26 Zhang Le <r0bertz@gentoo.org>
+ Ruan Beihong <ruanbeihong@gmail.com>
+ Liu Xinghua <yixiu@loongcore.org>
+
+ * mips.h: Add support for loongson2
+
2007-08-08 Ben Elliston <bje@au.ibm.com>
* ppc.h (PPC_OPCODE_PPCPS): New.
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.53
diff -u -r1.53 mips.h
--- include/opcode/mips.h 20 Feb 2007 13:28:54 -0000 1.53
+++ include/opcode/mips.h 27 Nov 2007 16:37:03 -0000
@@ -529,6 +529,8 @@
#define INSN_SMARTMIPS 0x10000000
/* DSP R2 ASE */
#define INSN_DSPR2 0x20000000
+/* Lemote Loongson2E instruction. */
+#define INSN_LS2E 0x40000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -576,6 +578,7 @@
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
+#define CPU_LS2E 76835069 /* decimal 'LS2E'. */
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@@ -593,6 +596,7 @@
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
&& ((insn)->membership & INSN_10000) != 0) \
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
+ || (cpu == CPU_LS2E && ((insn)->membership & INSN_LS2E) != 0) \
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.1194
diff -u -r1.1194 ChangeLog
--- opcodes/ChangeLog 27 Nov 2007 15:31:57 -0000 1.1194
+++ opcodes/ChangeLog 27 Nov 2007 16:37:06 -0000
@@ -1,3 +1,9 @@
+2007-11-27 Zhang Le <r0bertz@gentoo.org>
+ Sun Haiyong <youbest@sina.com>
+
+ * mips-dis.c (mips_arch_choices): Add support for loongson2
+ * mips-opc.c (mips_builtin_opcodes): Likewise
+
2007-11-27 Andreas Krebbel <krebbel1@de.ibm.com>
* s390-opc.txt ("tcet", "tcdt", "tcxt", "tget", "tgdt",
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.68
diff -u -r1.68 mips-dis.c
--- opcodes/mips-dis.c 8 Oct 2007 16:41:35 -0000 1.68
+++ opcodes/mips-dis.c 27 Nov 2007 16:37:06 -0000
@@ -391,6 +391,8 @@
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ { "ls2e", 1, bfd_mach_mips_ls2e, CPU_LS2E, ISA_MIPS3 | INSN_LS2E,
+ mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.62
diff -u -r1.62 mips-opc.c
--- opcodes/mips-opc.c 4 Oct 2007 21:53:06 -0000 1.62
+++ opcodes/mips-opc.c 27 Nov 2007 16:37:07 -0000
@@ -108,6 +108,7 @@
#define T3 INSN_3900
#define M1 INSN_10000
#define SB1 INSN_SB1
+#define LS2E INSN_LS2E
#define N411 INSN_4111
#define N412 INSN_4120
#define N5 (INSN_5400 | INSN_5500)
@@ -1692,6 +1693,113 @@
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
+
+/* Loongson2E extensions */
+{"faddu", "D,V,T", 0x45800000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"for", "D,V,T", 0x45a00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fadd", "D,V,T", 0x45c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fdadd", "D,V,T", 0x45e00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pavgh", "D,V,T", 0x46400000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pavgb", "D,V,T", 0x46600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pmaxsh", "D,V,T", 0x46800000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pminsh", "D,V,T", 0x46a00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pmaxub", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pminub", "D,V,T", 0x46e00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"paddsh", "D,V,T", 0x47000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"paddush", "D,V,T", 0x47200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"paddh", "D,V,T", 0x47400000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"paddw", "D,V,T", 0x47600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"paddsb", "D,V,T", 0x47800000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"paddusb", "D,V,T", 0x47a00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"paddb", "D,V,T", 0x47c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"paddd", "D,V,T", 0x47e00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fsubu", "D,V,T", 0x45800001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pasubub", "D,V,T", 0x45a00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fsub", "D,V,T", 0x45c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fdsub", "D,V,T", 0x45e00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pcmpeqw", "D,V,T", 0x46400001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pcmpgtw", "D,V,T", 0x46600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pcmpeqh", "D,V,T", 0x46800001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pcmpgth", "D,V,T", 0x46a00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pcmpeqb", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pcmpgtb", "D,V,T", 0x46e00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psubsh", "D,V,T", 0x47000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psubush", "D,V,T", 0x47200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psubh", "D,V,T", 0x47400001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psubw", "D,V,T", 0x47600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psubsb", "D,V,T", 0x47800001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psubusb", "D,V,T", 0x47a00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psubb", "D,V,T", 0x47c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psubd", "D,V,T", 0x47e00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fsll", "D,V,T", 0x45800002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fdsll", "D,V,T", 0x45a00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pextrh", "D,V,T", 0x45c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pmaddhw", "D,V,T", 0x45e00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psllw", "D,V,T", 0x46400002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psllh", "D,V,T", 0x46600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pmullh", "D,V,T", 0x46800002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pmulhh", "D,V,T", 0x46a00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pmuluw", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pmulhuh", "D,V,T", 0x46e00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pshufh", "D,V,T", 0x47000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"packsswh", "D,V,T", 0x47200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"packsshb", "D,V,T", 0x47400002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"packushb", "D,V,T", 0x47600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fxor", "D,V,T", 0x47800002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fnor", "D,V,T", 0x47a00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fand", "D,V,T", 0x47c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pandn", "D,V,T", 0x47e00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fsrl", "D,V,T", 0x45800003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fdsrl", "D,V,T", 0x45a00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fsra", "D,V,T", 0x45c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fdsra", "D,V,T", 0x45e00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psrlw", "D,V,T", 0x46400003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psrlh", "D,V,T", 0x46600003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psraw", "D,V,T", 0x46800003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"psrah", "D,V,T", 0x46a00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"punpcklwd", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"punpckhwd", "D,V,T", 0x46e00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"punpcklhw", "D,V,T", 0x47000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"punpckhhw", "D,V,T", 0x47200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"punpcklbh", "D,V,T", 0x47400003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"punpckhbh", "D,V,T", 0x47600003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pinsrh_0", "D,V,T", 0x47800003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pinsrh_1", "D,V,T", 0x47a00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pinsrh_2", "D,V,T", 0x47c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"pinsrh_3", "D,V,T", 0x47e00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"fseq", "S,T", 0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"fseq1", "S,T", 0x46a00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"fsltu", "S,T", 0x4680003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"fslt", "S,T", 0x46a0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"fsleu", "S,T", 0x4680003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"fsle", "S,T", 0x46a0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"biadd", "D,V", 0x46800005, 0xffff003f, WR_D|RD_S|FP_D, 0, LS2E },
+{"pmovmskb", "D,V", 0x46a00005, 0xffff003f, WR_D|RD_S|FP_D, 0, LS2E },
+
+/* Loongson2E paired single */
+{"add.gps", "D,V,T", 0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"sub.gps", "D,V,T", 0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"mul.gps", "D,V,T", 0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, LS2E },
+{"abs.gps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, LS2E },
+{"mov.gps", "D,S", 0x45600006, 0xffff003f, WR_D|RD_S|FP_D, 0, LS2E },
+{"neg.gps", "D,V", 0x45600007, 0xffff003f, WR_D|RD_S|FP_D, 0, LS2E },
+{"c.f.gps", "S,T", 0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.un.gps", "S,T", 0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.eq.gps", "S,T", 0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.ueq.gps", "S,T", 0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.olt.gps", "S,T", 0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.ult.gps", "S,T", 0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.ole.gps", "S,T", 0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.ule.gps", "S,T", 0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.sf.gps", "S,T", 0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.ngle.gps", "S,T", 0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.seq.gps", "S,T", 0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.ngl.gps", "S,T", 0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.lt.gps", "S,T", 0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.nge.gps", "S,T", 0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.le.gps", "S,T", 0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+{"c.ngt.gps", "S,T", 0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, LS2E },
+
};
#define MIPS_NUM_OPCODES \