This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH, MIPS] Add new Octeon configuration
- From: Adam Nemet <anemet at caviumnetworks dot com>
- To: binutils at sourceware dot org
- Date: Sun, 3 Feb 2008 11:08:43 -0800
- Subject: [PATCH, MIPS] Add new Octeon configuration
The Octeon instruction set is an extension of the standard MIPS64r2 ISA. A
description of the new instructions is avaible from cnusers.org under
Downloads -> Downloads for Non-Registered Users -> cnMIPS Instruction Set
Manual (or
http://www.cnusers.org/index.php?option=com_remository&Itemid=32&func=startdown&id=48).
This is the first of several patches and it adds the intitial configuration
bits. I am only adding one instruction for now to test the infrastructure. I
will submit separate patches with further instructions.
We support a GNU/Linux and an ELF target for Octeon. This patch contains the
linux part under the new target name mips64octeon-*-linux-gnu. I will add the
ELF target later.
Regarding the EF_MIPS_MACH value, we've been using 0x8b internally which is
not yet taken. So it would be nice if we could keep this.
Thanks to Mark Shinwell
(http://sourceware.org/ml/binutils/2007-11/msg00231.html) there is now room
for new INSN* masks. For INSN_OCTEON, I started filling the new bits backward
to leave room for new ISAs. I also added a similar macro to INSN_ASE_MASK to
show which bits are already taken.
I tested the patch with gas, binutils and ld. I compared the results to
mips64-uknown-linux-gnu results. (This is after locking mips_cpu from
from-abi to mips64 in gas for obvious reasons.) The only difference is that
the DSP tests are failing for Octeon. opcodes wants me to define Octeon an
INSN_DSP processor -- which it is not -- in order to display DSP instructions
compiled with -mdsp. This is not Octeon-related and I am planning to address
this in a follow-up patch.
OK?
Adam
bfd/
* archures.c: Update copyright.
(bfd_mach_mips_octeon): New macro.
* bfd-in2.h: Regenerate.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle Octeon.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Add Octeon.
* cpu-mips.c: Update copyright.
(I_mipsocteon): New enum constant.
(arch_info_struct): Add Octeon.
binutils/
* readelf.c (get_machine_flags): Handle Octeon.
gas/
* config/tc-mips.c (mips_cpu_info_table): Add Octeon.
gas/testsuite/
* gas/mips/mips.exp: Call mips_arch_create for Octeon. Invoke
Octeon tests.
* gas/mips/octeon.s, gas/mips/octeon.d: New test.
include/elf/
* mips.h: Update copyright.
(E_MIPS_MACH_OCTEON): New macro.
include/opcode/
* mips.h: Update copyright.
(INSN_CHIP_MASK): New macro.
(INSN_OCTEON): New macro.
(CPU_OCTEON): New macro.
(OPCODE_IS_MEMBER): Handle Octeon instructions.
(INSN_MDMX, INSN_MT, INSN_SMARTMIPS, INSN_DSPR2): Move these up
opcodes/
* mips-dis.c: Update copyright.
(mips_arch_choices): Add Octeon.
* mips-opc.c: Update copyright.
(IOCT): New macro.
(mips_builtin_opcodes): Add Octeon instruction synciobdma.
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.129
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.129 archures.c
--- bfd/archures.c 29 Nov 2007 12:23:43 -0000 1.129
+++ bfd/archures.c 3 Feb 2008 18:46:56 -0000
@@ -1,6 +1,6 @@
/* BFD library support routines for architectures.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
Free Software Foundation, Inc.
Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
@@ -172,6 +172,7 @@ DESCRIPTION
.#define bfd_mach_mips_loongson_2e 3001
.#define bfd_mach_mips_loongson_2f 3002
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
.#define bfd_mach_mipsisa64 64
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.28
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.28 cpu-mips.c
--- bfd/cpu-mips.c 29 Nov 2007 12:23:43 -0000 1.28
+++ bfd/cpu-mips.c 3 Feb 2008 18:46:58 -0000
@@ -1,6 +1,6 @@
/* bfd back-end for mips support
Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001,
- 2002, 2003, 2004, 2007 Free Software Foundation, Inc.
+ 2002, 2003, 2004, 2007, 2008 Free Software Foundation, Inc.
Written by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
@@ -88,7 +88,8 @@ enum
I_mipsisa64r2,
I_sb1,
I_loongson_2e,
- I_loongson_2f
+ I_loongson_2f,
+ I_mipsocteon
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -123,7 +124,8 @@ static const bfd_arch_info_type arch_inf
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
- N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, 0)
+ N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
+ N (64, 64, bfd_mach_mips_octeon, "mips:octeon", FALSE, 0)
};
/* The default architecture is mips:3000, but with a machine number of
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.224
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.224 elfxx-mips.c
--- bfd/elfxx-mips.c 11 Jan 2008 09:07:04 -0000 1.224
+++ bfd/elfxx-mips.c 3 Feb 2008 18:46:59 -0000
@@ -1,6 +1,6 @@
/* MIPS-specific support for ELF
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+ 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
Most of the information added by Ian Lance Taylor, Cygnus Support,
<ian@cygnus.com>.
@@ -5227,6 +5227,9 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_LS2F:
return bfd_mach_mips_loongson_2f;
+ case E_MIPS_MACH_OCTEON:
+ return bfd_mach_mips_octeon;
+
default:
switch (flags & EF_MIPS_ARCH)
{
@@ -9480,6 +9483,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
+ case bfd_mach_mips_octeon:
+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
+ break;
+
case bfd_mach_mipsisa32:
val = E_MIPS_ARCH_32;
break;
@@ -11215,6 +11222,9 @@ struct mips_mach_extension {
are ordered topologically with MIPS I extensions listed last. */
static const struct mips_mach_extension mips_mach_extensions[] = {
+ /* MIPS64r2 extensions. */
+ { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+
/* MIPS64 extensions. */
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
{ bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.399
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.399 readelf.c
--- binutils/readelf.c 30 Jan 2008 10:37:42 -0000 1.399
+++ binutils/readelf.c 3 Feb 2008 18:46:59 -0000
@@ -2260,6 +2260,7 @@ get_machine_flags (unsigned e_flags, uns
case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
+ case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
case 0:
/* We simply ignore the field in this case to avoid confusion:
MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.381
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.381 tc-mips.c
--- gas/config/tc-mips.c 2 Jan 2008 20:58:06 -0000 1.381
+++ gas/config/tc-mips.c 3 Feb 2008 18:47:00 -0000
@@ -14865,6 +14865,9 @@ static const struct mips_cpu_info mips_c
{ "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
{ "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
+ /* Cavium Networks Octeon CPU core */
+ { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
+
/* End marker */
{ NULL, 0, 0, 0 }
};
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.135
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.135 mips.exp
--- gas/testsuite/gas/mips/mips.exp 2 Jan 2008 20:59:46 -0000 1.135
+++ gas/testsuite/gas/mips/mips.exp 3 Feb 2008 18:47:01 -0000
@@ -361,6 +361,9 @@ mips_arch_create vr5400 64 mips4 { ror }
mips_arch_create sb1 64 mips64 { mips3d } \
{ -march=sb1 -mtune=sb1 } { -mmips:sb1 } \
{ mipsisa64sb1-*-* mipsisa64sb1el-*-* }
+mips_arch_create octeon 64 mips64r2 {} \
+ { -march=octeon -mtune=octeon } { -mmips:octeon } \
+ { mips64octeon-*-* }
#
# And now begin the actual tests! VxWorks uses RELA rather than REL
@@ -761,6 +764,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "loongson-2e"
run_dump_test "loongson-2f"
+ run_dump_test "octeon"
+
run_dump_test_arches "smartmips" [mips_arch_list_matching mips32 !gpr64]
run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32r2]
run_dump_test_arches "mips32-dspr2" [mips_arch_list_matching mips32r2]
Index: gas/testsuite/gas/mips/octeon.d
===================================================================
RCS file: gas/testsuite/gas/mips/octeon.d
diff -N gas/testsuite/gas/mips/octeon.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/octeon.d 3 Feb 2008 18:47:01 -0000
@@ -0,0 +1,11 @@
+#as: -march=octeon
+#objdump: -M reg-names=numeric -dr
+#name: MIPS octeon instructions
+
+.*: file format .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <sync_insns>:
+.*: 0000008f synciobdma
+#pass
Index: gas/testsuite/gas/mips/octeon.s
===================================================================
RCS file: gas/testsuite/gas/mips/octeon.s
diff -N gas/testsuite/gas/mips/octeon.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/octeon.s 3 Feb 2008 18:47:01 -0000
@@ -0,0 +1,6 @@
+ .text
+ .set noreorder
+
+sync_insns:
+ synciobdma
+
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.35
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.35 mips.h
--- include/elf/mips.h 29 Nov 2007 12:23:44 -0000 1.35
+++ include/elf/mips.h 3 Feb 2008 18:47:04 -0000
@@ -1,6 +1,6 @@
/* MIPS ELF support for BFD.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005
+ 2003, 2004, 2005, 2008
Free Software Foundation, Inc.
By Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>, from
@@ -213,6 +213,7 @@ #define E_MIPS_MACH_4650 0x00850000
#define E_MIPS_MACH_4120 0x00870000
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_SB1 0x008a0000
+#define E_MIPS_MACH_OCTEON 0x008b0000
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.55
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.55 mips.h
--- include/opcode/mips.h 29 Nov 2007 12:23:44 -0000 1.55
+++ include/opcode/mips.h 3 Feb 2008 18:47:05 -0000
@@ -1,6 +1,6 @@
/* mips.h. Mips opcode list for GDB, the GNU debugger.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005
+ 2003, 2004, 2005, 2008
Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
@@ -510,6 +510,12 @@ #define INSN_ISA5_32R2 14
static const unsigned int mips_isa_table[] =
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+/* Masks used for Chip specific instructions. */
+#define INSN_CHIP_MASK 0xc3ff0800
+
+/* Cavium Networks Octeon instructions. */
+#define INSN_OCTEON 0x00000800
+
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x3c00f000
@@ -521,8 +527,6 @@ #define INSN_MIPS16 0x0000
/* MIPS-3D ASE */
#define INSN_MIPS3D 0x00008000
-/* Chip specific instructions. These are bitmasks. */
-
/* MIPS R4650 instruction. */
#define INSN_4650 0x00010000
/* LSI R4010 instruction. */
@@ -605,6 +609,7 @@ #define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
+#define CPU_OCTEON 6501
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@@ -635,6 +640,8 @@ #define OPCODE_IS_MEMBER(insn, isa, cpu)
&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
|| (cpu == CPU_LOONGSON_2F \
&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
+ || (cpu == CPU_OCTEON \
+ && ((insn)->membership & INSN_OCTEON) != 0) \
|| 0) /* Please keep this term for easier source merging. */
/* This is a list of macro expanded instructions.
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.69
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.69 mips-dis.c
--- opcodes/mips-dis.c 29 Nov 2007 12:23:44 -0000 1.69
+++ opcodes/mips-dis.c 3 Feb 2008 18:47:10 -0000
@@ -1,6 +1,6 @@
/* Print mips instructions for GDB, the GNU debugger, or for objdump.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2005, 2007
+ 2000, 2001, 2002, 2003, 2005, 2007, 2008
Free Software Foundation, Inc.
Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
@@ -458,6 +458,10 @@ const struct mips_arch_choice mips_arch_
ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
+ { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
+ ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
+ mips_hwr_names_numeric },
+
/* This entry, mips16, is here only for ISA/processor selection; do
not print its name. */
{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.64
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.64 mips-opc.c
--- opcodes/mips-opc.c 29 Nov 2007 12:23:44 -0000 1.64
+++ opcodes/mips-opc.c 3 Feb 2008 18:47:10 -0000
@@ -1,6 +1,6 @@
/* mips-opc.c -- MIPS opcode list.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
- 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
+ 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -121,6 +121,7 @@ #define N412 INSN_4120
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
+#define IOCT INSN_OCTEON
#define G1 (T3 \
)
@@ -1295,6 +1296,7 @@ const struct mips_opcode mips_builtin_op
{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
+{"synciobdma", "", 0x0000008f, 0xffffffff, INSN_SYNC, 0, IOCT },
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },