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[PATCH] S/390: Add support for the System z10 Enterprise Class Mainframe
- From: "Andreas Krebbel" <Andreas dot Krebbel at de dot ibm dot com>
- To: binutils at sourceware dot org
- Cc: schwidefsky at de dot ibm dot com
- Date: Wed, 19 Mar 2008 10:35:52 +0100
- Subject: [PATCH] S/390: Add support for the System z10 Enterprise Class Mainframe
Hello,
the attached patch adds the new System z10 Enterprise Class
instructions as documented in:
http://publibz.boulder.ibm.com/epubs/pdf/dz9zr006.pdf
The patch also reworks the "automatic mnemonic extensions" I've added with:
http://sourceware.org/ml/binutils/2007-08/msg00314.html
Not all of the mnemonic extensions are appropriate for all conditional
instructions. So this patch limits the automatic extensions to a
common subset usable for conditional jumps as well as for compare and
branch instructions.
The new instructions are enabled with the -march=z10 option.
Tested on a System z10 EC machine. No regressions.
OK to apply?
Bye,
-Andreas-
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
(s390_cond_extensions): Reduced extensions to the compare related.
(main): z10 cpu type option added.
(expandConditionalJump): Renamed to ...
(insertExpandedMnemonic): ... this.
* opcodes/s390-opc.c: Re-group the operand format makros.
(INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI,
INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU,
INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0,
INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU,
INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU,
INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI,
INSTR_SIL_RDU): New instruction formats added.
(MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI,
MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0,
MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI,
MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR,
MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD,
MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format
masks added.
(s390_opformats): New formats added "ris", "rrs", "sil".
* opcodes/s390-opc.txt: Add the conditional jumps with the
extensions removed from automatic expansion in s390-mkopc.c manually.
(asi - trtre): Add new System z10 EC instructions.
* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z10 option added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z10.d: New file.
* gas/s390/zarch-z10.s: New file.
* gas/s390/s390.exp: Run the z10 testcases.
Index: gas/config/tc-s390.c
===================================================================
*** gas/config/tc-s390.c.orig 2008-03-18 17:57:42.000000000 +0100
--- gas/config/tc-s390.c 2008-03-18 18:28:03.000000000 +0100
*************** md_parse_option (c, arg)
*** 413,418 ****
--- 413,420 ----
current_cpu = S390_OPCODE_Z9_109;
else if (strcmp (arg + 5, "z9-ec") == 0)
current_cpu = S390_OPCODE_Z9_EC;
+ else if (strcmp (arg + 5, "z10") == 0)
+ current_cpu = S390_OPCODE_Z10;
else
{
as_bad (_("invalid switch -m%s"), arg);
Index: gas/testsuite/gas/s390/zarch-z10.d
===================================================================
*** /dev/null 1970-01-01 00:00:00.000000000 +0000
--- gas/testsuite/gas/s390/zarch-z10.d 2008-03-18 19:07:27.000000000 +0100
***************
*** 0 ****
--- 1,377 ----
+ #name: s390x opcode
+ #objdump: -drw
+
+ .*: +file format .*
+
+ Disassembly of section .text:
+
+ .* <foo>:
+ .*: eb d6 65 b3 01 6a [ ]*asi 5555\(%r6\),-42
+ .*: eb d6 65 b3 01 7a [ ]*agsi 5555\(%r6\),-42
+ .*: eb d6 65 b3 01 6e [ ]*alsi 5555\(%r6\),-42
+ .*: eb d6 65 b3 01 7e [ ]*algsi 5555\(%r6\),-42
+ .*: c6 6d 00 00 00 00 [ ]*crl %r6,18 <foo\+0x18>
+ .*: c6 68 00 00 00 00 [ ]*cgrl %r6,1e <foo\+0x1e>
+ .*: c6 6c 00 00 00 00 [ ]*cgfrl %r6,24 <foo\+0x24>
+ .*: ec 67 84 57 a0 f6 [ ]*crbhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 20 f6 [ ]*crbh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 30 f6 [ ]*crbnle %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 40 f6 [ ]*crbl %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 50 f6 [ ]*crbnhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 60 f6 [ ]*crblh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 70 f6 [ ]*crbne %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 80 f6 [ ]*crbe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 90 f6 [ ]*crbnlh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 a0 f6 [ ]*crbhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 b0 f6 [ ]*crbnl %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 c0 f6 [ ]*crble %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 d0 f6 [ ]*crbnh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 a0 e4 [ ]*cgrbhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 20 e4 [ ]*cgrbh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 30 e4 [ ]*cgrbnle %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 40 e4 [ ]*cgrbl %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 50 e4 [ ]*cgrbnhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 60 e4 [ ]*cgrblh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 70 e4 [ ]*cgrbne %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 80 e4 [ ]*cgrbe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 90 e4 [ ]*cgrbnlh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 a0 e4 [ ]*cgrbhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 b0 e4 [ ]*cgrbnl %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 c0 e4 [ ]*cgrble %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 d0 e4 [ ]*cgrbnh %r6,%r7,1111\(%r8\)
+ .*: ec 67 00 00 a0 76 [ ]*crj %r6,%r7,10,c6 <foo\+0xc6>
+ .*: ec 67 00 00 20 76 [ ]*crj %r6,%r7,2,cc <foo\+0xcc>
+ .*: ec 67 00 00 30 76 [ ]*crj %r6,%r7,3,d2 <foo\+0xd2>
+ .*: ec 67 00 00 40 76 [ ]*crj %r6,%r7,4,d8 <foo\+0xd8>
+ .*: ec 67 00 00 50 76 [ ]*crj %r6,%r7,5,de <foo\+0xde>
+ .*: ec 67 00 00 60 76 [ ]*crj %r6,%r7,6,e4 <foo\+0xe4>
+ .*: ec 67 00 00 70 76 [ ]*crj %r6,%r7,7,ea <foo\+0xea>
+ .*: ec 67 00 00 80 76 [ ]*crj %r6,%r7,8,f0 <foo\+0xf0>
+ .*: ec 67 00 00 90 76 [ ]*crj %r6,%r7,9,f6 <foo\+0xf6>
+ .*: ec 67 00 00 a0 76 [ ]*crj %r6,%r7,10,fc <foo\+0xfc>
+ .*: ec 67 00 00 b0 76 [ ]*crj %r6,%r7,11,102 <foo\+0x102>
+ .*: ec 67 00 00 c0 76 [ ]*crj %r6,%r7,12,108 <foo\+0x108>
+ .*: ec 67 00 00 d0 76 [ ]*crj %r6,%r7,13,10e <foo\+0x10e>
+ .*: ec 67 00 00 a0 64 [ ]*cgrjhe %r6,%r7,114 <foo\+0x114>
+ .*: ec 67 00 00 20 64 [ ]*cgrjh %r6,%r7,11a <foo\+0x11a>
+ .*: ec 67 00 00 30 64 [ ]*cgrjnle %r6,%r7,120 <foo\+0x120>
+ .*: ec 67 00 00 40 64 [ ]*cgrjl %r6,%r7,126 <foo\+0x126>
+ .*: ec 67 00 00 50 64 [ ]*cgrjnhe %r6,%r7,12c <foo\+0x12c>
+ .*: ec 67 00 00 60 64 [ ]*cgrjlh %r6,%r7,132 <foo\+0x132>
+ .*: ec 67 00 00 70 64 [ ]*cgrjne %r6,%r7,138 <foo\+0x138>
+ .*: ec 67 00 00 80 64 [ ]*cgrje %r6,%r7,13e <foo\+0x13e>
+ .*: ec 67 00 00 90 64 [ ]*cgrjnlh %r6,%r7,144 <foo\+0x144>
+ .*: ec 67 00 00 a0 64 [ ]*cgrjhe %r6,%r7,14a <foo\+0x14a>
+ .*: ec 67 00 00 b0 64 [ ]*cgrjnl %r6,%r7,150 <foo\+0x150>
+ .*: ec 67 00 00 c0 64 [ ]*cgrjle %r6,%r7,156 <foo\+0x156>
+ .*: ec 67 00 00 d0 64 [ ]*cgrjnh %r6,%r7,15c <foo\+0x15c>
+ .*: ec 6a 74 57 d6 fe [ ]*cibhe %r6,-42,1111\(%r7\)
+ .*: ec 62 74 57 d6 fe [ ]*cibh %r6,-42,1111\(%r7\)
+ .*: ec 63 74 57 d6 fe [ ]*cibnle %r6,-42,1111\(%r7\)
+ .*: ec 64 74 57 d6 fe [ ]*cibl %r6,-42,1111\(%r7\)
+ .*: ec 65 74 57 d6 fe [ ]*cibnhe %r6,-42,1111\(%r7\)
+ .*: ec 66 74 57 d6 fe [ ]*ciblh %r6,-42,1111\(%r7\)
+ .*: ec 67 74 57 d6 fe [ ]*cibne %r6,-42,1111\(%r7\)
+ .*: ec 68 74 57 d6 fe [ ]*cibe %r6,-42,1111\(%r7\)
+ .*: ec 69 74 57 d6 fe [ ]*cibnlh %r6,-42,1111\(%r7\)
+ .*: ec 6a 74 57 d6 fe [ ]*cibhe %r6,-42,1111\(%r7\)
+ .*: ec 6b 74 57 d6 fe [ ]*cibnl %r6,-42,1111\(%r7\)
+ .*: ec 6c 74 57 d6 fe [ ]*cible %r6,-42,1111\(%r7\)
+ .*: ec 6d 74 57 d6 fe [ ]*cibnh %r6,-42,1111\(%r7\)
+ .*: ec 6a 74 57 d6 fc [ ]*cgibhe %r6,-42,1111\(%r7\)
+ .*: ec 62 74 57 d6 fc [ ]*cgibh %r6,-42,1111\(%r7\)
+ .*: ec 63 74 57 d6 fc [ ]*cgibnle %r6,-42,1111\(%r7\)
+ .*: ec 64 74 57 d6 fc [ ]*cgibl %r6,-42,1111\(%r7\)
+ .*: ec 65 74 57 d6 fc [ ]*cgibnhe %r6,-42,1111\(%r7\)
+ .*: ec 66 74 57 d6 fc [ ]*cgiblh %r6,-42,1111\(%r7\)
+ .*: ec 67 74 57 d6 fc [ ]*cgibne %r6,-42,1111\(%r7\)
+ .*: ec 68 74 57 d6 fc [ ]*cgibe %r6,-42,1111\(%r7\)
+ .*: ec 69 74 57 d6 fc [ ]*cgibnlh %r6,-42,1111\(%r7\)
+ .*: ec 6a 74 57 d6 fc [ ]*cgibhe %r6,-42,1111\(%r7\)
+ .*: ec 6b 74 57 d6 fc [ ]*cgibnl %r6,-42,1111\(%r7\)
+ .*: ec 6c 74 57 d6 fc [ ]*cgible %r6,-42,1111\(%r7\)
+ .*: ec 6d 74 57 d6 fc [ ]*cgibnh %r6,-42,1111\(%r7\)
+ .*: ec 6a 00 00 d6 7e [ ]*cij %r6,-42,10,1fe <foo\+0x1fe>
+ .*: ec 62 00 00 d6 7e [ ]*cij %r6,-42,2,204 <foo\+0x204>
+ .*: ec 63 00 00 d6 7e [ ]*cij %r6,-42,3,20a <foo\+0x20a>
+ .*: ec 64 00 00 d6 7e [ ]*cij %r6,-42,4,210 <foo\+0x210>
+ .*: ec 65 00 00 d6 7e [ ]*cij %r6,-42,5,216 <foo\+0x216>
+ .*: ec 66 00 00 d6 7e [ ]*cij %r6,-42,6,21c <foo\+0x21c>
+ .*: ec 67 00 00 d6 7e [ ]*cij %r6,-42,7,222 <foo\+0x222>
+ .*: ec 68 00 00 d6 7e [ ]*cij %r6,-42,8,228 <foo\+0x228>
+ .*: ec 69 00 00 d6 7e [ ]*cij %r6,-42,9,22e <foo\+0x22e>
+ .*: ec 6a 00 00 d6 7e [ ]*cij %r6,-42,10,234 <foo\+0x234>
+ .*: ec 6b 00 00 d6 7e [ ]*cij %r6,-42,11,23a <foo\+0x23a>
+ .*: ec 6c 00 00 d6 7e [ ]*cij %r6,-42,12,240 <foo\+0x240>
+ .*: ec 6d 00 00 d6 7e [ ]*cij %r6,-42,13,246 <foo\+0x246>
+ .*: ec 6a 00 00 d6 7c [ ]*cgij %r6,-42,10,24c <foo\+0x24c>
+ .*: ec 62 00 00 d6 7c [ ]*cgij %r6,-42,2,252 <foo\+0x252>
+ .*: ec 63 00 00 d6 7c [ ]*cgij %r6,-42,3,258 <foo\+0x258>
+ .*: ec 64 00 00 d6 7c [ ]*cgij %r6,-42,4,25e <foo\+0x25e>
+ .*: ec 65 00 00 d6 7c [ ]*cgij %r6,-42,5,264 <foo\+0x264>
+ .*: ec 66 00 00 d6 7c [ ]*cgij %r6,-42,6,26a <foo\+0x26a>
+ .*: ec 67 00 00 d6 7c [ ]*cgij %r6,-42,7,270 <foo\+0x270>
+ .*: ec 68 00 00 d6 7c [ ]*cgij %r6,-42,8,276 <foo\+0x276>
+ .*: ec 69 00 00 d6 7c [ ]*cgij %r6,-42,9,27c <foo\+0x27c>
+ .*: ec 6a 00 00 d6 7c [ ]*cgij %r6,-42,10,282 <foo\+0x282>
+ .*: ec 6b 00 00 d6 7c [ ]*cgij %r6,-42,11,288 <foo\+0x288>
+ .*: ec 6c 00 00 d6 7c [ ]*cgij %r6,-42,12,28e <foo\+0x28e>
+ .*: ec 6d 00 00 d6 7c [ ]*cgij %r6,-42,13,294 <foo\+0x294>
+ .*: b9 72 a0 67 [ ]*crthe %r6,%r7
+ .*: b9 72 20 67 [ ]*crth %r6,%r7
+ .*: b9 72 30 67 [ ]*crtnle %r6,%r7
+ .*: b9 72 40 67 [ ]*crtl %r6,%r7
+ .*: b9 72 50 67 [ ]*crtnhe %r6,%r7
+ .*: b9 72 60 67 [ ]*crtlh %r6,%r7
+ .*: b9 72 70 67 [ ]*crtne %r6,%r7
+ .*: b9 72 80 67 [ ]*crte %r6,%r7
+ .*: b9 72 90 67 [ ]*crtnlh %r6,%r7
+ .*: b9 72 a0 67 [ ]*crthe %r6,%r7
+ .*: b9 72 b0 67 [ ]*crtnl %r6,%r7
+ .*: b9 72 c0 67 [ ]*crtle %r6,%r7
+ .*: b9 72 d0 67 [ ]*crtnh %r6,%r7
+ .*: b9 60 a0 67 [ ]*cgrthe %r6,%r7
+ .*: b9 60 20 67 [ ]*cgrth %r6,%r7
+ .*: b9 60 30 67 [ ]*cgrtnle %r6,%r7
+ .*: b9 60 40 67 [ ]*cgrtl %r6,%r7
+ .*: b9 60 50 67 [ ]*cgrtnhe %r6,%r7
+ .*: b9 60 60 67 [ ]*cgrtlh %r6,%r7
+ .*: b9 60 70 67 [ ]*cgrtne %r6,%r7
+ .*: b9 60 80 67 [ ]*cgrte %r6,%r7
+ .*: b9 60 90 67 [ ]*cgrtnlh %r6,%r7
+ .*: b9 60 a0 67 [ ]*cgrthe %r6,%r7
+ .*: b9 60 b0 67 [ ]*cgrtnl %r6,%r7
+ .*: b9 60 c0 67 [ ]*cgrtle %r6,%r7
+ .*: b9 60 d0 67 [ ]*cgrtnh %r6,%r7
+ .*: ec 60 8a d0 a0 72 [ ]*cithe %r6,-30000
+ .*: ec 60 8a d0 20 72 [ ]*cith %r6,-30000
+ .*: ec 60 8a d0 30 72 [ ]*citnle %r6,-30000
+ .*: ec 60 8a d0 40 72 [ ]*citl %r6,-30000
+ .*: ec 60 8a d0 50 72 [ ]*citnhe %r6,-30000
+ .*: ec 60 8a d0 60 72 [ ]*citlh %r6,-30000
+ .*: ec 60 8a d0 70 72 [ ]*citne %r6,-30000
+ .*: ec 60 8a d0 80 72 [ ]*cite %r6,-30000
+ .*: ec 60 8a d0 90 72 [ ]*citnlh %r6,-30000
+ .*: ec 60 8a d0 a0 72 [ ]*cithe %r6,-30000
+ .*: ec 60 8a d0 b0 72 [ ]*citnl %r6,-30000
+ .*: ec 60 8a d0 c0 72 [ ]*citle %r6,-30000
+ .*: ec 60 8a d0 d0 72 [ ]*citnh %r6,-30000
+ .*: ec 60 8a d0 a0 70 [ ]*cgithe %r6,-30000
+ .*: ec 60 8a d0 20 70 [ ]*cgith %r6,-30000
+ .*: ec 60 8a d0 30 70 [ ]*cgitnle %r6,-30000
+ .*: ec 60 8a d0 40 70 [ ]*cgitl %r6,-30000
+ .*: ec 60 8a d0 50 70 [ ]*cgitnhe %r6,-30000
+ .*: ec 60 8a d0 60 70 [ ]*cgitlh %r6,-30000
+ .*: ec 60 8a d0 70 70 [ ]*cgitne %r6,-30000
+ .*: ec 60 8a d0 80 70 [ ]*cgite %r6,-30000
+ .*: ec 60 8a d0 90 70 [ ]*cgitnlh %r6,-30000
+ .*: ec 60 8a d0 a0 70 [ ]*cgithe %r6,-30000
+ .*: ec 60 8a d0 b0 70 [ ]*cgitnl %r6,-30000
+ .*: ec 60 8a d0 c0 70 [ ]*cgitle %r6,-30000
+ .*: ec 60 8a d0 d0 70 [ ]*cgitnh %r6,-30000
+ .*: e3 67 85 b3 01 34 [ ]*cgh %r6,5555\(%r7,%r8\)
+ .*: e5 54 64 57 8a d0 [ ]*chhsi 1111\(%r6\),-30000
+ .*: e5 5c 64 57 8a d0 [ ]*chsi 1111\(%r6\),-30000
+ .*: e5 58 64 57 8a d0 [ ]*cghsi 1111\(%r6\),-30000
+ .*: c6 65 00 00 00 00 [ ]*chrl %r6,3b6 <foo\+0x3b6>
+ .*: c6 64 00 00 00 00 [ ]*cghrl %r6,3bc <foo\+0x3bc>
+ .*: e5 55 64 57 9c 40 [ ]*clhhsi 1111\(%r6\),40000
+ .*: e5 5d 64 57 9c 40 [ ]*clfhsi 1111\(%r6\),40000
+ .*: e5 59 64 57 9c 40 [ ]*clghsi 1111\(%r6\),40000
+ .*: c6 6f 00 00 00 00 [ ]*clrl %r6,3d4 <foo\+0x3d4>
+ .*: c6 6a 00 00 00 00 [ ]*clgrl %r6,3da <foo\+0x3da>
+ .*: c6 6e 00 00 00 00 [ ]*clgfrl %r6,3e0 <foo\+0x3e0>
+ .*: c6 67 00 00 00 00 [ ]*clhrl %r6,3e6 <foo\+0x3e6>
+ .*: c6 66 00 00 00 00 [ ]*clghrl %r6,3ec <foo\+0x3ec>
+ .*: ec 67 84 57 a0 f7 [ ]*clrbhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 20 f7 [ ]*clrbh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 30 f7 [ ]*clrbnle %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 40 f7 [ ]*clrbl %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 50 f7 [ ]*clrbnhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 60 f7 [ ]*clrblh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 70 f7 [ ]*clrbne %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 80 f7 [ ]*clrbe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 90 f7 [ ]*clrbnlh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 a0 f7 [ ]*clrbhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 b0 f7 [ ]*clrbnl %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 c0 f7 [ ]*clrble %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 d0 f7 [ ]*clrbnh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 a0 e5 [ ]*clgrbhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 20 e5 [ ]*clgrbh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 30 e5 [ ]*clgrbnle %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 40 e5 [ ]*clgrbl %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 50 e5 [ ]*clgrbnhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 60 e5 [ ]*clgrblh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 70 e5 [ ]*clgrbne %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 80 e5 [ ]*clgrbe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 90 e5 [ ]*clgrbnlh %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 a0 e5 [ ]*clgrbhe %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 b0 e5 [ ]*clgrbnl %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 c0 e5 [ ]*clgrble %r6,%r7,1111\(%r8\)
+ .*: ec 67 84 57 d0 e5 [ ]*clgrbnh %r6,%r7,1111\(%r8\)
+ .*: ec 67 00 00 a0 77 [ ]*clrj %r6,%r7,10,48e <foo\+0x48e>
+ .*: ec 67 00 00 20 77 [ ]*clrj %r6,%r7,2,494 <foo\+0x494>
+ .*: ec 67 00 00 30 77 [ ]*clrj %r6,%r7,3,49a <foo\+0x49a>
+ .*: ec 67 00 00 40 77 [ ]*clrj %r6,%r7,4,4a0 <foo\+0x4a0>
+ .*: ec 67 00 00 50 77 [ ]*clrj %r6,%r7,5,4a6 <foo\+0x4a6>
+ .*: ec 67 00 00 60 77 [ ]*clrj %r6,%r7,6,4ac <foo\+0x4ac>
+ .*: ec 67 00 00 70 77 [ ]*clrj %r6,%r7,7,4b2 <foo\+0x4b2>
+ .*: ec 67 00 00 80 77 [ ]*clrj %r6,%r7,8,4b8 <foo\+0x4b8>
+ .*: ec 67 00 00 90 77 [ ]*clrj %r6,%r7,9,4be <foo\+0x4be>
+ .*: ec 67 00 00 a0 77 [ ]*clrj %r6,%r7,10,4c4 <foo\+0x4c4>
+ .*: ec 67 00 00 b0 77 [ ]*clrj %r6,%r7,11,4ca <foo\+0x4ca>
+ .*: ec 67 00 00 c0 77 [ ]*clrj %r6,%r7,12,4d0 <foo\+0x4d0>
+ .*: ec 67 00 00 d0 77 [ ]*clrj %r6,%r7,13,4d6 <foo\+0x4d6>
+ .*: ec 67 00 00 a0 65 [ ]*clgrj %r6,%r7,10,4dc <foo\+0x4dc>
+ .*: ec 67 00 00 20 65 [ ]*clgrj %r6,%r7,2,4e2 <foo\+0x4e2>
+ .*: ec 67 00 00 30 65 [ ]*clgrj %r6,%r7,3,4e8 <foo\+0x4e8>
+ .*: ec 67 00 00 40 65 [ ]*clgrj %r6,%r7,4,4ee <foo\+0x4ee>
+ .*: ec 67 00 00 50 65 [ ]*clgrj %r6,%r7,5,4f4 <foo\+0x4f4>
+ .*: ec 67 00 00 60 65 [ ]*clgrj %r6,%r7,6,4fa <foo\+0x4fa>
+ .*: ec 67 00 00 70 65 [ ]*clgrj %r6,%r7,7,500 <foo\+0x500>
+ .*: ec 67 00 00 80 65 [ ]*clgrj %r6,%r7,8,506 <foo\+0x506>
+ .*: ec 67 00 00 90 65 [ ]*clgrj %r6,%r7,9,50c <foo\+0x50c>
+ .*: ec 67 00 00 a0 65 [ ]*clgrj %r6,%r7,10,512 <foo\+0x512>
+ .*: ec 67 00 00 b0 65 [ ]*clgrj %r6,%r7,11,518 <foo\+0x518>
+ .*: ec 67 00 00 c0 65 [ ]*clgrj %r6,%r7,12,51e <foo\+0x51e>
+ .*: ec 67 00 00 d0 65 [ ]*clgrj %r6,%r7,13,524 <foo\+0x524>
+ .*: ec 6a 74 57 c8 ff [ ]*clibhe %r6,200,1111\(%r7\)
+ .*: ec 62 74 57 c8 ff [ ]*clibh %r6,200,1111\(%r7\)
+ .*: ec 63 74 57 c8 ff [ ]*clibnle %r6,200,1111\(%r7\)
+ .*: ec 64 74 57 c8 ff [ ]*clibl %r6,200,1111\(%r7\)
+ .*: ec 65 74 57 c8 ff [ ]*clibnhe %r6,200,1111\(%r7\)
+ .*: ec 66 74 57 c8 ff [ ]*cliblh %r6,200,1111\(%r7\)
+ .*: ec 67 74 57 c8 ff [ ]*clibne %r6,200,1111\(%r7\)
+ .*: ec 68 74 57 c8 ff [ ]*clibe %r6,200,1111\(%r7\)
+ .*: ec 69 74 57 c8 ff [ ]*clibnlh %r6,200,1111\(%r7\)
+ .*: ec 6a 74 57 c8 ff [ ]*clibhe %r6,200,1111\(%r7\)
+ .*: ec 6b 74 57 c8 ff [ ]*clibnl %r6,200,1111\(%r7\)
+ .*: ec 6c 74 57 c8 ff [ ]*clible %r6,200,1111\(%r7\)
+ .*: ec 6d 74 57 c8 ff [ ]*clibnh %r6,200,1111\(%r7\)
+ .*: ec 6a 74 57 c8 fd [ ]*clgibhe %r6,200,1111\(%r7\)
+ .*: ec 62 74 57 c8 fd [ ]*clgibh %r6,200,1111\(%r7\)
+ .*: ec 63 74 57 c8 fd [ ]*clgibnle %r6,200,1111\(%r7\)
+ .*: ec 64 74 57 c8 fd [ ]*clgibl %r6,200,1111\(%r7\)
+ .*: ec 65 74 57 c8 fd [ ]*clgibnhe %r6,200,1111\(%r7\)
+ .*: ec 66 74 57 c8 fd [ ]*clgiblh %r6,200,1111\(%r7\)
+ .*: ec 67 74 57 c8 fd [ ]*clgibne %r6,200,1111\(%r7\)
+ .*: ec 68 74 57 c8 fd [ ]*clgibe %r6,200,1111\(%r7\)
+ .*: ec 69 74 57 c8 fd [ ]*clgibnlh %r6,200,1111\(%r7\)
+ .*: ec 6a 74 57 c8 fd [ ]*clgibhe %r6,200,1111\(%r7\)
+ .*: ec 6b 74 57 c8 fd [ ]*clgibnl %r6,200,1111\(%r7\)
+ .*: ec 6c 74 57 c8 fd [ ]*clgible %r6,200,1111\(%r7\)
+ .*: ec 6d 74 57 c8 fd [ ]*clgibnh %r6,200,1111\(%r7\)
+ .*: ec 6a 00 00 c8 7f [ ]*clij %r6,200,10,5c6 <foo\+0x5c6>
+ .*: ec 62 00 00 c8 7f [ ]*clij %r6,200,2,5cc <foo\+0x5cc>
+ .*: ec 63 00 00 c8 7f [ ]*clij %r6,200,3,5d2 <foo\+0x5d2>
+ .*: ec 64 00 00 c8 7f [ ]*clij %r6,200,4,5d8 <foo\+0x5d8>
+ .*: ec 65 00 00 c8 7f [ ]*clij %r6,200,5,5de <foo\+0x5de>
+ .*: ec 66 00 00 c8 7f [ ]*clij %r6,200,6,5e4 <foo\+0x5e4>
+ .*: ec 67 00 00 c8 7f [ ]*clij %r6,200,7,5ea <foo\+0x5ea>
+ .*: ec 68 00 00 c8 7f [ ]*clij %r6,200,8,5f0 <foo\+0x5f0>
+ .*: ec 69 00 00 c8 7f [ ]*clij %r6,200,9,5f6 <foo\+0x5f6>
+ .*: ec 6a 00 00 c8 7f [ ]*clij %r6,200,10,5fc <foo\+0x5fc>
+ .*: ec 6b 00 00 c8 7f [ ]*clij %r6,200,11,602 <foo\+0x602>
+ .*: ec 6c 00 00 c8 7f [ ]*clij %r6,200,12,608 <foo\+0x608>
+ .*: ec 6d 00 00 c8 7f [ ]*clij %r6,200,13,60e <foo\+0x60e>
+ .*: ec 6a 00 00 c8 7d [ ]*clgij %r6,200,10,614 <foo\+0x614>
+ .*: ec 62 00 00 c8 7d [ ]*clgij %r6,200,2,61a <foo\+0x61a>
+ .*: ec 63 00 00 c8 7d [ ]*clgij %r6,200,3,620 <foo\+0x620>
+ .*: ec 64 00 00 c8 7d [ ]*clgij %r6,200,4,626 <foo\+0x626>
+ .*: ec 65 00 00 c8 7d [ ]*clgij %r6,200,5,62c <foo\+0x62c>
+ .*: ec 66 00 00 c8 7d [ ]*clgij %r6,200,6,632 <foo\+0x632>
+ .*: ec 67 00 00 c8 7d [ ]*clgij %r6,200,7,638 <foo\+0x638>
+ .*: ec 68 00 00 c8 7d [ ]*clgij %r6,200,8,63e <foo\+0x63e>
+ .*: ec 69 00 00 c8 7d [ ]*clgij %r6,200,9,644 <foo\+0x644>
+ .*: ec 6a 00 00 c8 7d [ ]*clgij %r6,200,10,64a <foo\+0x64a>
+ .*: ec 6b 00 00 c8 7d [ ]*clgij %r6,200,11,650 <foo\+0x650>
+ .*: ec 6c 00 00 c8 7d [ ]*clgij %r6,200,12,656 <foo\+0x656>
+ .*: ec 6d 00 00 c8 7d [ ]*clgij %r6,200,13,65c <foo\+0x65c>
+ .*: b9 73 a0 67 [ ]*clrthe %r6,%r7
+ .*: b9 73 20 67 [ ]*clrth %r6,%r7
+ .*: b9 73 30 67 [ ]*clrtnle %r6,%r7
+ .*: b9 73 40 67 [ ]*clrtl %r6,%r7
+ .*: b9 73 50 67 [ ]*clrtnhe %r6,%r7
+ .*: b9 73 60 67 [ ]*clrtlh %r6,%r7
+ .*: b9 73 70 67 [ ]*clrtne %r6,%r7
+ .*: b9 73 80 67 [ ]*clrte %r6,%r7
+ .*: b9 73 90 67 [ ]*clrtnlh %r6,%r7
+ .*: b9 73 a0 67 [ ]*clrthe %r6,%r7
+ .*: b9 73 b0 67 [ ]*clrtnl %r6,%r7
+ .*: b9 73 c0 67 [ ]*clrtle %r6,%r7
+ .*: b9 73 d0 67 [ ]*clrtnh %r6,%r7
+ .*: b9 61 a0 67 [ ]*clgrthe %r6,%r7
+ .*: b9 61 20 67 [ ]*clgrth %r6,%r7
+ .*: b9 61 30 67 [ ]*clgrtnle %r6,%r7
+ .*: b9 61 40 67 [ ]*clgrtl %r6,%r7
+ .*: b9 61 50 67 [ ]*clgrtnhe %r6,%r7
+ .*: b9 61 60 67 [ ]*clgrtlh %r6,%r7
+ .*: b9 61 70 67 [ ]*clgrtne %r6,%r7
+ .*: b9 61 80 67 [ ]*clgrte %r6,%r7
+ .*: b9 61 90 67 [ ]*clgrtnlh %r6,%r7
+ .*: b9 61 a0 67 [ ]*clgrthe %r6,%r7
+ .*: b9 61 b0 67 [ ]*clgrtnl %r6,%r7
+ .*: b9 61 c0 67 [ ]*clgrtle %r6,%r7
+ .*: b9 61 d0 67 [ ]*clgrtnh %r6,%r7
+ .*: ec 60 75 30 a0 73 [ ]*clfithe %r6,30000
+ .*: ec 60 75 30 20 73 [ ]*clfith %r6,30000
+ .*: ec 60 75 30 30 73 [ ]*clfitnle %r6,30000
+ .*: ec 60 75 30 40 73 [ ]*clfitl %r6,30000
+ .*: ec 60 75 30 50 73 [ ]*clfitnhe %r6,30000
+ .*: ec 60 75 30 60 73 [ ]*clfitlh %r6,30000
+ .*: ec 60 75 30 70 73 [ ]*clfitne %r6,30000
+ .*: ec 60 75 30 80 73 [ ]*clfite %r6,30000
+ .*: ec 60 75 30 90 73 [ ]*clfitnlh %r6,30000
+ .*: ec 60 75 30 a0 73 [ ]*clfithe %r6,30000
+ .*: ec 60 75 30 b0 73 [ ]*clfitnl %r6,30000
+ .*: ec 60 75 30 c0 73 [ ]*clfitle %r6,30000
+ .*: ec 60 75 30 d0 73 [ ]*clfitnh %r6,30000
+ .*: ec 60 75 30 a0 71 [ ]*clgithe %r6,30000
+ .*: ec 60 75 30 20 71 [ ]*clgith %r6,30000
+ .*: ec 60 75 30 30 71 [ ]*clgitnle %r6,30000
+ .*: ec 60 75 30 40 71 [ ]*clgitl %r6,30000
+ .*: ec 60 75 30 50 71 [ ]*clgitnhe %r6,30000
+ .*: ec 60 75 30 60 71 [ ]*clgitlh %r6,30000
+ .*: ec 60 75 30 70 71 [ ]*clgitne %r6,30000
+ .*: ec 60 75 30 80 71 [ ]*clgite %r6,30000
+ .*: ec 60 75 30 90 71 [ ]*clgitnlh %r6,30000
+ .*: ec 60 75 30 a0 71 [ ]*clgithe %r6,30000
+ .*: ec 60 75 30 b0 71 [ ]*clgitnl %r6,30000
+ .*: ec 60 75 30 c0 71 [ ]*clgitle %r6,30000
+ .*: ec 60 75 30 d0 71 [ ]*clgitnh %r6,30000
+ .*: eb 67 84 57 00 4c [ ]*ecag %r6,%r7,1111\(%r8\)
+ .*: c4 6d 00 00 00 00 [ ]*lrl %r6,76c <foo\+0x76c>
+ .*: c4 68 00 00 00 00 [ ]*lgrl %r6,772 <foo\+0x772>
+ .*: c4 6c 00 00 00 00 [ ]*lgfrl %r6,778 <foo\+0x778>
+ .*: e3 67 85 b3 01 75 [ ]*laey %r6,5555\(%r7,%r8\)
+ .*: e3 67 85 b3 01 32 [ ]*ltgf %r6,5555\(%r7,%r8\)
+ .*: c4 65 00 00 00 00 [ ]*lhrl %r6,78a <foo\+0x78a>
+ .*: c4 64 00 00 00 00 [ ]*lghrl %r6,790 <foo\+0x790>
+ .*: c4 6e 00 00 00 00 [ ]*llgfrl %r6,796 <foo\+0x796>
+ .*: c4 62 00 00 00 00 [ ]*llhrl %r6,79c <foo\+0x79c>
+ .*: c4 66 00 00 00 00 [ ]*llghrl %r6,7a2 <foo\+0x7a2>
+ .*: e5 44 64 57 8a d0 [ ]*mvhhi 1111\(%r6\),-30000
+ .*: e5 4c 64 57 8a d0 [ ]*mvhi 1111\(%r6\),-30000
+ .*: e5 48 64 57 8a d0 [ ]*mvghi 1111\(%r6\),-30000
+ .*: e3 67 85 b3 01 5c [ ]*mfy %r6,5555\(%r7,%r8\)
+ .*: e3 67 85 b3 01 7c [ ]*mhy %r6,5555\(%r7,%r8\)
+ .*: c2 61 ff fe 79 60 [ ]*msfi %r6,-100000
+ .*: c2 60 ff fe 79 60 [ ]*msgfi %r6,-100000
+ .*: e3 a6 75 b3 01 36 [ ]*pfd 10,5555\(%r6,%r7\)
+ .*: c6 a2 00 00 00 00 [ ]*pfdrl 10,7d8 <foo\+0x7d8>
+ .*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
+ .*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
+ .*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
+ .*: ec 67 d2 dc e6 55 [ ]*risbg %r6,%r7,210,220,230
+ .*: c4 6f 00 00 00 00 [ ]*strl %r6,7f6 <foo\+0x7f6>
+ .*: c4 6b 00 00 00 00 [ ]*stgrl %r6,7fc <foo\+0x7fc>
+ .*: c4 67 00 00 00 00 [ ]*sthrl %r6,802 <foo\+0x802>
+ .*: c6 60 00 00 00 00 [ ]*exrl %r6,808 <foo\+0x808>
+ .*: af ee 6d 05 [ ]*mc 3333\(%r6\),238
+ .*: b9 a2 00 60 [ ]*ptf %r6
+ .*: b9 af 00 67 [ ]*pfmf %r6,%r7
+ .*: b9 bf a0 67 [ ]*trte %r6,%r7,10
+ .*: b9 bf 00 67 [ ]*trte %r6,%r7,0
+ .*: b9 bd a0 67 [ ]*trtre %r6,%r7,10
+ .*: b9 bd 00 67 [ ]*trtre %r6,%r7,0
+ .*: 07 07 [ ]*bcr 0,%r7
\ No newline at end of file
Index: gas/testsuite/gas/s390/zarch-z10.s
===================================================================
*** /dev/null 1970-01-01 00:00:00.000000000 +0000
--- gas/testsuite/gas/s390/zarch-z10.s 2008-03-18 18:58:10.000000000 +0100
***************
*** 0 ****
--- 1,370 ----
+ .text
+ foo:
+ asi 5555(%r6),-42
+ agsi 5555(%r6),-42
+ alsi 5555(%r6),-42
+ algsi 5555(%r6),-42
+ crl %r6,.
+ cgrl %r6,.
+ cgfrl %r6,.
+ crb %r6,%r7,10,1111(%r8)
+ crbh %r6,%r7,1111(%r8)
+ crbnle %r6,%r7,1111(%r8)
+ crbl %r6,%r7,1111(%r8)
+ crbnhe %r6,%r7,1111(%r8)
+ crblh %r6,%r7,1111(%r8)
+ crbne %r6,%r7,1111(%r8)
+ crbe %r6,%r7,1111(%r8)
+ crbnlh %r6,%r7,1111(%r8)
+ crbhe %r6,%r7,1111(%r8)
+ crbnl %r6,%r7,1111(%r8)
+ crble %r6,%r7,1111(%r8)
+ crbnh %r6,%r7,1111(%r8)
+ cgrb %r6,%r7,10,1111(%r8)
+ cgrbh %r6,%r7,1111(%r8)
+ cgrbnle %r6,%r7,1111(%r8)
+ cgrbl %r6,%r7,1111(%r8)
+ cgrbnhe %r6,%r7,1111(%r8)
+ cgrblh %r6,%r7,1111(%r8)
+ cgrbne %r6,%r7,1111(%r8)
+ cgrbe %r6,%r7,1111(%r8)
+ cgrbnlh %r6,%r7,1111(%r8)
+ cgrbhe %r6,%r7,1111(%r8)
+ cgrbnl %r6,%r7,1111(%r8)
+ cgrble %r6,%r7,1111(%r8)
+ cgrbnh %r6,%r7,1111(%r8)
+ crj %r6,%r7,10,.
+ crjh %r6,%r7,.
+ crjnle %r6,%r7,.
+ crjl %r6,%r7,.
+ crjnhe %r6,%r7,.
+ crjlh %r6,%r7,.
+ crjne %r6,%r7,.
+ crje %r6,%r7,.
+ crjnlh %r6,%r7,.
+ crjhe %r6,%r7,.
+ crjnl %r6,%r7,.
+ crjle %r6,%r7,.
+ crjnh %r6,%r7,.
+ cgrj %r6,%r7,10,.
+ cgrjh %r6,%r7,.
+ cgrjnle %r6,%r7,.
+ cgrjl %r6,%r7,.
+ cgrjnhe %r6,%r7,.
+ cgrjlh %r6,%r7,.
+ cgrjne %r6,%r7,.
+ cgrje %r6,%r7,.
+ cgrjnlh %r6,%r7,.
+ cgrjhe %r6,%r7,.
+ cgrjnl %r6,%r7,.
+ cgrjle %r6,%r7,.
+ cgrjnh %r6,%r7,.
+ cib %r6,-42,10,1111(%r7)
+ cibh %r6,-42,1111(%r7)
+ cibnle %r6,-42,1111(%r7)
+ cibl %r6,-42,1111(%r7)
+ cibnhe %r6,-42,1111(%r7)
+ ciblh %r6,-42,1111(%r7)
+ cibne %r6,-42,1111(%r7)
+ cibe %r6,-42,1111(%r7)
+ cibnlh %r6,-42,1111(%r7)
+ cibhe %r6,-42,1111(%r7)
+ cibnl %r6,-42,1111(%r7)
+ cible %r6,-42,1111(%r7)
+ cibnh %r6,-42,1111(%r7)
+ cgib %r6,-42,10,1111(%r7)
+ cgibh %r6,-42,1111(%r7)
+ cgibnle %r6,-42,1111(%r7)
+ cgibl %r6,-42,1111(%r7)
+ cgibnhe %r6,-42,1111(%r7)
+ cgiblh %r6,-42,1111(%r7)
+ cgibne %r6,-42,1111(%r7)
+ cgibe %r6,-42,1111(%r7)
+ cgibnlh %r6,-42,1111(%r7)
+ cgibhe %r6,-42,1111(%r7)
+ cgibnl %r6,-42,1111(%r7)
+ cgible %r6,-42,1111(%r7)
+ cgibnh %r6,-42,1111(%r7)
+ cij %r6,-42,10,.
+ cijh %r6,-42,.
+ cijnle %r6,-42,.
+ cijl %r6,-42,.
+ cijnhe %r6,-42,.
+ cijlh %r6,-42,.
+ cijne %r6,-42,.
+ cije %r6,-42,.
+ cijnlh %r6,-42,.
+ cijhe %r6,-42,.
+ cijnl %r6,-42,.
+ cijle %r6,-42,.
+ cijnh %r6,-42,.
+ cgij %r6,-42,10,.
+ cgijh %r6,-42,.
+ cgijnle %r6,-42,.
+ cgijl %r6,-42,.
+ cgijnhe %r6,-42,.
+ cgijlh %r6,-42,.
+ cgijne %r6,-42,.
+ cgije %r6,-42,.
+ cgijnlh %r6,-42,.
+ cgijhe %r6,-42,.
+ cgijnl %r6,-42,.
+ cgijle %r6,-42,.
+ cgijnh %r6,-42,.
+ crt %r6,%r7,10
+ crth %r6,%r7
+ crtnle %r6,%r7
+ crtl %r6,%r7
+ crtnhe %r6,%r7
+ crtlh %r6,%r7
+ crtne %r6,%r7
+ crte %r6,%r7
+ crtnlh %r6,%r7
+ crthe %r6,%r7
+ crtnl %r6,%r7
+ crtle %r6,%r7
+ crtnh %r6,%r7
+ cgrt %r6,%r7,10
+ cgrth %r6,%r7
+ cgrtnle %r6,%r7
+ cgrtl %r6,%r7
+ cgrtnhe %r6,%r7
+ cgrtlh %r6,%r7
+ cgrtne %r6,%r7
+ cgrte %r6,%r7
+ cgrtnlh %r6,%r7
+ cgrthe %r6,%r7
+ cgrtnl %r6,%r7
+ cgrtle %r6,%r7
+ cgrtnh %r6,%r7
+ cit %r6,-30000,10
+ cith %r6,-30000
+ citnle %r6,-30000
+ citl %r6,-30000
+ citnhe %r6,-30000
+ citlh %r6,-30000
+ citne %r6,-30000
+ cite %r6,-30000
+ citnlh %r6,-30000
+ cithe %r6,-30000
+ citnl %r6,-30000
+ citle %r6,-30000
+ citnh %r6,-30000
+ cgit %r6,-30000,10
+ cgith %r6,-30000
+ cgitnle %r6,-30000
+ cgitl %r6,-30000
+ cgitnhe %r6,-30000
+ cgitlh %r6,-30000
+ cgitne %r6,-30000
+ cgite %r6,-30000
+ cgitnlh %r6,-30000
+ cgithe %r6,-30000
+ cgitnl %r6,-30000
+ cgitle %r6,-30000
+ cgitnh %r6,-30000
+ cgh %r6,5555(%r7,%r8)
+ chhsi 1111(%r6),-30000
+ chsi 1111(%r6),-30000
+ cghsi 1111(%r6),-30000
+ chrl %r6,.
+ cghrl %r6,.
+ clhhsi 1111(%r6),40000
+ clfhsi 1111(%r6),40000
+ clghsi 1111(%r6),40000
+ clrl %r6,.
+ clgrl %r6,.
+ clgfrl %r6,.
+ clhrl %r6,.
+ clghrl %r6,.
+ clrb %r6,%r7,10,1111(%r8)
+ clrbh %r6,%r7,1111(%r8)
+ clrbnle %r6,%r7,1111(%r8)
+ clrbl %r6,%r7,1111(%r8)
+ clrbnhe %r6,%r7,1111(%r8)
+ clrblh %r6,%r7,1111(%r8)
+ clrbne %r6,%r7,1111(%r8)
+ clrbe %r6,%r7,1111(%r8)
+ clrbnlh %r6,%r7,1111(%r8)
+ clrbhe %r6,%r7,1111(%r8)
+ clrbnl %r6,%r7,1111(%r8)
+ clrble %r6,%r7,1111(%r8)
+ clrbnh %r6,%r7,1111(%r8)
+ clgrb %r6,%r7,10,1111(%r8)
+ clgrbh %r6,%r7,1111(%r8)
+ clgrbnle %r6,%r7,1111(%r8)
+ clgrbl %r6,%r7,1111(%r8)
+ clgrbnhe %r6,%r7,1111(%r8)
+ clgrblh %r6,%r7,1111(%r8)
+ clgrbne %r6,%r7,1111(%r8)
+ clgrbe %r6,%r7,1111(%r8)
+ clgrbnlh %r6,%r7,1111(%r8)
+ clgrbhe %r6,%r7,1111(%r8)
+ clgrbnl %r6,%r7,1111(%r8)
+ clgrble %r6,%r7,1111(%r8)
+ clgrbnh %r6,%r7,1111(%r8)
+ clrj %r6,%r7,10,.
+ clrjh %r6,%r7,.
+ clrjnle %r6,%r7,.
+ clrjl %r6,%r7,.
+ clrjnhe %r6,%r7,.
+ clrjlh %r6,%r7,.
+ clrjne %r6,%r7,.
+ clrje %r6,%r7,.
+ clrjnlh %r6,%r7,.
+ clrjhe %r6,%r7,.
+ clrjnl %r6,%r7,.
+ clrjle %r6,%r7,.
+ clrjnh %r6,%r7,.
+ clgrj %r6,%r7,10,.
+ clgrjh %r6,%r7,.
+ clgrjnle %r6,%r7,.
+ clgrjl %r6,%r7,.
+ clgrjnhe %r6,%r7,.
+ clgrjlh %r6,%r7,.
+ clgrjne %r6,%r7,.
+ clgrje %r6,%r7,.
+ clgrjnlh %r6,%r7,.
+ clgrjhe %r6,%r7,.
+ clgrjnl %r6,%r7,.
+ clgrjle %r6,%r7,.
+ clgrjnh %r6,%r7,.
+ clib %r6,200,10,1111(%r7)
+ clibh %r6,200,1111(%r7)
+ clibnle %r6,200,1111(%r7)
+ clibl %r6,200,1111(%r7)
+ clibnhe %r6,200,1111(%r7)
+ cliblh %r6,200,1111(%r7)
+ clibne %r6,200,1111(%r7)
+ clibe %r6,200,1111(%r7)
+ clibnlh %r6,200,1111(%r7)
+ clibhe %r6,200,1111(%r7)
+ clibnl %r6,200,1111(%r7)
+ clible %r6,200,1111(%r7)
+ clibnh %r6,200,1111(%r7)
+ clgib %r6,200,10,1111(%r7)
+ clgibh %r6,200,1111(%r7)
+ clgibnle %r6,200,1111(%r7)
+ clgibl %r6,200,1111(%r7)
+ clgibnhe %r6,200,1111(%r7)
+ clgiblh %r6,200,1111(%r7)
+ clgibne %r6,200,1111(%r7)
+ clgibe %r6,200,1111(%r7)
+ clgibnlh %r6,200,1111(%r7)
+ clgibhe %r6,200,1111(%r7)
+ clgibnl %r6,200,1111(%r7)
+ clgible %r6,200,1111(%r7)
+ clgibnh %r6,200,1111(%r7)
+ clij %r6,200,10,.
+ clijh %r6,200,.
+ clijnle %r6,200,.
+ clijl %r6,200,.
+ clijnhe %r6,200,.
+ clijlh %r6,200,.
+ clijne %r6,200,.
+ clije %r6,200,.
+ clijnlh %r6,200,.
+ clijhe %r6,200,.
+ clijnl %r6,200,.
+ clijle %r6,200,.
+ clijnh %r6,200,.
+ clgij %r6,200,10,.
+ clgijh %r6,200,.
+ clgijnle %r6,200,.
+ clgijl %r6,200,.
+ clgijnhe %r6,200,.
+ clgijlh %r6,200,.
+ clgijne %r6,200,.
+ clgije %r6,200,.
+ clgijnlh %r6,200,.
+ clgijhe %r6,200,.
+ clgijnl %r6,200,.
+ clgijle %r6,200,.
+ clgijnh %r6,200,.
+ clrt %r6,%r7,10
+ clrth %r6,%r7
+ clrtnle %r6,%r7
+ clrtl %r6,%r7
+ clrtnhe %r6,%r7
+ clrtlh %r6,%r7
+ clrtne %r6,%r7
+ clrte %r6,%r7
+ clrtnlh %r6,%r7
+ clrthe %r6,%r7
+ clrtnl %r6,%r7
+ clrtle %r6,%r7
+ clrtnh %r6,%r7
+ clgrt %r6,%r7,10
+ clgrth %r6,%r7
+ clgrtnle %r6,%r7
+ clgrtl %r6,%r7
+ clgrtnhe %r6,%r7
+ clgrtlh %r6,%r7
+ clgrtne %r6,%r7
+ clgrte %r6,%r7
+ clgrtnlh %r6,%r7
+ clgrthe %r6,%r7
+ clgrtnl %r6,%r7
+ clgrtle %r6,%r7
+ clgrtnh %r6,%r7
+ clfit %r6,30000,10
+ clfith %r6,30000
+ clfitnle %r6,30000
+ clfitl %r6,30000
+ clfitnhe %r6,30000
+ clfitlh %r6,30000
+ clfitne %r6,30000
+ clfite %r6,30000
+ clfitnlh %r6,30000
+ clfithe %r6,30000
+ clfitnl %r6,30000
+ clfitle %r6,30000
+ clfitnh %r6,30000
+ clgit %r6,30000,10
+ clgith %r6,30000
+ clgitnle %r6,30000
+ clgitl %r6,30000
+ clgitnhe %r6,30000
+ clgitlh %r6,30000
+ clgitne %r6,30000
+ clgite %r6,30000
+ clgitnlh %r6,30000
+ clgithe %r6,30000
+ clgitnl %r6,30000
+ clgitle %r6,30000
+ clgitnh %r6,30000
+ ecag %r6,%r7,1111(%r8)
+ lrl %r6,.
+ lgrl %r6,.
+ lgfrl %r6,.
+ laey %r6,5555(%r7,%r8)
+ ltgf %r6,5555(%r7,%r8)
+ lhrl %r6,.
+ lghrl %r6,.
+ llgfrl %r6,.
+ llhrl %r6,.
+ llghrl %r6,.
+ mvhhi 1111(%r6),-30000
+ mvhi 1111(%r6),-30000
+ mvghi 1111(%r6),-30000
+ mfy %r6,5555(%r7,%r8)
+ mhy %r6,5555(%r7,%r8)
+ msfi %r6,-100000
+ msgfi %r6,-100000
+ pfd 10,5555(%r6,%r7)
+ pfdrl 10,.
+ rnsbg %r6,%r7,210,220,230
+ rxsbg %r6,%r7,210,220,230
+ rosbg %r6,%r7,210,220,230
+ risbg %r6,%r7,210,220,230
+ strl %r6,.
+ stgrl %r6,.
+ sthrl %r6,.
+ exrl %r6,.
+ mc 3333(%r6),238
+ ptf %r6
+ pfmf %r6,%r7
+ trte %r6,%r7,10
+ trte %r6,%r7
+ trtre %r6,%r7,10
+ trtre %r6,%r7
Index: opcodes/s390-mkopc.c
===================================================================
*** opcodes/s390-mkopc.c.orig 2008-03-18 17:57:42.000000000 +0100
--- opcodes/s390-mkopc.c 2008-03-18 18:28:03.000000000 +0100
*************** enum s390_opcode_cpu_val
*** 37,43 ****
S390_OPCODE_Z900,
S390_OPCODE_Z990,
S390_OPCODE_Z9_109,
! S390_OPCODE_Z9_EC
};
struct op_struct
--- 37,44 ----
S390_OPCODE_Z900,
S390_OPCODE_Z990,
S390_OPCODE_Z9_109,
! S390_OPCODE_Z9_EC,
! S390_OPCODE_Z10
};
struct op_struct
*************** struct s390_cond_ext_format
*** 121,202 ****
char extension[4];
};
! #define NUM_COND_EXTENSIONS 20
!
const struct s390_cond_ext_format s390_cond_extensions[NUM_COND_EXTENSIONS] =
! {
! { '1', "o" }, /* jump on overflow / if ones */
! { '2', "h" }, /* jump on A high */
! { '2', "p" }, /* jump on plus */
! { '3', "nle" }, /* jump on not low or equal */
! { '4', "l" }, /* jump on A low */
! { '4', "m" }, /* jump on minus / if mixed */
! { '5', "nhe" }, /* jump on not high or equal */
! { '6', "lh" }, /* jump on low or high */
! { '7', "ne" }, /* jump on A not equal B */
! { '7', "nz" }, /* jump on not zero / if not zeros */
! { '8', "e" }, /* jump on A equal B */
! { '8', "z" }, /* jump on zero / if zeros */
! { '9', "nlh" }, /* jump on not low or high */
! { 'a', "he" }, /* jump on high or equal */
! { 'b', "nl" }, /* jump on A not low */
! { 'b', "nm" }, /* jump on not minus / if not mixed */
! { 'c', "le" }, /* jump on low or equal */
! { 'd', "nh" }, /* jump on A not high */
! { 'd', "np" }, /* jump on not plus */
! { 'e', "no" }, /* jump on not overflow / if not ones */
! };
/* As with insertOpcode instructions are added to the sorted opcode
array. Additionally mnemonics containing the '*<number>' tag are
expanded to the set of conditional instructions described by
! s390_cond_extensions with the '*<number>' tag replaced by the
! respective mnemonic extensions. */
static void
! expandConditionalJump (char *opcode, char *mnemonic, char *format,
! int min_cpu, int mode_bits)
{
char prefix[5];
char suffix[5];
char number[5];
! int mask_start, i = 0, star_found = 0, reading_number = 0;
int number_p = 0, suffix_p = 0, prefix_p = 0;
while (mnemonic[i] != '\0')
{
! switch (mnemonic[i])
{
! case '*':
! if (star_found)
goto malformed_mnemonic;
! star_found = 1;
reading_number = 1;
- break;
-
- case '0': case '1': case '2': case '3': case '4':
- case '5': case '6': case '7': case '8': case '9':
- if (!star_found || !reading_number)
- goto malformed_mnemonic;
-
- number[number_p++] = mnemonic[i];
- break;
-
- default:
- if (reading_number)
- {
- if (!number_p)
- goto malformed_mnemonic;
- else
- reading_number = 0;
- }
-
- if (star_found)
- suffix[suffix_p++] = mnemonic[i];
- else
- prefix[prefix_p++] = mnemonic[i];
}
i++;
}
--- 122,203 ----
char extension[4];
};
! /* The mnemonic extensions for conditional branches used to replace
! the '*' tag. */
! #define NUM_COND_EXTENSIONS 12
const struct s390_cond_ext_format s390_cond_extensions[NUM_COND_EXTENSIONS] =
! { { '2', "h" }, /* jump on A high */
! { '3', "nle" }, /* jump on not low or equal */
! { '4', "l" }, /* jump on A low */
! { '5', "nhe" }, /* jump on not high or equal */
! { '6', "lh" }, /* jump on low or high */
! { '7', "ne" }, /* jump on A not equal B */
! { '8', "e" }, /* jump on A equal B */
! { '9', "nlh" }, /* jump on not low or high */
! { 'a', "he" }, /* jump on high or equal */
! { 'b', "nl" }, /* jump on A not low */
! { 'c', "le" }, /* jump on low or equal */
! { 'd', "nh" }, /* jump on A not high */
! };
/* As with insertOpcode instructions are added to the sorted opcode
array. Additionally mnemonics containing the '*<number>' tag are
expanded to the set of conditional instructions described by
! s390_cond_extensions with the tag replaced by the respective
! mnemonic extensions. */
static void
! insertExpandedMnemonic (char *opcode, char *mnemonic, char *format,
! int min_cpu, int mode_bits)
{
+ char *tag;
char prefix[5];
char suffix[5];
char number[5];
! int mask_start, i = 0, tag_found = 0, reading_number = 0;
int number_p = 0, suffix_p = 0, prefix_p = 0;
+ if (!(tag = strchr (mnemonic, '*')))
+ {
+ insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits);
+ return;
+ }
+
while (mnemonic[i] != '\0')
{
! if (mnemonic[i] == *tag)
{
! if (tag_found)
goto malformed_mnemonic;
! tag_found = 1;
reading_number = 1;
}
+ else
+ switch (mnemonic[i])
+ {
+ case '0': case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
+ if (!tag_found || !reading_number)
+ goto malformed_mnemonic;
+
+ number[number_p++] = mnemonic[i];
+ break;
+
+ default:
+ if (reading_number)
+ {
+ if (!number_p)
+ goto malformed_mnemonic;
+ else
+ reading_number = 0;
+ }
+
+ if (tag_found)
+ suffix[suffix_p++] = mnemonic[i];
+ else
+ prefix[prefix_p++] = mnemonic[i];
+ }
i++;
}
*************** expandConditionalJump (char *opcode, cha
*** 221,229 ****
char new_mnemonic[15];
strcpy (new_mnemonic, prefix);
strcat (new_mnemonic, s390_cond_extensions[i].extension);
strcat (new_mnemonic, suffix);
- opcode[mask_start] = s390_cond_extensions[i].nibble;
insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits);
}
return;
--- 222,230 ----
char new_mnemonic[15];
strcpy (new_mnemonic, prefix);
+ opcode[mask_start] = s390_cond_extensions[i].nibble;
strcat (new_mnemonic, s390_cond_extensions[i].extension);
strcat (new_mnemonic, suffix);
insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits);
}
return;
*************** main (void)
*** 318,323 ****
--- 319,326 ----
min_cpu = S390_OPCODE_Z9_109;
else if (strcmp (cpu_string, "z9-ec") == 0)
min_cpu = S390_OPCODE_Z9_EC;
+ else if (strcmp (cpu_string, "z10") == 0)
+ min_cpu = S390_OPCODE_Z10;
else {
fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
exit (1);
*************** main (void)
*** 343,353 ****
str++;
} while (*str != 0);
! if (!strchr (mnemonic, '*'))
! insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits);
! else
! expandConditionalJump (opcode, mnemonic, format,
! min_cpu, mode_bits);
}
else
fprintf (stderr, "Couldn't scan line %s\n", currentLine);
--- 346,352 ----
str++;
} while (*str != 0);
! insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits);
}
else
fprintf (stderr, "Couldn't scan line %s\n", currentLine);
Index: gas/testsuite/gas/s390/s390.exp
===================================================================
*** gas/testsuite/gas/s390/s390.exp.orig 2008-03-18 17:57:42.000000000 +0100
--- gas/testsuite/gas/s390/s390.exp 2008-03-18 18:28:03.000000000 +0100
*************** if [expr [istarget "s390-*-*"] || [ista
*** 20,25 ****
--- 20,26 ----
run_dump_test "zarch-z990" "{as -m64} {as -march=z990}"
run_dump_test "zarch-z9-109" "{as -m64} {as -march=z9-109}"
run_dump_test "zarch-z9-ec" "{as -m64} {as -march=z9-ec}"
+ run_dump_test "zarch-z10" "{as -m64} {as -march=z10}"
run_dump_test "zarch-reloc" "{as -m64}"
run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}"
}
Index: include/opcode/s390.h
===================================================================
*** include/opcode/s390.h.orig 2008-03-18 17:57:42.000000000 +0100
--- include/opcode/s390.h 2008-03-18 18:28:03.000000000 +0100
*************** enum s390_opcode_cpu_val
*** 37,43 ****
S390_OPCODE_Z900,
S390_OPCODE_Z990,
S390_OPCODE_Z9_109,
! S390_OPCODE_Z9_EC
};
/* The opcode table is an array of struct s390_opcode. */
--- 37,44 ----
S390_OPCODE_Z900,
S390_OPCODE_Z990,
S390_OPCODE_Z9_109,
! S390_OPCODE_Z9_EC,
! S390_OPCODE_Z10
};
/* The opcode table is an array of struct s390_opcode. */
Index: opcodes/s390-opc.c
===================================================================
*** opcodes/s390-opc.c.orig 2008-03-18 17:58:12.000000000 +0100
--- opcodes/s390-opc.c 2008-03-18 18:28:03.000000000 +0100
*************** const struct s390_operand s390_operands[
*** 42,47 ****
--- 42,49 ----
#define UNUSED 0
{ 0, 0, 0 }, /* Indicates the end of the operand list */
+ /* General purpose register operands. */
+
#define R_8 1 /* GPR starting at position 8 */
{ 4, 8, S390_OPERAND_GPR },
#define R_12 2 /* GPR starting at position 12 */
*************** const struct s390_operand s390_operands[
*** 54,141 ****
{ 4, 24, S390_OPERAND_GPR },
#define R_28 6 /* GPR starting at position 28 */
{ 4, 28, S390_OPERAND_GPR },
! #define R_32 7 /* GPR starting at position 32 */
{ 4, 32, S390_OPERAND_GPR },
! #define F_8 8 /* FPR starting at position 8 */
{ 4, 8, S390_OPERAND_FPR },
! #define F_12 9 /* FPR starting at position 12 */
{ 4, 12, S390_OPERAND_FPR },
! #define F_16 10 /* FPR starting at position 16 */
{ 4, 16, S390_OPERAND_FPR },
! #define F_20 11 /* FPR starting at position 16 */
{ 4, 16, S390_OPERAND_FPR },
! #define F_24 12 /* FPR starting at position 24 */
{ 4, 24, S390_OPERAND_FPR },
! #define F_28 13 /* FPR starting at position 28 */
{ 4, 28, S390_OPERAND_FPR },
! #define F_32 14 /* FPR starting at position 32 */
{ 4, 32, S390_OPERAND_FPR },
! #define A_8 15 /* Access reg. starting at position 8 */
{ 4, 8, S390_OPERAND_AR },
! #define A_12 16 /* Access reg. starting at position 12 */
{ 4, 12, S390_OPERAND_AR },
! #define A_24 17 /* Access reg. starting at position 24 */
{ 4, 24, S390_OPERAND_AR },
! #define A_28 18 /* Access reg. starting at position 28 */
{ 4, 28, S390_OPERAND_AR },
! #define C_8 19 /* Control reg. starting at position 8 */
{ 4, 8, S390_OPERAND_CR },
! #define C_12 20 /* Control reg. starting at position 12 */
{ 4, 12, S390_OPERAND_CR },
! #define B_16 21 /* Base register starting at position 16 */
{ 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
! #define B_32 22 /* Base register starting at position 32 */
{ 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
! #define X_12 23 /* Index register starting at position 12 */
{ 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
! #define D_20 24 /* Displacement starting at position 20 */
{ 12, 20, S390_OPERAND_DISP },
! #define D_36 25 /* Displacement starting at position 36 */
{ 12, 36, S390_OPERAND_DISP },
! #define D20_20 26 /* 20 bit displacement starting at 20 */
{ 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
! #define L4_8 27 /* 4 bit length starting at position 8 */
{ 4, 8, S390_OPERAND_LENGTH },
! #define L4_12 28 /* 4 bit length starting at position 12 */
{ 4, 12, S390_OPERAND_LENGTH },
! #define L8_8 29 /* 8 bit length starting at position 8 */
{ 8, 8, S390_OPERAND_LENGTH },
! #define U4_8 30 /* 4 bit unsigned value starting at 8 */
{ 4, 8, 0 },
! #define U4_12 31 /* 4 bit unsigned value starting at 12 */
{ 4, 12, 0 },
! #define U4_16 32 /* 4 bit unsigned value starting at 16 */
{ 4, 16, 0 },
! #define U4_20 33 /* 4 bit unsigned value starting at 20 */
{ 4, 20, 0 },
! #define U8_8 34 /* 8 bit unsigned value starting at 8 */
{ 8, 8, 0 },
! #define U8_16 35 /* 8 bit unsigned value starting at 16 */
{ 8, 16, 0 },
! #define I16_16 36 /* 16 bit signed value starting at 16 */
! { 16, 16, S390_OPERAND_SIGNED },
! #define U16_16 37 /* 16 bit unsigned value starting at 16 */
{ 16, 16, 0 },
! #define J16_16 38 /* PC relative jump offset at 16 */
{ 16, 16, S390_OPERAND_PCREL },
! #define J32_16 39 /* PC relative long offset at 16 */
{ 32, 16, S390_OPERAND_PCREL },
! #define I32_16 40 /* 32 bit signed value starting at 16 */
! { 32, 16, S390_OPERAND_SIGNED },
! #define U32_16 41 /* 32 bit unsigned value starting at 16 */
! { 32, 16, 0 },
! #define M_16 42 /* 4 bit optional mask starting at 16 */
{ 4, 16, S390_OPERAND_OPTIONAL },
- #define RO_28 43 /* optional GPR starting at position 28 */
- { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }
};
--- 56,180 ----
{ 4, 24, S390_OPERAND_GPR },
#define R_28 6 /* GPR starting at position 28 */
{ 4, 28, S390_OPERAND_GPR },
! #define RO_28 7 /* optional GPR starting at position 28 */
! { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },
! #define R_32 8 /* GPR starting at position 32 */
{ 4, 32, S390_OPERAND_GPR },
! /* Floating point register operands. */
!
! #define F_8 9 /* FPR starting at position 8 */
{ 4, 8, S390_OPERAND_FPR },
! #define F_12 10 /* FPR starting at position 12 */
{ 4, 12, S390_OPERAND_FPR },
! #define F_16 11 /* FPR starting at position 16 */
{ 4, 16, S390_OPERAND_FPR },
! #define F_20 12 /* FPR starting at position 16 */
{ 4, 16, S390_OPERAND_FPR },
! #define F_24 13 /* FPR starting at position 24 */
{ 4, 24, S390_OPERAND_FPR },
! #define F_28 14 /* FPR starting at position 28 */
{ 4, 28, S390_OPERAND_FPR },
! #define F_32 15 /* FPR starting at position 32 */
{ 4, 32, S390_OPERAND_FPR },
! /* Access register operands. */
!
! #define A_8 16 /* Access reg. starting at position 8 */
{ 4, 8, S390_OPERAND_AR },
! #define A_12 17 /* Access reg. starting at position 12 */
{ 4, 12, S390_OPERAND_AR },
! #define A_24 18 /* Access reg. starting at position 24 */
{ 4, 24, S390_OPERAND_AR },
! #define A_28 19 /* Access reg. starting at position 28 */
{ 4, 28, S390_OPERAND_AR },
! /* Control register operands. */
!
! #define C_8 20 /* Control reg. starting at position 8 */
{ 4, 8, S390_OPERAND_CR },
! #define C_12 21 /* Control reg. starting at position 12 */
{ 4, 12, S390_OPERAND_CR },
! /* Base register operands. */
!
! #define B_16 22 /* Base register starting at position 16 */
{ 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
! #define B_32 23 /* Base register starting at position 32 */
{ 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
! #define X_12 24 /* Index register starting at position 12 */
{ 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
! /* Address displacement operands. */
!
! #define D_20 25 /* Displacement starting at position 20 */
{ 12, 20, S390_OPERAND_DISP },
! #define D_36 26 /* Displacement starting at position 36 */
{ 12, 36, S390_OPERAND_DISP },
! #define D20_20 27 /* 20 bit displacement starting at 20 */
{ 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
! /* Length operands. */
!
! #define L4_8 28 /* 4 bit length starting at position 8 */
{ 4, 8, S390_OPERAND_LENGTH },
! #define L4_12 29 /* 4 bit length starting at position 12 */
{ 4, 12, S390_OPERAND_LENGTH },
! #define L8_8 30 /* 8 bit length starting at position 8 */
{ 8, 8, S390_OPERAND_LENGTH },
! /* Signed immediate operands. */
!
! #define I8_8 31 /* 8 bit signed value starting at 8 */
! { 8, 8, S390_OPERAND_SIGNED },
! #define I8_32 32 /* 8 bit signed value starting at 32 */
! { 8, 32, S390_OPERAND_SIGNED },
! #define I16_16 33 /* 16 bit signed value starting at 16 */
! { 16, 16, S390_OPERAND_SIGNED },
! #define I16_32 34 /* 16 bit signed value starting at 32 */
! { 16, 32, S390_OPERAND_SIGNED },
! #define I32_16 35 /* 32 bit signed value starting at 16 */
! { 32, 16, S390_OPERAND_SIGNED },
!
! /* Unsigned immediate operands. */
!
! #define U4_8 36 /* 4 bit unsigned value starting at 8 */
{ 4, 8, 0 },
! #define U4_12 37 /* 4 bit unsigned value starting at 12 */
{ 4, 12, 0 },
! #define U4_16 38 /* 4 bit unsigned value starting at 16 */
{ 4, 16, 0 },
! #define U4_20 39 /* 4 bit unsigned value starting at 20 */
{ 4, 20, 0 },
! #define U4_32 40 /* 4 bit unsigned value starting at 32 */
! { 4, 32, 0 },
! #define U8_8 41 /* 8 bit unsigned value starting at 8 */
{ 8, 8, 0 },
! #define U8_16 42 /* 8 bit unsigned value starting at 16 */
{ 8, 16, 0 },
! #define U8_24 43 /* 8 bit unsigned value starting at 24 */
! { 8, 24, 0 },
! #define U8_32 44 /* 8 bit unsigned value starting at 32 */
! { 8, 32, 0 },
! #define U16_16 45 /* 16 bit unsigned value starting at 16 */
{ 16, 16, 0 },
! #define U16_32 46 /* 16 bit unsigned value starting at 32 */
! { 16, 32, 0 },
! #define U32_16 47 /* 32 bit unsigned value starting at 16 */
! { 32, 16, 0 },
!
! /* PC-relative address operands. */
!
! #define J16_16 48 /* PC relative jump offset at 16 */
{ 16, 16, S390_OPERAND_PCREL },
! #define J32_16 49 /* PC relative long offset at 16 */
{ 32, 16, S390_OPERAND_PCREL },
!
! /* Conditional mask operands. */
!
! #define M_16 50 /* 4 bit optional mask starting at 16 */
{ 4, 16, S390_OPERAND_OPTIONAL },
};
*************** const struct s390_operand s390_operands[
*** 185,190 ****
--- 224,240 ----
#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
+ #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
+ #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */
+ #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */
+ #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */
+ #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */
+ #define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */
+ #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */
+ #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */
+ #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */
+ #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
+ #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
*************** const struct s390_operand s390_operands[
*** 195,200 ****
--- 245,254 ----
#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */
+ #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
+ #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
+ #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
+ #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */
#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
*************** const struct s390_operand s390_operands[
*** 221,226 ****
--- 275,282 ----
#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */
#define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
#define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */
+ #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */
+ #define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */
#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
*************** const struct s390_operand s390_operands[
*** 228,233 ****
--- 284,291 ----
#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */
+ #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
+ #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */
#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
*************** const struct s390_operand s390_operands[
*** 248,259 ****
--- 306,321 ----
#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */
#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */
#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */
+ #define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */
#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */
+ #define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */
+ #define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */
+ #define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */
#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */
*************** const struct s390_operand s390_operands[
*** 262,273 ****
#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
- #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
--- 324,346 ----
#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
+ #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+ #define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+ #define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+ #define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff }
+ #define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
+ #define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff }
+ #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
+ #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
*************** const struct s390_operand s390_operands[
*** 278,283 ****
--- 351,360 ----
#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+ #define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
*************** const struct s390_operand s390_operands[
*** 302,307 ****
--- 379,386 ----
#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
#define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+ #define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+ #define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
*************** const struct s390_operand s390_operands[
*** 309,314 ****
--- 388,395 ----
#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+ #define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
+ #define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
*************** const struct s390_operand s390_operands[
*** 329,340 ****
--- 410,425 ----
#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+ #define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
*************** const struct s390_operand s390_operands[
*** 343,351 ****
#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
! #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
/* The opcode formats table (blueprints for .insn pseudo mnemonic). */
--- 428,437 ----
#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+ #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
!
/* The opcode formats table (blueprints for .insn pseudo mnemonic). */
*************** const struct s390_opcode s390_opformats[
*** 356,364 ****
--- 442,452 ----
{ "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 },
{ "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 },
{ "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 },
+ { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 },
{ "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 },
{ "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 },
{ "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 },
+ { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 },
{ "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 },
{ "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 },
{ "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 },
*************** const struct s390_opcode s390_opformats[
*** 370,375 ****
--- 458,464 ----
{ "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 },
{ "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 },
{ "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 },
+ { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 },
{ "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
{ "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 },
{ "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 },
Index: opcodes/s390-opc.txt
===================================================================
*** opcodes/s390-opc.txt.orig 2008-03-18 17:58:12.000000000 +0100
--- opcodes/s390-opc.txt 2008-03-18 18:44:48.000000000 +0100
*************** a700 tmh RI_RU "test under mask high" g5
*** 262,272 ****
--- 262,296 ----
a701 tml RI_RU "test under mask low" g5 esa,zarch
0700 nopr RR_0R "no operation" g5 esa,zarch
0700 b*8r RR_0R "conditional branch" g5 esa,zarch
+ 0710 bor RR_0R "branch on overflow / if ones" g5 esa,zarch
+ 0720 bpr RR_0R "branch on plus" g5 esa,zarch
+ 0740 bmr RR_0R "branch on minus / if mixed" g5 esa,zarch
+ 0770 bnzr RR_0R "branch on not zero / if not zeros" g5 esa,zarch
+ 0780 bzr RR_0R "branch on zero / if zeros" g5 esa,zarch
+ 07b0 bnmr RR_0R "branch on not minus / if not mixed" g5 esa,zarch
+ 07d0 bnpr RR_0R "branch on not plus" g5 esa,zarch
+ 07e0 bnor RR_0R "branch on not overflow / if not ones" g5 esa,zarch
07f0 br RR_0R "unconditional branch" g5 esa,zarch
4700 nop RX_0RRD "no operation" g5 esa,zarch
4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch
+ 4710 bo RX_0RRD "branch on overflow / if ones" g5 esa,zarch
+ 4720 bp RX_0RRD "branch on plus" g5 esa,zarch
+ 4740 bm RX_0RRD "branch on minus / if mixed" g5 esa,zarch
+ 4770 bnz RX_0RRD "branch on not zero / if not zeros" g5 esa,zarch
+ 4780 bz RX_0RRD "branch on zero / if zeros" g5 esa,zarch
+ 47b0 bnm RX_0RRD "branch on not minus / if not mixed" g5 esa,zarch
+ 47d0 bnp RX_0RRD "branch on not plus" g5 esa,zarch
+ 47e0 bno RX_0RRD "branch on not overflow / if not ones" g5 esa,zarch
47f0 b RX_0RRD "unconditional branch" g5 esa,zarch
a704 j*8 RI_0P "conditional jump" g5 esa,zarch
+ a714 jo RI_0P "jump on overflow / if ones" g5 esa,zarch
+ a724 jp RI_0P "jump on plus" g5 esa,zarch
+ a744 jm RI_0P "jump on minus / if mixed" g5 esa,zarch
+ a774 jnz RI_0P "jump on not zero / if not zeros" g5 esa,zarch
+ a784 jz RI_0P "jump on zero / if zeros" g5 esa,zarch
+ a7b4 jnm RI_0P "jump on not minus / if not mixed" g5 esa,zarch
+ a7d4 jnp RI_0P "jump on not plus" g5 esa,zarch
+ a7e4 jno RI_0P "jump on not overflow / if not ones" g5 esa,zarch
a7f4 j RI_0P "unconditional jump" g5 esa,zarch
b34a axbr RRE_FF "add extended bfp" g5 esa,zarch
b31a adbr RRE_FF "add long bfp" g5 esa,zarch
*************** a702 tmhh RI_RU "test under mask high hi
*** 463,468 ****
--- 487,500 ----
a703 tmhl RI_RU "test under mask high low" z900 zarch
c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch
c004 jg*8 RIL_0P "conditional jump long" z900 esa,zarch
+ c014 jgo RIL_0P "jump long on overflow / if ones" z900 esa,zarch
+ c024 jgp RIL_0P "jump long on plus" z900 esa,zarch
+ c044 jgm RIL_0P "jump long on minus / if mixed" z900 esa,zarch
+ c074 jgnz RIL_0P "jump long on not zero / if not zeros" z900 esa,zarch
+ c084 jgz RIL_0P "jump long on zero / if zeros" z900 esa,zarch
+ c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" z900 esa,zarch
+ c0d4 jgnp RIL_0P "jump long on not plus" z900 esa,zarch
+ c0e4 jgno RIL_0P "jump long on not overflow / if not ones" z900 esa,zarch
c0f4 jg RIL_0P "unconditional jump long" z900 esa,zarch
c005 brasl RIL_RP "branch relative and save long" z900 esa,zarch
a707 brctg RI_RP "branch relative on count 64" z900 zarch
*************** ed0000000059 tdgxt RXE_FRRD "test data g
*** 852,854 ****
--- 884,988 ----
010a pfpo E "perform floating point operation" z9-ec zarch
c801 ectg SSF_RRDRD "extract cpu time" z9-ec zarch
c802 csst SSF_RRDRD "compare and swap and store" z9-ec zarch
+ eb000000006a asi SIY_IRD "add immediate (32<8)" z10 zarch
+ eb000000007a agsi SIY_IRD "add immediate (64<8)" z10 zarch
+ eb000000006e alsi SIY_IRD "add logical with signed immediate (32<8)" z10 zarch
+ eb000000007e algsi SIY_IRD "add logical with signed immediate (64<8)" z10 zarch
+ c60d crl RIL_RP "compare relative long (32)" z10 zarch
+ c608 cgrl RIL_RP "compare relative long (64)" z10 zarch
+ c60c cgfrl RIL_RP "compare relative long (64<32)" z10 zarch
+ ec00000000f6 crb*32 RRS_RRRD0 "compare and branch (32)" z10 zarch
+ ec00000000f6 crb RRS_RRRDU "compare and branch (32)" z10 zarch
+ ec00000000e4 cgrb*32 RRS_RRRD0 "compare and branch (64)" z10 zarch
+ ec00000000e4 cgrb RRS_RRRDU "compare and branch (64)" z10 zarch
+ ec0000000076 crj*32 RIE_RRP "compare and branch relative (32)" z10 zarch
+ ec0000000076 crj RIE_RRPU "compare and branch relative (32)" z10 zarch
+ ec0000000064 cgrj*32 RIE_RRP0 "compare and branch relative (64)" z10 zarch
+ ec0000000064 cgrj RIE_RRPU "compare and branch relative (64)" z10 zarch
+ ec00000000fe cib*12 RIS_R0RDI "compare immediate and branch (32<8)" z10 zarch
+ ec00000000fe cib RIS_RURDI "compare immediate and branch (32<8)" z10 zarch
+ ec00000000fc cgib*12 RIS_R0RDI "compare immediate and branch (64<8)" z10 zarch
+ ec00000000fc cgib RIS_RURDI "compare immediate and branch (64<8)" z10 zarch
+ ec000000007e cij*12 RIE_R0PI "compare immediate and branch relative (32<8)" z10 zarch
+ ec000000007e cij RIE_RUPI "compare immediate and branch relative (32<8)" z10 zarch
+ ec000000007c cgij*12 RIE_R0PI "compare immediate and branch relative (64<8)" z10 zarch
+ ec000000007c cgij RIE_RUPI "compare immediate and branch relative (64<8)" z10 zarch
+ b97200000000 crt*16 RRF_00RR "compare and trap" z10 zarch
+ b972 crt RRF_U0RR "compare and trap" z10 zarch
+ b96000000000 cgrt*16 RRF_00RR "compare and trap 64" z10 zarch
+ b960 cgrt RRF_U0RR "compare and trap 64" z10 zarch
+ ec0000000072 cit*32 RIE_R0I0 "compare immediate and trap (32<16)" z10 zarch
+ ec0000000072 cit RIE_R0IU "compare immediate and trap (32<16)" z10 zarch
+ ec0000000070 cgit*32 RIE_R0I0 "compare immediate and trap (64<16)" z10 zarch
+ ec0000000070 cgit RIE_R0IU "compare immediate and trap (64<16)" z10 zarch
+ e30000000034 cgh RXY_RRRD "compare halfword (64<16)" z10 zarch
+ e554 chhsi SIL_RDI "compare halfword immediate (16<16)" z10 zarch
+ e55c chsi SIL_RDI "compare halfword immediate (32<16)" z10 zarch
+ e558 cghsi SIL_RDI "compare halfword immediate (64<16)" z10 zarch
+ c605 chrl RIL_RP "compare halfword relative long (32<8)" z10 zarch
+ c604 cghrl RIL_RP "compare halfword relative long (64<8)" z10 zarch
+ e555 clhhsi SIL_RDU "compare logical immediate (16<16)" z10 zarch
+ e55d clfhsi SIL_RDU "compare logical immediate (32<16)" z10 zarch
+ e559 clghsi SIL_RDU "compare logical immediate (64<16)" z10 zarch
+ c60f clrl RIL_RP "compare logical relative long (32)" z10 zarch
+ c60a clgrl RIL_RP "compare logical relative long (64)" z10 zarch
+ c60e clgfrl RIL_RP "compare logical relative long (64<32)" z10 zarch
+ c607 clhrl RIL_RP "compare logical relative long (32<16)" z10 zarch
+ c606 clghrl RIL_RP "compare logical relative long (64<16)" z10 zarch
+ ec00000000f7 clrb*32 RRS_RRRD0 "compare logical and branch (32)" z10 zarch
+ ec00000000f7 clrb RRS_RRRDU "compare logical and branch (32)" z10 zarch
+ ec00000000e5 clgrb*32 RRS_RRRD0 "compare logical and branch (64)" z10 zarch
+ ec00000000e5 clgrb RRS_RRRDU "compare logical and branch (64)" z10 zarch
+ ec0000000077 clrj*32 RIE_RRP "compare logical and branch relative (32)" z10 zarch
+ ec0000000077 clrj RIE_RRPU "compare logical and branch relative (32)" z10 zarch
+ ec0000000065 clgrj*32 RIE_RRP "compare logical and branch relative (64)" z10 zarch
+ ec0000000065 clgrj RIE_RRPU "compare logical and branch relative (64)" z10 zarch
+ ec00000000ff clib*12 RIS_R0RDU "compare logical immediate and branch (32<8)" z10 zarch
+ ec00000000ff clib RIS_RURDU "compare logical immediate and branch (32<8)" z10 zarch
+ ec00000000fd clgib*12 RIS_R0RDU "compare logical immediate and branch (64<8)" z10 zarch
+ ec00000000fd clgib RIS_RURDU "compare logical immediate and branch (64<8)" z10 zarch
+ ec000000007f clij*12 RIE_R0PU "compare logical immediate and branch relative (32<8)" z10 zarch
+ ec000000007f clij RIE_RUPU "compare logical immediate and branch relative (32<8)" z10 zarch
+ ec000000007d clgij*12 RIE_R0PU "compare logical immediate and branch relative (64<8)" z10 zarch
+ ec000000007d clgij RIE_RUPU "compare logical immediate and branch relative (64<8)" z10 zarch
+ b97300000000 clrt*16 RRF_00RR "compare logical and trap (32)" z10 zarch
+ b973 clrt RRF_U0RR "compare logical and trap (32)" z10 zarch
+ b96100000000 clgrt*16 RRF_00RR "compare logical and trap (64)" z10 zarch
+ b961 clgrt RRF_U0RR "compare logical and trap (64)" z10 zarch
+ ec0000000073 clfit*32 RIE_R0U0 "compare logical and trap (32<16)" z10 zarch
+ ec0000000073 clfit RIE_R0UU "compare logical and trap (32<16)" z10 zarch
+ ec0000000071 clgit*32 RIE_R0U0 "compare logical and trap (64<16)" z10 zarch
+ ec0000000071 clgit RIE_R0UU "compare logical and trap (64<16)" z10 zarch
+ eb000000004c ecag RSY_RRRD "extract cache attribute" z10 zarch
+ c40d lrl RIL_RP "load relative long (32)" z10 zarch
+ c408 lgrl RIL_RP "load relative long (64)" z10 zarch
+ c40c lgfrl RIL_RP "load relative long (64<32)" z10 zarch
+ e30000000075 laey RXY_RRRD "load address extended" z10 zarch
+ e30000000032 ltgf RXY_RRRD "load and test (64<32)" z10 zarch
+ c405 lhrl RIL_RP "load halfword relative long (32<16)" z10 zarch
+ c404 lghrl RIL_RP "load halfword relative long (64<16)" z10 zarch
+ c40e llgfrl RIL_RP "load logical relative long (64<32)" z10 zarch
+ c402 llhrl RIL_RP "load logical halfword relative long (32<16)" z10 zarch
+ c406 llghrl RIL_RP "load logical halfword relative long (64<16)" z10 zarch
+ e544 mvhhi SIL_RDI "move (16<16)" z10 zarch
+ e54c mvhi SIL_RDI "move (32<16)" z10 zarch
+ e548 mvghi SIL_RDI "move (64<16)" z10 zarch
+ e3000000005c mfy RXY_RRRD "multiply" z10 zarch
+ e3000000007c mhy RXY_RRRD "multiply halfword" z10 zarch
+ c201 msfi RIL_RI "multiply single immediate (32)" z10 zarch
+ c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch
+ e30000000036 pfd RXY_URRD "prefetch data" z10 zarch
+ c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch
+ ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch
+ ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch
+ ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch
+ ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch
+ c40f strl RIL_RP "store relative long (32)" z10 zarch
+ c40b stgrl RIL_RP "store relative long (64)" z10 zarch
+ c407 sthrl RIL_RP "store halfword relative long" z10 zarch
+ c600 exrl RIL_RP "execute relative long" z10 zarch
+ af00 mc SI_URD "monitor call" z10 zarch
+ b9a2 ptf RRE_R0 "perform topology function" z10 zarch
+ b9af pfmf RRE_RR "perform frame management function" z10 zarch
+ b9bf trte RRF_M0RR "translate and test extended" z10 zarch
+ b9bd trtre RRF_M0RR "translate and test reverse extended" z10 zarch