This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
Blackfin: Use local symbols for hardware loops in gas
- From: Bernd Schmidt <bernds_cb1 at t-online dot de>
- To: binutils at sources dot redhat dot com
- Cc: Jie Zhang <jzhang918 at gmail dot com>
- Date: Wed, 26 Mar 2008 17:35:40 +0100
- Subject: Blackfin: Use local symbols for hardware loops in gas
The Blackfin assembler knows two pseudo instructions, LOOP_BEGIN and
LOOP_END, which get expanded to a real LSETUP instruction with two
labels as argument. This patch ensures that the labels we create aren't
visible globally. Like the others in this series this change is by Jie
Zhang.
Bernd
--
This footer brought to you by insane German lawmakers.
Analog Devices GmbH Wilhelm-Wagenfeld-Str. 6 80807 Muenchen
Sitz der Gesellschaft Muenchen, Registergericht Muenchen HRB 40368
Geschaeftsfuehrer Thomas Wessel, William A. Martin, Margaret Seif
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.3515
diff -c -p -r1.3515 ChangeLog
*** gas/ChangeLog 26 Mar 2008 16:21:09 -0000 1.3515
--- gas/ChangeLog 26 Mar 2008 16:31:13 -0000
***************
*** 20,25 ****
--- 20,29 ----
data register in each rule that moves to the data
register.
+ * config/tc-bfin.c (bfin_start_line_hook): Localize the labels
+ generated for LOOP_BEGIN and LOOP_END instructions.
+ (bfin_gen_loop): Likewise.
+
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z10 option added.
Index: gas/config/tc-bfin.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-bfin.c,v
retrieving revision 1.14
diff -c -p -r1.14 tc-bfin.c
*** gas/config/tc-bfin.c 17 Oct 2007 16:45:55 -0000 1.14
--- gas/config/tc-bfin.c 26 Mar 2008 16:31:13 -0000
*************** bfin_start_line_hook ()
*** 866,880 ****
input_line_pointer = c;
if (maybe_end)
{
! label_name = (char *) xmalloc ((c - c1) + strlen ("__END") + 1);
label_name[0] = 0;
strncat (label_name, c1, c-c1);
strcat (label_name, "__END");
}
else /* maybe_begin. */
{
! label_name = (char *) xmalloc ((c - c1) + strlen ("__BEGIN") + 1);
label_name[0] = 0;
strncat (label_name, c1, c-c1);
strcat (label_name, "__BEGIN");
}
--- 866,882 ----
input_line_pointer = c;
if (maybe_end)
{
! label_name = (char *) xmalloc ((c - c1) + strlen ("__END") + 5);
label_name[0] = 0;
+ strcat (label_name, "L$L$");
strncat (label_name, c1, c-c1);
strcat (label_name, "__END");
}
else /* maybe_begin. */
{
! label_name = (char *) xmalloc ((c - c1) + strlen ("__BEGIN") + 5);
label_name[0] = 0;
+ strcat (label_name, "L$L$");
strncat (label_name, c1, c-c1);
strcat (label_name, "__BEGIN");
}
*************** bfin_start_line_hook ()
*** 884,891 ****
/* Loop_End follows the last instruction in the loop.
Adjust label address. */
if (maybe_end)
! line_label->sy_value.X_add_number -= last_insn_size;
!
}
/* Special extra functions that help bfin-parse.y perform its job. */
--- 886,892 ----
/* Loop_End follows the last instruction in the loop.
Adjust label address. */
if (maybe_end)
! ((struct local_symbol *) line_label)->lsy_value -= last_insn_size;
}
/* Special extra functions that help bfin-parse.y perform its job. */
*************** bfin_gen_loop (Expr_Node *expr, REG_T re
*** 1878,1892 ****
Expr_Node *lbegin, *lend;
loopsym = expr->value.s_value;
! lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 1);
! lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 1);
lbeginsym[0] = 0;
lendsym[0] = 0;
strcat (lbeginsym, loopsym);
strcat (lbeginsym, "__BEGIN");
strcat (lendsym, loopsym);
strcat (lendsym, "__END");
--- 1879,1895 ----
Expr_Node *lbegin, *lend;
loopsym = expr->value.s_value;
! lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 5);
! lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 5);
lbeginsym[0] = 0;
lendsym[0] = 0;
+ strcat (lbeginsym, "L$L$");
strcat (lbeginsym, loopsym);
strcat (lbeginsym, "__BEGIN");
+ strcat (lendsym, "L$L$");
strcat (lendsym, loopsym);
strcat (lendsym, "__END");
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.1327
diff -c -p -r1.1327 ChangeLog
*** gas/testsuite/ChangeLog 26 Mar 2008 16:21:10 -0000 1.1327
--- gas/testsuite/ChangeLog 26 Mar 2008 16:31:13 -0000
***************
*** 15,21 ****
Add check for mismatch of accumulator and data register.
* gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
for IU option.
!
From Mike Frysinger <michael.frysinger@analog.com>
* gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test
for mismatched half registers in vector multipy-accumulate
--- 15,25 ----
Add check for mismatch of accumulator and data register.
* gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
for IU option.
!
! * gas/bfin/flow.d: Adjust since the generated labels for LOOP_BEGIN
! and LOOP_END instruction are local now.
! * gas/bfin/flow2.d: Likewise.
!
From Mike Frysinger <michael.frysinger@analog.com>
* gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test
for mismatched half registers in vector multipy-accumulate
Index: gas/testsuite/gas/bfin/flow.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/bfin/flow.d,v
retrieving revision 1.1
diff -c -p -r1.1 flow.d
*** gas/testsuite/gas/bfin/flow.d 30 Sep 2005 15:10:16 -0000 1.1
--- gas/testsuite/gas/bfin/flow.d 26 Mar 2008 16:31:14 -0000
*************** Disassembly of section .text:
*** 39,47 ****
3e: 14 00 RTE;
00000040 <loop_lc0>:
! 40: 82 e0 13 00 LSETUP\(44 <first_loop__BEGIN>,66 <first_loop__END>\)LC0;
!
! 00000044 <first_loop__BEGIN>:
44: 38 e4 7b fc R0=\[FP\+-3604\];
48: 49 60 R1=0x9\(x\);
4a: 38 e4 7b fc R0=\[FP\+-3604\];
--- 39,45 ----
3e: 14 00 RTE;
00000040 <loop_lc0>:
! 40: 82 e0 13 00 LSETUP\(44 <loop_lc0\+0x4>,66 <loop_lc0\+0x26>\)LC0;
44: 38 e4 7b fc R0=\[FP\+-3604\];
48: 49 60 R1=0x9\(x\);
4a: 38 e4 7b fc R0=\[FP\+-3604\];
*************** Disassembly of section .text:
*** 55,81 ****
5e: 10 93 \[P2\]=R0;
60: 38 e4 7b fc R0=\[FP\+-3604\];
64: 08 64 R0\+=0x1;
-
- 00000066 <first_loop__END>:
66: 38 e6 7b fc \[FP\+-3604\]=R0;
! 6a: a2 e0 02 40 LSETUP\(6e <second_loop__BEGIN>,6e <second_loop__BEGIN>\)LC0=P4;
!
! 0000006e <second_loop__BEGIN>:
6e: 00 00 NOP;
! 70: e0 e0 00 10 LSETUP\(70 <second_loop__BEGIN\+0x2>,70 <second_loop__BEGIN\+0x2>\)LC0=P1>>1;
! 74: 82 e0 ff 03 LSETUP\(78 <second_loop__BEGIN\+0xa>,72 <second_loop__BEGIN\+0x4>\)LC0;
! 78: af e0 00 52 LSETUP\(76 <second_loop__BEGIN\+0x8>,fffffc78 <another_loop__END\+0xfffffbba>\)LC0=P5;
! 7c: ef e0 02 00 LSETUP\(7a <second_loop__BEGIN\+0xc>,80 <loop_lc1>\)LC0=P0>>1;
00000080 <loop_lc1>:
80: 90 e0 00 00 LSETUP\(80 <loop_lc1>,80 <loop_lc1>\)LC1;
84: b0 e0 00 40 LSETUP\(84 <loop_lc1\+0x4>,84 <loop_lc1\+0x4>\)LC1=P4;
! 88: f8 e0 1b 10 LSETUP\(78 <second_loop__BEGIN\+0xa>,be <another_loop__END>\)LC1=P1>>1;
8c: 92 e0 ff 03 LSETUP\(90 <loop_lc1\+0x10>,8a <loop_lc1\+0xa>\)LC1;
! 90: bf e0 00 52 LSETUP\(8e <loop_lc1\+0xe>,fffffc90 <another_loop__END\+0xfffffbd2>\)LC1=P5;
! 94: ff e0 02 00 LSETUP\(92 <loop_lc1\+0x12>,98 <another_loop__BEGIN>\)LC1=P0>>1;
!
! 00000098 <another_loop__BEGIN>:
98: 38 e4 7a fc R0=\[FP\+-3608\];
9c: 00 32 P0=R0;
9e: 42 44 P2=P0<<2;
--- 53,73 ----
5e: 10 93 \[P2\]=R0;
60: 38 e4 7b fc R0=\[FP\+-3604\];
64: 08 64 R0\+=0x1;
66: 38 e6 7b fc \[FP\+-3604\]=R0;
! 6a: a2 e0 02 40 LSETUP\(6e <loop_lc0\+0x2e>,6e <loop_lc0\+0x2e>\)LC0=P4;
6e: 00 00 NOP;
! 70: e0 e0 00 10 LSETUP\(70 <loop_lc0\+0x30>,70 <loop_lc0\+0x30>\)LC0=P1>>1;
! 74: 82 e0 ff 03 LSETUP\(78 <loop_lc0\+0x38>,72 <loop_lc0\+0x32>\)LC0;
! 78: af e0 00 52 LSETUP\(76 <loop_lc0\+0x36>,fffffc78 <loop_lc1\+0xfffffbf8>\)LC0=P5;
! 7c: ef e0 02 00 LSETUP\(7a <loop_lc0\+0x3a>,80 <loop_lc1>\)LC0=P0>>1;
00000080 <loop_lc1>:
80: 90 e0 00 00 LSETUP\(80 <loop_lc1>,80 <loop_lc1>\)LC1;
84: b0 e0 00 40 LSETUP\(84 <loop_lc1\+0x4>,84 <loop_lc1\+0x4>\)LC1=P4;
! 88: f8 e0 1b 10 LSETUP\(78 <loop_lc0\+0x38>,be <loop_lc1\+0x3e>\)LC1=P1>>1;
8c: 92 e0 ff 03 LSETUP\(90 <loop_lc1\+0x10>,8a <loop_lc1\+0xa>\)LC1;
! 90: bf e0 00 52 LSETUP\(8e <loop_lc1\+0xe>,fffffc90 <loop_lc1\+0xfffffc10>\)LC1=P5;
! 94: ff e0 02 00 LSETUP\(92 <loop_lc1\+0x12>,98 <loop_lc1\+0x18>\)LC1=P0>>1;
98: 38 e4 7a fc R0=\[FP\+-3608\];
9c: 00 32 P0=R0;
9e: 42 44 P2=P0<<2;
*************** Disassembly of section .text:
*** 91,96 ****
b8: 00 32 P0=R0;
ba: 82 5a P2=P2\+P0;
bc: 10 91 R0=\[P2\];
-
- 000000be <another_loop__END>:
be: 08 93 \[P1\]=R0;
--- 83,86 ----
Index: gas/testsuite/gas/bfin/flow2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/bfin/flow2.d,v
retrieving revision 1.2
diff -c -p -r1.2 flow2.d
*** gas/testsuite/gas/bfin/flow2.d 24 Oct 2005 18:42:37 -0000 1.2
--- gas/testsuite/gas/bfin/flow2.d 26 Mar 2008 16:31:14 -0000
*************** Disassembly of section .text:
*** 102,114 ****
000000ce <bottom_of_FIR_filter>:
ce: 81 e1 02 00 R1=2 <MY_LABEL1-0x28>\(Z\);
d2: a2 e0 04 10 LSETUP\(d6 <bottom_of_FIR_filter\+0x8>,da <bottom_of_FIR_filter\+0xc>\)LC0=P1;
! d6: e2 e0 04 10 LSETUP\(da <bottom_of_FIR_filter\+0xc>,de <DoItSome__BEGIN>\)LC0=P1>>1;
! da: 82 e0 03 00 LSETUP\(de <DoItSome__BEGIN>,e0 <DoItSome__END>\)LC0;
!
! 000000de <DoItSome__BEGIN>:
de: 08 60 R0=0x1\(x\);
-
- 000000e0 <DoItSome__END>:
e0: 11 60 R1=0x2\(x\);
! e2: 90 e0 00 00 LSETUP\(e2 <DoItSome__END\+0x2>,e2 <DoItSome__END\+0x2>\)LC1;
...
--- 102,110 ----
000000ce <bottom_of_FIR_filter>:
ce: 81 e1 02 00 R1=2 <MY_LABEL1-0x28>\(Z\);
d2: a2 e0 04 10 LSETUP\(d6 <bottom_of_FIR_filter\+0x8>,da <bottom_of_FIR_filter\+0xc>\)LC0=P1;
! d6: e2 e0 04 10 LSETUP\(da <bottom_of_FIR_filter\+0xc>,de <bottom_of_FIR_filter\+0x10>\)LC0=P1>>1;
! da: 82 e0 03 00 LSETUP\(de <bottom_of_FIR_filter\+0x10>,e0 <bottom_of_FIR_filter\+0x12>\)LC0;
de: 08 60 R0=0x1\(x\);
e0: 11 60 R1=0x2\(x\);
! e2: 90 e0 00 00 LSETUP\(e2 <bottom_of_FIR_filter\+0x14>,e2 <bottom_of_FIR_filter\+0x14>\)LC1;
...