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[RFA] PowerPC E500mc support
- From: Edmar Wienskoski <edmar at freescale dot com>
- To: binutils at sourceware dot org
- Date: Thu, 10 Apr 2008 10:09:13 -0500
- Subject: [RFA] PowerPC E500mc support
Freescale would like to contribute this patch to binutils. It implements
new instructions
that will be available on the E500MC
Could some PowerPC maintainer review and commit the patch ?
Thanks
Edmar
bfd/ChangeLog
2008-03-31 Edmar Wienskoski <edmar@freescale.com>
* archures.c: Add bfd_mach_ppc_e500mc.
* bfd-in2.h: Regenerate.
gas/ChangeLog
2008-03-31 Edmar Wienskoski <edmar@freescale.com>
* config/tc-ppc.c (parse_cpu): Handle "e500mc". Extend "e500" to
accept e500mc instructions.
(md_show_usage): Document -me500mc.
gas/testsuite/ChangeLog
2008-03-31 Edmar Wienskoski <edmar@freescale.com>
* gas/ppc/e500mc.s, gas/ppc/e500mc.d: New test.
* gas/ppc/ppc.exp: Run the new test
include/opcode/ChangeLog
2008-03-31 Edmar Wienskoski <edmar@freescale.com>
* ppc.h: (PPC_OPCODE_E500MC): New.
opcodes/ChangeLog
2008-03-31 Edmar Wienskoski <edmar@freescale.com>
* ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
accept Power E500MC instructions.
(print_ppc_disassembler_options): Document -Me500mc.
* ppc-opc.c: (DUIS, DUI, T): New.
(XRT, XRTRA): Likewise.
(E500MC): Likewise.
(powerpc_opcodes): Add new Power E500MC instructions.
diff -rcN binutils-2.18-20080331/bfd/archures.c binutils-2.18-20080331-E500MC/bfd/archures.c
*** binutils-2.18-20080331/bfd/archures.c 2008-02-04 13:15:50.000000000 -0600
--- binutils-2.18-20080331-E500MC/bfd/archures.c 2008-03-31 15:06:31.000000000 -0500
***************
*** 221,226 ****
--- 221,227 ----
.#define bfd_mach_ppc_rs64iii 643
.#define bfd_mach_ppc_7400 7400
.#define bfd_mach_ppc_e500 500
+ .#define bfd_mach_ppc_e500mc 5001
. bfd_arch_rs6000, {* IBM RS/6000 *}
.#define bfd_mach_rs6k 6000
.#define bfd_mach_rs6k_rs1 6001
diff -rcN binutils-2.18-20080331/bfd/bfd-in2.h binutils-2.18-20080331-E500MC/bfd/bfd-in2.h
*** binutils-2.18-20080331/bfd/bfd-in2.h 2008-03-31 14:21:23.000000000 -0500
--- binutils-2.18-20080331-E500MC/bfd/bfd-in2.h 2008-03-31 15:06:31.000000000 -0500
***************
*** 1835,1840 ****
--- 1835,1841 ----
#define bfd_mach_ppc_rs64iii 643
#define bfd_mach_ppc_7400 7400
#define bfd_mach_ppc_e500 500
+ #define bfd_mach_ppc_e500mc 5001
bfd_arch_rs6000, /* IBM RS/6000 */
#define bfd_mach_rs6k 6000
#define bfd_mach_rs6k_rs1 6001
diff -rcN binutils-2.18-20080331/bfd/cpu-powerpc.c binutils-2.18-20080331-E500MC/bfd/cpu-powerpc.c
*** binutils-2.18-20080331/bfd/cpu-powerpc.c 2007-07-03 09:26:40.000000000 -0500
--- binutils-2.18-20080331-E500MC/bfd/cpu-powerpc.c 2008-03-31 15:06:31.000000000 -0500
***************
*** 285,290 ****
--- 285,304 ----
&bfd_powerpc_archs[14]
},
{
+ 32, /* 32 bits in a word */
+ 32, /* 32 bits in an address */
+ 8, /* 8 bits in a byte */
+ bfd_arch_powerpc,
+ bfd_mach_ppc_e500mc,
+ "powerpc",
+ "powerpc:e500mc",
+ 3,
+ FALSE, /* not the default */
+ powerpc_compatible,
+ bfd_default_scan,
+ &bfd_powerpc_archs[15]
+ },
+ {
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
***************
*** 296,302 ****
FALSE, /* not the default */
powerpc_compatible,
bfd_default_scan,
! &bfd_powerpc_archs[15]
},
{
32, /* 32 bits in a word */
--- 310,316 ----
FALSE, /* not the default */
powerpc_compatible,
bfd_default_scan,
! &bfd_powerpc_archs[16]
},
{
32, /* 32 bits in a word */
diff -rcN binutils-2.18-20080331/gas/config/tc-ppc.c binutils-2.18-20080331-E500MC/gas/config/tc-ppc.c
*** binutils-2.18-20080331/gas/config/tc-ppc.c 2008-03-31 14:21:31.000000000 -0500
--- binutils-2.18-20080331-E500MC/gas/config/tc-ppc.c 2008-03-31 15:06:31.000000000 -0500
***************
*** 878,884 ****
ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
! | PPC_OPCODE_RFMCI);
}
else if (strcmp (arg, "spe") == 0)
{
--- 878,890 ----
ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
! | PPC_OPCODE_RFMCI | PPC_OPCODE_E500MC);
! }
! else if (strcmp (arg, "e500mc") == 0)
! {
! ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
! | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
! | PPC_OPCODE_RFMCI | PPC_OPCODE_E500MC);
}
else if (strcmp (arg, "spe") == 0)
{
***************
*** 1135,1140 ****
--- 1141,1147 ----
-maltivec generate code for AltiVec\n\
-me300 generate code for PowerPC e300 family\n\
-me500, -me500x2 generate code for Motorola e500 core complex\n\
+ -me500mc, generate code for Freescale e500mc core complex\n\
-mspe generate code for Motorola SPE instructions\n\
-mregnames Allow symbolic names for registers\n\
-mno-regnames Do not allow symbolic names for registers\n"));
diff -rcN binutils-2.18-20080331/gas/testsuite/gas/ppc/e500mc.d binutils-2.18-20080331-E500MC/gas/testsuite/gas/ppc/e500mc.d
*** binutils-2.18-20080331/gas/testsuite/gas/ppc/e500mc.d 1969-12-31 18:00:00.000000000 -0600
--- binutils-2.18-20080331-E500MC/gas/testsuite/gas/ppc/e500mc.d 2008-03-31 16:58:24.000000000 -0500
***************
*** 0 ****
--- 1,51 ----
+ #as: -mppc -me500mc
+ #objdump: -dr -Me500mc
+ #name: Power E500MC tests
+
+ .*: +file format elf(32)?(64)?-powerpc.*
+
+ Disassembly of section \.text:
+
+ 0+0000000 <start>:
+ 0: 4c 00 00 4e rfdi
+ 4: 4c 00 00 cc rfgi
+ 8: 4c 1f f9 8c dnh 0,1023
+ c: 4f e0 01 8c dnh 31,0
+ 10: 7c 09 57 be icbiep r9,r10
+ 14: 7c 00 69 dc msgclr r13
+ 18: 7c 00 71 9c msgsnd r14
+ 1c: 7c 00 00 7c wait
+ 20: 7f 9c e3 78 mdors
+ 24: 7c 00 02 1c ehpriv
+ 28: 7c 18 cb c6 dsn r24,r25
+ 2c: 7c 22 18 be lbepx r1,r2,r3
+ 30: 7c 85 32 3e lhepx r4,r5,r6
+ 34: 7c e8 48 3e lwepx r7,r8,r9
+ 38: 7d 4b 60 3a ldepx r10,r11,r12
+ 3c: 7d ae 7c be lfdepx r13,r14,r15
+ 40: 7e 11 91 be stbepx r16,r17,r18
+ 44: 7e 74 ab 3e sthepx r19,r20,r21
+ 48: 7e d7 c1 3e stwepx r22,r23,r24
+ 4c: 7f 3a d9 3a stdepx r25,r26,r27
+ 50: 7f 9d f5 be stfdepx r28,r29,r30
+ 54: 7c 01 14 06 lbdx r0,r1,r2
+ 58: 7d 8d 74 46 lhdx r12,r13,r14
+ 5c: 7c 64 2c 86 lwdx r3,r4,r5
+ 60: 7f 5b e6 46 lfddx f26,r27,r28
+ 64: 7d f0 8c c6 lddx r15,r16,r17
+ 68: 7c c7 45 06 stbdx r6,r7,r8
+ 6c: 7e 53 a5 46 sthdx r18,r19,r20
+ 70: 7d 2a 5d 86 stwdx r9,r10,r11
+ 74: 7f be ff 46 stfddx f29,r30,r31
+ 78: 7e b6 bd c6 stddx r21,r22,r23
+ 7c: 7c 20 0d ec dcbal r0,r1
+ 80: 7c 26 3f ec dcbzl r6,r7
+ 84: 7c 1f 00 7e dcbstep r31,r0
+ 88: 7c 01 10 fe dcbfep r1,r2
+ 8c: 7c 64 29 fe dcbtstep r3,r4,r5
+ 90: 7c c7 42 7e dcbtep r6,r7,r8
+ 94: 7c 0b 67 fe dcbzep r11,r12
+ 98: 7c 00 06 26 tlbilx 0,0,r0
+ 9c: 7c 20 06 26 tlbilx 1,0,r0
+ a0: 7c 62 1e 26 tlbilx 3,r2,r3
+ a4: 7c 64 2e 26 tlbilx 3,r4,r5
diff -rcN binutils-2.18-20080331/gas/testsuite/gas/ppc/e500mc.s binutils-2.18-20080331-E500MC/gas/testsuite/gas/ppc/e500mc.s
*** binutils-2.18-20080331/gas/testsuite/gas/ppc/e500mc.s 1969-12-31 18:00:00.000000000 -0600
--- binutils-2.18-20080331-E500MC/gas/testsuite/gas/ppc/e500mc.s 2008-03-31 16:06:29.000000000 -0500
***************
*** 0 ****
--- 1,45 ----
+ # Power E500MC tests
+ .section ".text"
+ start:
+ rfdi
+ rfgi
+ dnh 0, 1023
+ dnh 31, 0
+ icbiep 9, 10
+ msgclr 13
+ msgsnd 14
+ wait
+ mdors
+ ehpriv
+ dsn 24, 25
+ lbepx 1, 2, 3
+ lhepx 4, 5, 6
+ lwepx 7, 8, 9
+ ldepx 10, 11, 12
+ lfdepx 13, 14, 15
+ stbepx 16, 17, 18
+ sthepx 19, 20, 21
+ stwepx 22, 23, 24
+ stdepx 25, 26, 27
+ stfdepx 28, 29, 30
+ lbdx 0, 1, 2
+ lhdx 12, 13, 14
+ lwdx 3, 4, 5
+ lfddx 26, 27, 28
+ lddx 15, 16, 17
+ stbdx 6, 7, 8
+ sthdx 18, 19, 20
+ stwdx 9, 10, 11
+ stfddx 29, 30, 31
+ stddx 21, 22, 23
+ dcbal 0, 1
+ dcbzl 6, 7
+ dcbstep 31, 0
+ dcbfep 1, 2
+ dcbtstep 3, 4, 5
+ dcbtep 6, 7, 8
+ dcbzep 11, 12
+ tlbilxlpid
+ tlbilxpid
+ tlbilxva 2, 3
+ tlbilx 3, 4, 5
diff -rcN binutils-2.18-20080331/gas/testsuite/gas/ppc/ppc.exp binutils-2.18-20080331-E500MC/gas/testsuite/gas/ppc/ppc.exp
*** binutils-2.18-20080331/gas/testsuite/gas/ppc/ppc.exp 2008-01-04 08:53:50.000000000 -0600
--- binutils-2.18-20080331-E500MC/gas/testsuite/gas/ppc/ppc.exp 2008-03-31 15:06:31.000000000 -0500
***************
*** 44,48 ****
--- 44,49 ----
run_dump_test "e500"
run_list_test "range" "-a32"
run_dump_test "ppc750ps"
+ run_dump_test "e500mc"
}
}
diff -rcN binutils-2.18-20080331/include/opcode/ppc.h binutils-2.18-20080331-E500MC/include/opcode/ppc.h
*** binutils-2.18-20080331/include/opcode/ppc.h 2007-08-23 19:56:30.000000000 -0500
--- binutils-2.18-20080331-E500MC/include/opcode/ppc.h 2008-03-31 15:06:31.000000000 -0500
***************
*** 149,154 ****
--- 149,157 ----
/* Opcode is supported by CPUs with paired singles support. */
#define PPC_OPCODE_PPCPS 0x10000000
+ /* Opcode is supported by Power E500MC */
+ #define PPC_OPCODE_E500MC 0x20000000
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff -rcN binutils-2.18-20080331/opcodes/ppc-dis.c binutils-2.18-20080331-E500MC/opcodes/ppc-dis.c
*** binutils-2.18-20080331/opcodes/ppc-dis.c 2007-08-23 19:56:30.000000000 -0500
--- binutils-2.18-20080331-E500MC/opcodes/ppc-dis.c 2008-03-31 15:06:31.000000000 -0500
***************
*** 51,56 ****
--- 51,62 ----
else if (info->disassembler_options
&& strstr (info->disassembler_options, "booke") != NULL)
dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
+ else if ((info->mach == bfd_mach_ppc_e500mc)
+ || (info->disassembler_options
+ && strstr (info->disassembler_options, "e500mc") != NULL))
+ dialect |= (PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
+ | PPC_OPCODE_RFMCI | PPC_OPCODE_E500MC);
else if ((info->mach == bfd_mach_ppc_e500)
|| (info->disassembler_options
&& strstr (info->disassembler_options, "e500") != NULL))
***************
*** 58,64 ****
| PPC_OPCODE_SPE | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
! | PPC_OPCODE_RFMCI);
else if (info->disassembler_options
&& strstr (info->disassembler_options, "efs") != NULL)
dialect |= PPC_OPCODE_EFS;
--- 64,70 ----
| PPC_OPCODE_SPE | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
! | PPC_OPCODE_RFMCI | PPC_OPCODE_E500MC);
else if (info->disassembler_options
&& strstr (info->disassembler_options, "efs") != NULL)
dialect |= PPC_OPCODE_EFS;
***************
*** 366,371 ****
--- 372,378 ----
fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n");
fprintf (stream, " e300 Disassemble the e300 instructions\n");
fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n");
+ fprintf (stream, " e500mc Disassemble the e500mc instructions\n");
fprintf (stream, " 440 Disassemble the 440 instructions\n");
fprintf (stream, " efs Disassemble the EFS instructions\n");
fprintf (stream, " ppcps Disassemble the PowerPC paired singles instructions\n");
diff -rcN binutils-2.18-20080331/opcodes/ppc-opc.c binutils-2.18-20080331-E500MC/opcodes/ppc-opc.c
*** binutils-2.18-20080331/opcodes/ppc-opc.c 2008-03-31 14:21:37.000000000 -0500
--- binutils-2.18-20080331-E500MC/opcodes/ppc-opc.c 2008-04-02 10:00:25.000000000 -0500
***************
*** 237,245 ****
{ 0xfffc, 0, NULL, NULL,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
/* The E field in a wrteei instruction. */
/* And the W bit in the pair singles instructions. */
! #define E DS + 1
#define PSW E
{ 0x1, 15, NULL, NULL, 0 },
--- 237,249 ----
{ 0xfffc, 0, NULL, NULL,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
+ /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
+ #define DUIS DS + 1
+ { 0x3ff, 11, NULL, NULL, 0 },
+
/* The E field in a wrteei instruction. */
/* And the W bit in the pair singles instructions. */
! #define E DUIS + 1
#define PSW E
{ 0x1, 15, NULL, NULL, 0 },
***************
*** 455,460 ****
--- 459,466 ----
/* The STRM field in an X AltiVec form instruction. */
#define STRM SR + 1
+ /* The T field in a tlbilx form instruction. */
+ #define T STRM
{ 0x3, 21, NULL, NULL, 0 },
/* The SV field in a POWER SC form instruction. */
***************
*** 468,473 ****
--- 474,480 ----
/* The TO field in a D or X form instruction. */
#define TO TBR + 1
+ #define DUI TO
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
***************
*** 1455,1460 ****
--- 1462,1476 ----
/* An X form instruction with the L bit specified. */
#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
+ /* An X form instruction with RT fields specified */
+ #define XRT(op, xop, rt) (X ((op), (xop)) \
+ | ((((unsigned long)(rt)) & 0x1f) << 21))
+
+ /* An X form instruction with RT and RA fields specified */
+ #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
+ | ((((unsigned long)(rt)) & 0x1f) << 21) \
+ | ((((unsigned long)(ra)) & 0x1f) << 16))
+
/* The mask for an X form comparison instruction. */
#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
***************
*** 1677,1682 ****
--- 1693,1699 ----
#define PPCCHLK PPC_OPCODE_CACHELCK
#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
#define PPCRFMCI PPC_OPCODE_RFMCI
+ #define E500MC PPC_OPCODE_E500MC
/* The opcode table.
***************
*** 2863,2873 ****
--- 2880,2893 ----
{"crnor", XL(19,33), XL_MASK, COM, {BT, BA, BB}},
{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, {0}},
+ {"rfdi", XL(19,39), 0xffffffff, E500MC, {0}},
{"rfi", XL(19,50), 0xffffffff, COM, {0}},
{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE, {0}},
{"rfsvc", XL(19,82), 0xffffffff, POWER, {0}},
+ {"rfgi", XL(19,102), 0xffffffff, E500MC, {0}},
+
{"crandc", XL(19,129), XL_MASK, COM, {BT, BA, BB}},
{"isync", XL(19,150), 0xffffffff, PPCCOM, {0}},
***************
*** 2876,2881 ****
--- 2896,2903 ----
{"crclr", XL(19,193), XL_MASK, PPCCOM, {BT, BAT, BBA}},
{"crxor", XL(19,193), XL_MASK, COM, {BT, BA, BB}},
+ {"dnh", X(19,198), X_MASK, E500MC, {DUI, DUIS}},
+
{"crnand", XL(19,225), XL_MASK, COM, {BT, BA, BB}},
{"crand", XL(19,257), XL_MASK, COM, {BT, BA, BB}},
***************
*** 3218,3226 ****
--- 3240,3251 ----
{"maskg", XRC(31,29,0), X_MASK, M601, {RA, RS, RB}},
{"maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}},
+ {"ldepx", X(31,29), X_MASK, E500MC, {RT, RA, RB}},
+
{"icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}},
{"lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}},
+ {"lwepx", X(31,31), X_MASK, E500MC, {RT, RA, RB}},
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}},
{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, {OBF, RA, RB}},
***************
*** 3258,3265 ****
--- 3283,3294 ----
{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}},
+ {"wait", X(31,62), 0xffffffff, E500MC, {0}},
+
{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}},
+ {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, {RA, RB}},
+
{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}},
{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, {RA, RB}},
{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, {RA, RB}},
***************
*** 3299,3304 ****
--- 3328,3334 ----
{"dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}},
{"lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}},
+ {"lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}},
{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}},
***************
*** 3325,3330 ****
--- 3355,3362 ----
{"lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}},
+ {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, {RA, RB}},
+
{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}},
{"dcbtstls", X(31,134), X_MASK, PPCCHLK, {CT, RA, RB}},
***************
*** 3364,3372 ****
--- 3396,3407 ----
{"prtyw", X(31,154), XRB_MASK, POWER6, {RA, RS}},
+ {"stdepx", X(31,157), X_MASK, E500MC, {RS, RA, RB}},
+
{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}},
{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}},
+ {"stwepx", X(31,159), X_MASK, E500MC, {RS, RA, RB}},
{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}},
***************
*** 3402,3407 ****
--- 3437,3444 ----
{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, {RT, RA}},
{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, {RT, RA}},
+ {"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, {RB}},
+
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, {SR, RS}},
{"stdcx.", XRC(31,214,1), X_MASK, PPC64, {RS, RA0, RB}},
***************
*** 3415,3420 ****
--- 3452,3458 ----
{"sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}},
{"stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}},
+ {"stbepx", X(31,223), X_MASK, E500MC, {RS, RA, RB}},
{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}},
***************
*** 3438,3443 ****
--- 3476,3482 ----
{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
+ {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, {RB}},
{"icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}},
***************
*** 3453,3458 ****
--- 3492,3499 ----
{"stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}},
+ {"dcbtstep", XRT(31,255,0), X_MASK, E500MC, {RT, RA, RB}},
+
{"mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}},
{"icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}},
***************
*** 3465,3470 ****
--- 3506,3513 ----
{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
+ {"ehpriv", X(31,270), 0xffffffff, E500MC, {0}},
+
{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, {RB, L}},
{"mfapidi", X(31,275), X_MASK, BOOKE, {RT, RA}},
***************
*** 3482,3487 ****
--- 3525,3531 ----
{"dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}},
{"lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}},
+ {"lhepx", X(31,287), X_MASK, E500MC, {RT, RA, RB}},
{"tlbie", X(31,306), XRTLRA_MASK, PPC, {RB, L}},
{"tlbi", X(31,306), XRT_MASK, POWER, {RA0, RB}},
***************
*** 3495,3500 ****
--- 3539,3546 ----
{"lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}},
+ {"dcbtep", XRT(31,319,0), X_MASK, E500MC, {RT, RA, RB}},
+
{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}},
{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, {RT}},
{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, {RT}},
***************
*** 3770,3775 ****
--- 3816,3822 ----
{"orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}},
{"sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}},
+ {"sthepx", X(31,415), X_MASK, E500MC, {RS, RA, RB}},
{"slbie", X(31,434), XRTRA_MASK, PPC64, {RB}},
***************
*** 3777,3782 ****
--- 3824,3831 ----
{"sthux", X(31,439), X_MASK, COM, {RS, RAS, RB}},
+ {"mdors", 0x7f9ce378, 0xffffffff, E500MC, {0}},
+
{"mr", XRC(31,444,0), X_MASK, COM, {RA, RS, RBS}},
{"or", XRC(31,444,0), X_MASK, COM, {RA, RS, RB}},
{"mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}},
***************
*** 3995,4000 ****
--- 4044,4051 ----
{"dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}},
+ {"dsn", X(31,483), XRT_MASK, E500MC, {RA, RB}},
+
{"dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}},
{"icbtls", X(31,486), X_MASK, PPCCHLK, {CT, RA, RB}},
***************
*** 4025,4030 ****
--- 4076,4083 ----
{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}},
+ {"lbdx", X(31,515), X_MASK, E500MC, {RT, RA, RB}},
+
{"bblels", X(31,518), X_MASK, PPCBRLK, {0}},
{"lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}},
***************
*** 4073,4078 ****
--- 4126,4133 ----
{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}},
+ {"lhdx", X(31,547), X_MASK, E500MC, {RT, RA, RB}},
+
{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}},
{"lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}},
***************
*** 4088,4093 ****
--- 4143,4150 ----
{"lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}},
+ {"lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}},
+
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, {RT, SR}},
{"lswi", X(31,597), X_MASK, PPCCOM, {RT, RA0, NB}},
***************
*** 4102,4109 ****
--- 4159,4169 ----
{"lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}},
{"lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}},
+ {"lfdepx", X(31,607), X_MASK, E500MC, {RT, RA, RB}},
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}},
+ {"lddx", X(31,611), X_MASK, E500MC, {RT, RA, RB}},
+
{"nego", XO(31,104,1,0), XORB_MASK, COM, {RT, RA}},
{"nego.", XO(31,104,1,1), XORB_MASK, COM, {RT, RA}},
***************
*** 4118,4123 ****
--- 4178,4185 ----
{"lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}},
+ {"stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}},
+
{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}},
{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
***************
*** 4152,4157 ****
--- 4214,4221 ----
{"stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}},
+ {"sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}},
+
{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}},
{"stfsux", X(31,695), X_MASK, COM, {FRS, RAS, RB}},
***************
*** 4161,4166 ****
--- 4225,4232 ----
{"stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}},
+ {"stwdx", X(31,707), X_MASK, E500MC, {RS, RA, RB}},
+
{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, {RT, RA}},
{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, {RT, RA}},
{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, {RT, RA}},
***************
*** 4183,4190 ****
--- 4249,4259 ----
{"sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}},
{"stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}},
+ {"stfdepx", X(31,735), X_MASK, E500MC, {RS, RA, RB}},
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}},
+ {"stddx", X(31,739), X_MASK, E500MC, {RS, RA, RB}},
+
{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, {RT, RA}},
{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, {RT, RA}},
{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, {RT, RA}},
***************
*** 4204,4209 ****
--- 4273,4279 ----
{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, {RA, RB}},
+ {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, {RA, RB}},
{"stfdux", X(31,759), X_MASK, COM, {FRS, RAS, RB}},
***************
*** 4226,4231 ****
--- 4296,4305 ----
{"tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}},
{"tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}},
+ {"tlbilx", X(31,787), X_MASK, E500MC, {T, RA0, RB}},
+ {"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, {0}},
+ {"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, {0}},
+ {"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, {RA0, RB}},
{"lwzcix", X(31,789), X_MASK, POWER6, {RT, RA0, RB}},
***************
*** 4246,4251 ****
--- 4320,4327 ----
{"ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}},
+ {"lfddx", X(31,803), X_MASK, E500MC, {FRT, RA, RB}},
+
{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}},
{"rac", X(31,818), X_MASK, PWRCOM, {RT, RA, RB}},
***************
*** 4320,4325 ****
--- 4396,4403 ----
{"stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}},
+ {"stfddx", X(31,931), X_MASK, E500MC, {FRS, RA, RB}},
+
{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}},
{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, {RT, RA}},
***************
*** 4367,4372 ****
--- 4445,4452 ----
{"icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}},
{"stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}},
+ {"icbiep", XRT(31,991,0), XRT_MASK, E500MC, {RA, RB}},
+
{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}},
{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}},
***************
*** 4389,4396 ****
--- 4469,4478 ----
{"dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
{"dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}},
+ {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, {RA, RB}},
{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}},
+ {"dcbzl", XOPL(31,1014,1), XRT_MASK, NOPOWER4|E500MC,{RA, RB}},
{"cctpl", 0x7c210b78, 0xffffffff, CELL, {0}},
{"cctpm", 0x7c421378, 0xffffffff, CELL, {0}},