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Re: Ping version 2 of the MIPS soft-float patch
Thanks for the review, Eric!
Eric Christopher writes:
> I'd been waiting for Richard to comment since he had last time, but...
Sorry I didn't mean to be impatient ;).
> Couple of comments:
>
> Can you comment this struct with the field locations please?
> static struct mips_set_options mips_opts = {
> - ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, ATREG, 0, 0, 0, 0, 0, 0,
> CPU_UNKNOWN, FALSE
> + ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, ATREG, 0, 0, 0, 0, 0, 0,
> + CPU_UNKNOWN, FALSE, FALSE, FALSE };
>
> and the general flow here, i.e. what's going on. It's fairly obvious
> but a comment would be nice.
> + if (mo->pinfo == INSN_MACRO)
>
> Otherwise OK.
Here is what I've checked in after retesting. Thanks again.
Adam
include/opcode/
2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
* mips.h (INSN_MACRO): Move it up to the the pinfo macros.
(INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
opcodes/
2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
* mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
gas/
2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
gas/testsuite/
2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
* gas/mips/mips4.s: Split out fp instruction from here ...
* gas/mips/mips4-fp.s: ... to here.
* gas/mips/mips4.d: Update.
* gas/mips/mips4-fp.l: New file. Check error messages with
-msoft-float.
* gas/mips/mips4-fp.d: New file. Check disassembly with
hard-float.
* gas/mips/mips32r2.s: Split out fp instructions from here ...
* gas/mips/mips32r2-fp32.s: ... to here.
* gas/mips/mips32r2.d: Update.
* gas/mips/mips32r2-fp32.l: New file. Check error messages with
-msoft-float.
* gas/mips/mips32r2-fp32.d: New file. Check disassembly with
hard-float.
* gas/mips/mips32r2-ill-nofp.s, gas/mips/mips32r2-ill-nofp.l: New
test derived from mips32r2-ill.
* gas/mips/mips32-sf32.l: New list test for mips32-sf32.s to check
error messages for soft-float targets.
* gas/mips/mips-macro-ill-sfp.s, gas/mips/mips-macro-ill-sfp.l:
New test for -msingle-float.
* gas/mips/mips-macro-ill-nofp.s, gas/mips/mips-macro-ill-nofp.l:
New test for -msoft-float.
* gas/mips/mips-hard-float-flag.s,
gas/mips/mips-hard-float-flag.l: New test for -mhard-float.
* gas/mips/mips-double-float-flag.s,
gas/mips/mips-double-float-flag.l: New test for -mdouble-float.
* gas/mips/mips.exp: Run new mips4-fp and mips32r2-fp dump tests.
Run mips4-fp and mips32r2-fp list tests with -msoft-float. Run
new mips32r2-ill-nofp with -msoft-float. Run new mips32-sf32 list
test with -msoft-float. Run new mips-macro-ill-sfp test with
-msingle-float. Run new mips-macro-ill-nofp test with
-msoft-float. Run new mips-hard-float-flag and
mips-double-float-flag tests.
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.56
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.56 mips.h
--- include/opcode/mips.h 4 Feb 2008 19:25:05 -0000 1.56
+++ include/opcode/mips.h 28 Apr 2008 16:41:47 -0000
@@ -456,6 +456,9 @@ #define FP_D 0x20000000
#define INSN_MULT 0x40000000
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
+/* Instruction is actually a macro. It should be ignored by the
+ disassembler, and requires special treatment by the assembler. */
+#define INSN_MACRO 0xffffffff
/* These are the bits which may be set in the pinfo2 field of an
instruction. */
@@ -466,10 +469,14 @@ #define INSN2_ALIAS 0x00000001
#define INSN2_READ_MDMX_ACC 0x00000002
/* Instruction writes MDMX accumulator. */
#define INSN2_WRITE_MDMX_ACC 0x00000004
-
-/* Instruction is actually a macro. It should be ignored by the
- disassembler, and requires special treatment by the assembler. */
-#define INSN_MACRO 0xffffffff
+/* Macro uses single-precision floating-point instructions. This should
+ only be set for macros. For instructions, FP_S in pinfo carries the
+ same information. */
+#define INSN2_M_FP_S 0x00000008
+/* Macro uses double-precision floating-point instructions. This should
+ only be set for macros. For instructions, FP_D in pinfo carries the
+ same information. */
+#define INSN2_M_FP_D 0x00000010
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.65
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.65 mips-opc.c
--- opcodes/mips-opc.c 4 Feb 2008 19:26:11 -0000 1.65
+++ opcodes/mips-opc.c 28 Apr 2008 16:41:51 -0000
@@ -184,7 +184,7 @@ const struct mips_opcode mips_builtin_op
instruction name anyhow. */
/* name, args, match, mask, pinfo, pinfo2, membership */
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32|G3 },
-{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4_33 },
+{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I4_33 },
{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */
{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */
@@ -733,11 +733,11 @@ const struct mips_opcode mips_builtin_op
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
-{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
-{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
+{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
+{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
+{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
@@ -752,10 +752,10 @@ const struct mips_opcode mips_builtin_op
{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
/* li is at the start of the table. */
-{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 },
-{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 },
-{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 },
-{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 },
+{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1 },
{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 },
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 },
{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
@@ -768,10 +768,10 @@ const struct mips_opcode mips_builtin_op
{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
-{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
-{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
+{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
-{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
+{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
@@ -1151,15 +1151,15 @@ const struct mips_opcode mips_builtin_op
{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
-{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
-{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
+{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
+{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
-{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
-{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
+{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
@@ -1275,10 +1275,10 @@ const struct mips_opcode mips_builtin_op
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
-{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
-{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
+{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
-{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
+{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
@@ -1337,10 +1337,10 @@ const struct mips_opcode mips_builtin_op
{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
-{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 },
+{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, INSN2_M_FP_S|INSN2_M_FP_D, I1 },
{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
-{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 },
+{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1 },
{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
@@ -1927,11 +1927,11 @@ const struct mips_opcode mips_builtin_op
user to put in nops as necessary. These are at the end so that the
disassembler recognizes more specific versions first. */
{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 },
-{"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 },
+{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 },
{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 },
{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 },
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
-{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 },
+{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 },
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }
};
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.382
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.382 tc-mips.c
--- gas/config/tc-mips.c 4 Feb 2008 19:20:16 -0000 1.382
+++ gas/config/tc-mips.c 28 Apr 2008 16:42:02 -0000
@@ -235,21 +235,41 @@ struct mips_set_options
int arch;
/* True if ".set sym32" is in effect. */
bfd_boolean sym32;
+ /* True if floating-point operations are not allowed. Changed by .set
+ softfloat or .set hardfloat, by command line options -msoft-float or
+ -mhard-float. The default is false. */
+ bfd_boolean soft_float;
+
+ /* True if only single-precision floating-point operations are allowed.
+ Changed by .set singlefloat or .set doublefloat, command-line options
+ -msingle-float or -mdouble-float. The default is false. */
+ bfd_boolean single_float;
};
+/* This is the struct we use to hold the current set of options. Note
+ that we must set the isa field to ISA_UNKNOWN and the ASE fields to
+ -1 to indicate that they have not been initialized. */
+
/* True if -mgp32 was passed. */
static int file_mips_gp32 = -1;
/* True if -mfp32 was passed. */
static int file_mips_fp32 = -1;
-/* This is the struct we use to hold the current set of options. Note
- that we must set the isa field to ISA_UNKNOWN and the ASE fields to
- -1 to indicate that they have not been initialized. */
+/* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
+static int file_mips_soft_float = 0;
+
+/* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
+static int file_mips_single_float = 0;
static struct mips_set_options mips_opts =
{
- ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, ATREG, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
+ /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
+ /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
+ /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
+ /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
+ /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
+ /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
};
/* These variables are filled in with the masks of registers used.
@@ -1750,6 +1770,71 @@ reg_lookup (char **s, unsigned int types
return reg >= 0;
}
+/* Return TRUE if opcode MO is valid on the currently selected ISA and
+ architecture. If EXPANSIONP is TRUE then this check is done while
+ expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
+
+static bfd_boolean
+is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp)
+{
+ int isa = mips_opts.isa;
+ int fp_s, fp_d;
+
+ if (mips_opts.ase_mdmx)
+ isa |= INSN_MDMX;
+ if (mips_opts.ase_dsp)
+ isa |= INSN_DSP;
+ if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
+ isa |= INSN_DSP64;
+ if (mips_opts.ase_dspr2)
+ isa |= INSN_DSPR2;
+ if (mips_opts.ase_mt)
+ isa |= INSN_MT;
+ if (mips_opts.ase_mips3d)
+ isa |= INSN_MIPS3D;
+ if (mips_opts.ase_smartmips)
+ isa |= INSN_SMARTMIPS;
+
+ /* For user code we don't check for mips_opts.mips16 since we want
+ to allow jalx if -mips16 was specified on the command line. */
+ if (expansionp ? mips_opts.mips16 : file_ase_mips16)
+ isa |= INSN_MIPS16;
+
+ if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
+ return FALSE;
+
+ /* Check whether the instruction or macro requires single-precision or
+ double-precision floating-point support. Note that this information is
+ stored differently in the opcode table for insns and macros. */
+ if (mo->pinfo == INSN_MACRO)
+ {
+ fp_s = mo->pinfo2 & INSN2_M_FP_S;
+ fp_d = mo->pinfo2 & INSN2_M_FP_D;
+ }
+ else
+ {
+ fp_s = mo->pinfo & FP_S;
+ fp_d = mo->pinfo & FP_D;
+ }
+
+ if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
+ return FALSE;
+
+ if (fp_s && mips_opts.soft_float)
+ return FALSE;
+
+ return TRUE;
+}
+
+/* Return TRUE if the MIPS16 opcode MO is valid on the currently
+ selected ISA and architecture. */
+
+static bfd_boolean
+is_opcode_valid_16 (const struct mips_opcode *mo)
+{
+ return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
+}
+
/* This function is called once, at assembler startup time. It should set up
all the tables, etc. that the MD part of the assembler will need. */
@@ -3367,16 +3452,7 @@ macro_build (expressionS *ep, const char
macros will never generate MDMX, MIPS-3D, or MT instructions. */
if (strcmp (fmt, mo->args) == 0
&& mo->pinfo != INSN_MACRO
- && OPCODE_IS_MEMBER (mo,
- (mips_opts.isa
- | (mips_opts.mips16 ? INSN_MIPS16 : 0)
- | (mips_opts.ase_dsp ? INSN_DSP : 0)
- | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
- ? INSN_DSP64 : 0)
- | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
- | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
- mips_opts.arch)
- && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0))
+ && is_opcode_valid (mo, TRUE))
break;
++mo;
@@ -6120,11 +6196,6 @@ macro (struct mips_cl_insn *ip)
lr = 1;
goto ld;
case M_LDC1_AB:
- if (mips_opts.arch == CPU_R4650)
- {
- as_bad (_("opcode not supported on this processor"));
- break;
- }
s = "ldc1";
/* Itbl support may require additional care here. */
coproc = 1;
@@ -6211,11 +6282,6 @@ macro (struct mips_cl_insn *ip)
s = "cache";
goto st;
case M_SDC1_AB:
- if (mips_opts.arch == CPU_R4650)
- {
- as_bad (_("opcode not supported on this processor"));
- break;
- }
s = "sdc1";
coproc = 1;
/* Itbl support may require additional care here. */
@@ -6757,11 +6823,6 @@ macro (struct mips_cl_insn *ip)
}
case M_L_DOB:
- if (mips_opts.arch == CPU_R4650)
- {
- as_bad (_("opcode not supported on this processor"));
- break;
- }
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when loading from memory. */
r = BFD_RELOC_LO16;
@@ -6788,11 +6849,6 @@ macro (struct mips_cl_insn *ip)
* But, the resulting address is the same after relocation so why
* generate the extra instruction?
*/
- if (mips_opts.arch == CPU_R4650)
- {
- as_bad (_("opcode not supported on this processor"));
- break;
- }
/* Itbl support may require additional care here. */
coproc = 1;
if (mips_opts.isa != ISA_MIPS1)
@@ -6806,12 +6862,6 @@ macro (struct mips_cl_insn *ip)
goto ldd_std;
case M_S_DAB:
- if (mips_opts.arch == CPU_R4650)
- {
- as_bad (_("opcode not supported on this processor"));
- break;
- }
-
if (mips_opts.isa != ISA_MIPS1)
{
s = "sdc1";
@@ -7456,11 +7506,6 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_S_DOB:
- if (mips_opts.arch == CPU_R4650)
- {
- as_bad (_("opcode not supported on this processor"));
- break;
- }
assert (mips_opts.isa == ISA_MIPS1);
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when storing to memory. */
@@ -8452,31 +8497,7 @@ mips_ip (char *str, struct mips_cl_insn
assert (strcmp (insn->name, str) == 0);
- if (OPCODE_IS_MEMBER (insn,
- (mips_opts.isa
- /* We don't check for mips_opts.mips16 here since
- we want to allow jalx if -mips16 was specified
- on the command line. */
- | (file_ase_mips16 ? INSN_MIPS16 : 0)
- | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
- | (mips_opts.ase_dsp ? INSN_DSP : 0)
- | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
- ? INSN_DSP64 : 0)
- | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
- | (mips_opts.ase_mt ? INSN_MT : 0)
- | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
- | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
- mips_opts.arch))
- ok = TRUE;
- else
- ok = FALSE;
-
- if (insn->pinfo != INSN_MACRO)
- {
- if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
- ok = FALSE;
- }
-
+ ok = is_opcode_valid (insn, FALSE);
if (! ok)
{
if (insn + 1 < &mips_opcodes[NUMOPCODES]
@@ -9824,11 +9845,7 @@ mips16_ip (char *str, struct mips_cl_ins
assert (strcmp (insn->name, str) == 0);
- if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch))
- ok = TRUE;
- else
- ok = FALSE;
-
+ ok = is_opcode_valid_16 (insn);
if (! ok)
{
if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
@@ -10957,10 +10974,18 @@ #define OPTION_MSYM32 (OPTION_MISC_BASE
#define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
{"msym32", no_argument, NULL, OPTION_MSYM32},
{"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
-
+#define OPTION_SOFT_FLOAT (OPTION_MISC_BASE + 16)
+#define OPTION_HARD_FLOAT (OPTION_MISC_BASE + 17)
+ {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
+ {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
+#define OPTION_SINGLE_FLOAT (OPTION_MISC_BASE + 18)
+#define OPTION_DOUBLE_FLOAT (OPTION_MISC_BASE + 19)
+ {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
+ {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
+
/* ELF-specific options. */
#ifdef OBJ_ELF
-#define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
+#define OPTION_ELF_BASE (OPTION_MISC_BASE + 20)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
{"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
{"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
@@ -11320,6 +11345,22 @@ md_parse_option (int c, char *arg)
file_mips_fp32 = 0;
break;
+ case OPTION_SINGLE_FLOAT:
+ file_mips_single_float = 1;
+ break;
+
+ case OPTION_DOUBLE_FLOAT:
+ file_mips_single_float = 0;
+ break;
+
+ case OPTION_SOFT_FLOAT:
+ file_mips_soft_float = 1;
+ break;
+
+ case OPTION_HARD_FLOAT:
+ file_mips_soft_float = 0;
+ break;
+
#ifdef OBJ_ELF
case OPTION_MABI:
if (!IS_ELF)
@@ -11597,6 +11638,8 @@ mips_after_parse_args (void)
file_ase_mt = mips_opts.ase_mt;
mips_opts.gp32 = file_mips_gp32;
mips_opts.fp32 = file_mips_fp32;
+ mips_opts.soft_float = file_mips_soft_float;
+ mips_opts.single_float = file_mips_single_float;
if (mips_flag_mdebug < 0)
{
@@ -12473,6 +12516,14 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
mips_cpu_info_from_isa (mips_opts.isa)->name);
mips_opts.fp32 = 0;
}
+ else if (strcmp (name, "softfloat") == 0)
+ mips_opts.soft_float = 1;
+ else if (strcmp (name, "hardfloat") == 0)
+ mips_opts.soft_float = 0;
+ else if (strcmp (name, "singlefloat") == 0)
+ mips_opts.single_float = 1;
+ else if (strcmp (name, "doublefloat") == 0)
+ mips_opts.single_float = 0;
else if (strcmp (name, "mips16") == 0
|| strcmp (name, "MIPS-16") == 0)
mips_opts.mips16 = 1;
@@ -15094,9 +15145,15 @@ MIPS options:\n\
-msym32 assume all symbols have 32-bit values\n\
-O0 remove unneeded NOPs, do not swap branches\n\
-O remove unneeded NOPs and swap branches\n\
---[no-]construct-floats [dis]allow floating point values to be constructed\n\
--trap, --no-break trap exception on div by 0 and mult overflow\n\
--break, --no-trap break exception on div by 0 and mult overflow\n"));
+ fprintf (stream, _("\
+-mhard-float allow floating-point instructions\n\
+-msoft-float do not allow floating-point instructions\n\
+-msingle-float only allow 32-bit floating-point operations\n\
+-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
+--[no-]construct-floats [dis]allow floating point values to be constructed\n"
+ ));
#ifdef OBJ_ELF
fprintf (stream, _("\
-KPIC, -call_shared generate SVR4 position independent code\n\
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.44
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.44 c-mips.texi
--- gas/doc/c-mips.texi 29 Nov 2007 12:23:44 -0000 1.44
+++ gas/doc/c-mips.texi 28 Apr 2008 16:42:02 -0000
@@ -32,6 +32,7 @@ Assembly Language Programming'' in the s
* MIPS option stack:: Directives to save and restore options
* MIPS ASE instruction generation overrides:: Directives to control
generation of MIPS ASE instructions
+* MIPS floating-point:: Directives to override floating-point options
@end menu
@node MIPS Opts
@@ -272,7 +273,8 @@ 25kf,
sb1,
sb1a,
loongson2e,
-loongson2f
+loongson2f,
+octeon
@end quotation
For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
@@ -301,10 +303,21 @@ other assemblers, which use it to turn o
@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
@sc{gnu} assembler itself never runs the C preprocessor.
+@item -msoft-float
+@itemx -mhard-float
+Disable or enable floating-point instructions. Note that by default
+floating-point instructions are always allowed even with CPU targets
+that don't have support for these instructions.
+
+@item -msingle-float
+@itemx -mdouble-float
+Disable or enable double-precision floating-point operations. Note
+that by default double-precision floating-point operations are always
+allowed even with CPU targets that don't have support for these
+operations.
+
@item --construct-floats
@itemx --no-construct-floats
-@cindex --construct-floats
-@cindex --no-construct-floats
The @code{--no-construct-floats} option disables the construction of
double width floating point constants by loading the two halves of the
value into the two single width floating point registers that make up
@@ -579,3 +592,26 @@ in the assembly. The @code{.set nomt} d
instructions from being accepted.
Traditional @sc{mips} assemblers do not support these directives.
+
+@node MIPS floating-point
+@section Directives to override floating-point options
+
+@cindex Disable floating-point instructions
+@kindex @code{.set softfloat}
+@kindex @code{.set hardfloat}
+The directives @code{.set softfloat} and @code{.set hardfloat} provide
+finer control of disabling and enabling float-point instructions.
+These directives always override the default (that hard-float
+instructions are accepted) or the command-line options
+(@samp{-msoft-float} and @samp{-mhard-float}).
+
+@cindex Disable single-precision floating-point operations
+@kindex @code{.set softfloat}
+@kindex @code{.set hardfloat}
+The directives @code{.set singlefloat} and @code{.set doublefloat}
+provide finer control of disabling and enabling double-precision
+float-point operations. These directives always override the default
+(that double-precision operations are accepted) or the command-line
+options (@samp{-msingle-float} and @samp{-mdouble-float}).
+
+Traditional @sc{mips} assemblers do not support these directives.
Index: gas/testsuite/gas/mips/mips4.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips4.s,v
retrieving revision 1.3
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.3 mips4.s
--- gas/testsuite/gas/mips/mips4.s 18 Jul 2006 14:06:10 -0000 1.3
+++ gas/testsuite/gas/mips/mips4.s 28 Apr 2008 16:42:02 -0000
@@ -1,45 +1,10 @@
-# Source file used to test -mips4 instructions.
+# Source file used to test -mips4 *non-fp* instructions.
text_label:
- bc1f text_label
- bc1f $fcc1,text_label
- bc1fl $fcc1,text_label
- bc1t $fcc1,text_label
- bc1tl $fcc2,text_label
- c.f.d $f4,$f6
- c.f.d $fcc1,$f4,$f6
- ldxc1 $f2,$4($5)
- lwxc1 $f2,$4($5)
- madd.d $f0,$f2,$f4,$f6
- # This choice of arguments is so that it matches bc3f on pre-mips4.
- madd.s $f10,$f8,$f2,$f0
- movf $4,$5,$fcc4
- movf.d $f4,$f6,$fcc0
- movf.s $f4,$f6,$fcc0
movn $4,$6,$6
- movn.d $f4,$f6,$6
- movn.s $f4,$f6,$6
- movt $4,$5,$fcc4
- movt.d $f4,$f6,$fcc0
- movt.s $f4,$f6,$fcc0
movz $4,$6,$6
- movz.d $f4,$f6,$6
- movz.s $f4,$f6,$6
- msub.d $f0,$f2,$f4,$f6
- msub.s $f0,$f2,$f4,$f6
- nmadd.d $f0,$f2,$f4,$f6
- nmadd.s $f0,$f2,$f4,$f6
- nmsub.d $f0,$f2,$f4,$f6
- nmsub.s $f0,$f2,$f4,$f6
# It used to be disabled due to a clash with lwc3.
pref 4,0($4)
- prefx 4,$4($5)
- recip.d $f4,$f6
- recip.s $f4,$f6
- rsqrt.d $f4,$f6
- rsqrt.s $f4,$f6
- sdxc1 $f4,$4($5)
- swxc1 $f4,$4($5)
# Round to a 16 byte boundary, for ease in testing multiple targets.
nop
Index: gas/testsuite/gas/mips/mips4.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips4.d,v
retrieving revision 1.6
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.6 mips4.d
--- gas/testsuite/gas/mips/mips4.d 18 Jul 2006 14:06:10 -0000 1.6
+++ gas/testsuite/gas/mips/mips4.d 28 Apr 2008 16:42:02 -0000
@@ -1,51 +1,12 @@
#objdump: -dr --prefix-addresses
-#name: MIPS mips4
+#name: MIPS mips4 non-fp
-# Test the mips4 macros.
+# Test mips4 *non-fp* insturctions.
.*: +file format .*mips.*
Disassembly of section .text:
-0+0000 <[^>]*> bc1f 00000000+ <text_label>
-0+0004 <[^>]*> nop
-0+0008 <[^>]*> bc1f \$fcc1,00000000+ <text_label>
-0+000c <[^>]*> nop
-0+0010 <[^>]*> bc1fl \$fcc1,00000000+ <text_label>
-0+0014 <[^>]*> nop
-0+0018 <[^>]*> bc1t \$fcc1,00000000+ <text_label>
-0+001c <[^>]*> nop
-0+0020 <[^>]*> bc1tl \$fcc2,00000000+ <text_label>
-0+0024 <[^>]*> nop
-0+0028 <[^>]*> c.f.d \$f4,\$f6
-0+002c <[^>]*> c.f.d \$fcc1,\$f4,\$f6
-0+0030 <[^>]*> ldxc1 \$f2,a0\(a1\)
-0+0034 <[^>]*> lwxc1 \$f2,a0\(a1\)
-0+0038 <[^>]*> madd.d \$f0,\$f2,\$f4,\$f6
-0+003c <[^>]*> madd.s \$f10,\$f8,\$f2,\$f0
-0+0040 <[^>]*> movf a0,a1,\$fcc4
-0+0044 <[^>]*> movf.d \$f4,\$f6,\$fcc0
-0+0048 <[^>]*> movf.s \$f4,\$f6,\$fcc0
-0+004c <[^>]*> movn a0,a2,a2
-0+0050 <[^>]*> movn.d \$f4,\$f6,a2
-0+0054 <[^>]*> movn.s \$f4,\$f6,a2
-0+0058 <[^>]*> movt a0,a1,\$fcc4
-0+005c <[^>]*> movt.d \$f4,\$f6,\$fcc0
-0+0060 <[^>]*> movt.s \$f4,\$f6,\$fcc0
-0+0064 <[^>]*> movz a0,a2,a2
-0+0068 <[^>]*> movz.d \$f4,\$f6,a2
-0+006c <[^>]*> movz.s \$f4,\$f6,a2
-0+0070 <[^>]*> msub.d \$f0,\$f2,\$f4,\$f6
-0+0074 <[^>]*> msub.s \$f0,\$f2,\$f4,\$f6
-0+0078 <[^>]*> nmadd.d \$f0,\$f2,\$f4,\$f6
-0+007c <[^>]*> nmadd.s \$f0,\$f2,\$f4,\$f6
-0+0080 <[^>]*> nmsub.d \$f0,\$f2,\$f4,\$f6
-0+0084 <[^>]*> nmsub.s \$f0,\$f2,\$f4,\$f6
-0+0088 <[^>]*> pref 0x4,0\(a0\)
-0+008c <[^>]*> prefx 0x4,a0\(a1\)
-0+0090 <[^>]*> recip.d \$f4,\$f6
-0+0094 <[^>]*> recip.s \$f4,\$f6
-0+0098 <[^>]*> rsqrt.d \$f4,\$f6
-0+009c <[^>]*> rsqrt.s \$f4,\$f6
-0+00a0 <[^>]*> sdxc1 \$f4,a0\(a1\)
-0+00a4 <[^>]*> swxc1 \$f4,a0\(a1\)
+0+0000 <[^>]*> movn a0,a2,a2
+0+0004 <[^>]*> movz a0,a2,a2
+0+0008 <[^>]*> pref 0x4,0\(a0\)
...
Index: gas/testsuite/gas/mips/mips4-fp.s
===================================================================
RCS file: gas/testsuite/gas/mips/mips4-fp.s
diff -N gas/testsuite/gas/mips/mips4-fp.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips4-fp.s 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,44 @@
+# Source file used to test -mips4 fp instructions.
+
+text_label:
+ bc1f text_label
+ bc1f $fcc1,text_label
+ bc1fl $fcc1,text_label
+ bc1t $fcc1,text_label
+ bc1tl $fcc2,text_label
+ c.f.d $f4,$f6
+ c.f.d $fcc1,$f4,$f6
+ ldxc1 $f2,$4($5)
+ lwxc1 $f2,$4($5)
+ madd.d $f0,$f2,$f4,$f6
+ # This choice of arguments is so that it matches bc3f on pre-mips4.
+ madd.s $f10,$f8,$f2,$f0
+ movf $4,$5,$fcc4
+ movf.d $f4,$f6,$fcc0
+ movf.s $f4,$f6,$fcc0
+ movn.d $f4,$f6,$6
+ movn.s $f4,$f6,$6
+ movt $4,$5,$fcc4
+ movt.d $f4,$f6,$fcc0
+ movt.s $f4,$f6,$fcc0
+ movz.d $f4,$f6,$6
+ movz.s $f4,$f6,$6
+ msub.d $f0,$f2,$f4,$f6
+ msub.s $f0,$f2,$f4,$f6
+ nmadd.d $f0,$f2,$f4,$f6
+ nmadd.s $f0,$f2,$f4,$f6
+ nmsub.d $f0,$f2,$f4,$f6
+ nmsub.s $f0,$f2,$f4,$f6
+ # It used to be disabled due to a clash with lwc3.
+ prefx 4,$4($5)
+ recip.d $f4,$f6
+ recip.s $f4,$f6
+ rsqrt.d $f4,$f6
+ rsqrt.s $f4,$f6
+ sdxc1 $f4,$4($5)
+ swxc1 $f4,$4($5)
+
+# Round to a 16 byte boundary, for ease in testing multiple targets.
+ nop
+ nop
+ nop
Index: gas/testsuite/gas/mips/mips4-fp.d
===================================================================
RCS file: gas/testsuite/gas/mips/mips4-fp.d
diff -N gas/testsuite/gas/mips/mips4-fp.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips4-fp.d 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,48 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS mips4 fp
+
+# Test mips4 fp instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> bc1f 00000000+ <text_label>
+0+0004 <[^>]*> nop
+0+0008 <[^>]*> bc1f \$fcc1,00000000+ <text_label>
+0+000c <[^>]*> nop
+0+0010 <[^>]*> bc1fl \$fcc1,00000000+ <text_label>
+0+0014 <[^>]*> nop
+0+0018 <[^>]*> bc1t \$fcc1,00000000+ <text_label>
+0+001c <[^>]*> nop
+0+0020 <[^>]*> bc1tl \$fcc2,00000000+ <text_label>
+0+0024 <[^>]*> nop
+0+0028 <[^>]*> c.f.d \$f4,\$f6
+0+002c <[^>]*> c.f.d \$fcc1,\$f4,\$f6
+0+0030 <[^>]*> ldxc1 \$f2,a0\(a1\)
+0+0034 <[^>]*> lwxc1 \$f2,a0\(a1\)
+0+0038 <[^>]*> madd.d \$f0,\$f2,\$f4,\$f6
+0+003c <[^>]*> madd.s \$f10,\$f8,\$f2,\$f0
+0+0040 <[^>]*> movf a0,a1,\$fcc4
+0+0044 <[^>]*> movf.d \$f4,\$f6,\$fcc0
+0+0048 <[^>]*> movf.s \$f4,\$f6,\$fcc0
+0+004c <[^>]*> movn.d \$f4,\$f6,a2
+0+0050 <[^>]*> movn.s \$f4,\$f6,a2
+0+0054 <[^>]*> movt a0,a1,\$fcc4
+0+0058 <[^>]*> movt.d \$f4,\$f6,\$fcc0
+0+005c <[^>]*> movt.s \$f4,\$f6,\$fcc0
+0+0060 <[^>]*> movz.d \$f4,\$f6,a2
+0+0064 <[^>]*> movz.s \$f4,\$f6,a2
+0+0068 <[^>]*> msub.d \$f0,\$f2,\$f4,\$f6
+0+006c <[^>]*> msub.s \$f0,\$f2,\$f4,\$f6
+0+0070 <[^>]*> nmadd.d \$f0,\$f2,\$f4,\$f6
+0+0074 <[^>]*> nmadd.s \$f0,\$f2,\$f4,\$f6
+0+0078 <[^>]*> nmsub.d \$f0,\$f2,\$f4,\$f6
+0+007c <[^>]*> nmsub.s \$f0,\$f2,\$f4,\$f6
+0+0080 <[^>]*> prefx 0x4,a0\(a1\)
+0+0084 <[^>]*> recip.d \$f4,\$f6
+0+0088 <[^>]*> recip.s \$f4,\$f6
+0+008c <[^>]*> rsqrt.d \$f4,\$f6
+0+0090 <[^>]*> rsqrt.s \$f4,\$f6
+0+0094 <[^>]*> sdxc1 \$f4,a0\(a1\)
+0+0098 <[^>]*> swxc1 \$f4,a0\(a1\)
+ ...
Index: gas/testsuite/gas/mips/mips4-fp.l
===================================================================
RCS file: gas/testsuite/gas/mips/mips4-fp.l
diff -N gas/testsuite/gas/mips/mips4-fp.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips4-fp.l 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,35 @@
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc1f text_label'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1f \$fcc1,text_label'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1fl \$fcc1,text_label'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `bc1tl \$fcc2,text_label'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f4,\$f6'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f2,\$4\(\$5\)'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f0,\$f2,\$f4,\$f6'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `movf \$4,\$5,\$fcc4'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f4,\$f6,\$6'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f4,\$f6,\$6'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f0,\$f2,\$f4,\$f6'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f0,\$f2,\$f4,\$f6'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f0,\$f2,\$f4,\$f6'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f0,\$f2,\$f4,\$f6'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f0,\$f2,\$f4,\$f6'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f0,\$f2,\$f4,\$f6'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `prefx 4,\$4\(\$5\)'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
+.*:36: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f4,\$4\(\$5\)'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f4,\$4\(\$5\)'
Index: gas/testsuite/gas/mips/mips32r2.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips32r2.s,v
retrieving revision 1.1
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.1 mips32r2.s
--- gas/testsuite/gas/mips/mips32r2.s 31 Dec 2002 07:29:28 -0000 1.1
+++ gas/testsuite/gas/mips/mips32r2.s 28 Apr 2008 16:42:02 -0000
@@ -1,4 +1,4 @@
-# source file to test assembly of mips32r2 instructions
+# source file to test assembly of mips32r2 *non-fp* instructions
.set noreorder
.set noat
@@ -63,15 +63,6 @@ text_label:
wrpgpr $10, $25
- # FPU (cp1) instructions
- #
- # Even registers are supported w/ 32-bit FPU, odd
- # registers supported only for 64-bit FPU.
- # Only the 32-bit FPU instructions are tested here.
-
- mfhc1 $17, $f0
- mthc1 $17, $f0
-
# cp2 instructions
mfhc2 $17, 0x5555
Index: gas/testsuite/gas/mips/mips32r2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips32r2.d,v
retrieving revision 1.3
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.3 mips32r2.d
--- gas/testsuite/gas/mips/mips32r2.d 7 May 2003 05:08:20 -0000 1.3
+++ gas/testsuite/gas/mips/mips32r2.d 28 Apr 2008 16:42:02 -0000
@@ -1,8 +1,8 @@
#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
-#name: MIPS MIPS32r2 instructions
+#name: MIPS MIPS32r2 non-fp instructions
#as: -32
-# Check MIPS32 Release 2 (mips32r2) instruction assembly
+# Check MIPS32 Release 2 (mips32r2) *non-fp* instruction assembly
.*: +file format .*mips.*
@@ -40,8 +40,6 @@ 0+0074 <[^>]*> 41606020 ei
0+0078 <[^>]*> 416a6020 ei \$10
0+007c <[^>]*> 41595000 rdpgpr \$10,\$25
0+0080 <[^>]*> 41d95000 wrpgpr \$10,\$25
-0+0084 <[^>]*> 44710000 mfhc1 \$17,\$f0
-0+0088 <[^>]*> 44f10000 mthc1 \$17,\$f0
-0+008c <[^>]*> 48715555 mfhc2 \$17,0x5555
-0+0090 <[^>]*> 48f15555 mthc2 \$17,0x5555
+0+0084 <[^>]*> 48715555 mfhc2 \$17,0x5555
+0+0088 <[^>]*> 48f15555 mthc2 \$17,0x5555
...
Index: gas/testsuite/gas/mips/mips32r2-fp32.s
===================================================================
RCS file: gas/testsuite/gas/mips/mips32r2-fp32.s
diff -N gas/testsuite/gas/mips/mips32r2-fp32.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips32r2-fp32.s 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,13 @@
+# source file to test assembly of mips32r2 FP instructions
+
+ .text
+text_label:
+
+ # FPU (cp1) instructions
+ #
+ # Even registers are supported w/ 32-bit FPU, odd
+ # registers supported only for 64-bit FPU.
+ # Only the 32-bit FPU instructions are tested here.
+
+ mfhc1 $17, $f0
+ mthc1 $17, $f0
Index: gas/testsuite/gas/mips/mips32r2-fp32.d
===================================================================
RCS file: gas/testsuite/gas/mips/mips32r2-fp32.d
diff -N gas/testsuite/gas/mips/mips32r2-fp32.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips32r2-fp32.d 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,12 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS32r2 fp instructions
+#as: -32
+
+# Check MIPS32 Release 2 (mips32r2) FP instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 44710000 mfhc1 \$17,\$f0
+0+0004 <[^>]*> 44f10000 mthc1 \$17,\$f0
+#pass
Index: gas/testsuite/gas/mips/mips32r2-fp32.l
===================================================================
RCS file: gas/testsuite/gas/mips/mips32r2-fp32.l
diff -N gas/testsuite/gas/mips/mips32r2-fp32.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips32r2-fp32.l 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `mfhc1 \$17,\$f0'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `mthc1 \$17,\$f0'
Index: gas/testsuite/gas/mips/mips32r2-ill-nofp.s
===================================================================
RCS file: gas/testsuite/gas/mips/mips32r2-ill-nofp.s
diff -N gas/testsuite/gas/mips/mips32r2-ill-nofp.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips32r2-ill-nofp.s 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,48 @@
+# source file to test illegal mips32r2 instructions
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+
+ # insert and extract position/size checks:
+
+ # ext constraint: 0 <= pos < 32
+ ext $4, $5, -1, 1 # error
+ ext $4, $5, 0, 1
+ ext $4, $5, 31, 1
+ ext $4, $5, 32, 1 # error
+
+ # ext constraint: 0 < size <= 32
+ ext $4, $5, 0, 0 # error
+ ext $4, $5, 0, 1
+ ext $4, $5, 0, 32
+ ext $4, $5, 0, 33 # error
+
+ # ext constraint: 0 < (pos+size) <= 32
+ ext $4, $5, 0, 0 # error
+ ext $4, $5, 0, 1
+ ext $4, $5, 31, 1
+ ext $4, $5, 31, 2 # error
+
+ # ins constraint: 0 <= pos < 32
+ ins $4, $5, -1, 1 # error
+ ins $4, $5, 0, 1
+ ins $4, $5, 31, 1
+ ins $4, $5, 32, 1 # error
+
+ # ins constraint: 0 < size <= 32
+ ins $4, $5, 0, 0 # error
+ ins $4, $5, 0, 1
+ ins $4, $5, 0, 32
+ ins $4, $5, 0, 33 # error
+
+ # ins constraint: 0 < (pos+size) <= 32
+ ins $4, $5, 0, 0 # error
+ ins $4, $5, 0, 1
+ ins $4, $5, 31, 1
+ ins $4, $5, 31, 2 # error
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/testsuite/gas/mips/mips32r2-ill-nofp.l
===================================================================
RCS file: gas/testsuite/gas/mips/mips32r2-ill-nofp.l
diff -N gas/testsuite/gas/mips/mips32r2-ill-nofp.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips32r2-ill-nofp.l 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*:12: Error: Improper position \([0-9]*\)
+.*:15: Error: Improper position \(32\)
+.*:18: Error: Improper extract size \(0, position 0\)
+.*:21: Error: Improper extract size \(33, position 0\)
+.*:24: Error: Improper extract size \(0, position 0\)
+.*:27: Error: Improper extract size \(2, position 31\)
+.*:30: Error: Improper position \([0-9]*\)
+.*:33: Error: Improper position \(32\)
+.*:36: Error: Improper insert size \(0, position 0\)
+.*:39: Error: Improper insert size \(33, position 0\)
+.*:42: Error: Improper insert size \(0, position 0\)
+.*:45: Error: Improper insert size \(2, position 31\)
Index: gas/testsuite/gas/mips/mips32-sf32.l
===================================================================
RCS file: gas/testsuite/gas/mips/mips32-sf32.l
diff -N gas/testsuite/gas/mips/mips32-sf32.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips32-sf32.l 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f1,1.0'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f3,1.9'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f5,\$f1,\$f3'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.s \$f8,\$f7'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.w \$f8,\$f7'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `cvt.s.d \$f7,\$f8'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f7,\$f8'
Index: gas/testsuite/gas/mips/mips-macro-ill-nofp.s
===================================================================
RCS file: gas/testsuite/gas/mips/mips-macro-ill-nofp.s
diff -N gas/testsuite/gas/mips/mips-macro-ill-nofp.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips-macro-ill-nofp.s 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,32 @@
+# Macros that are disabled without floating point.
+
+ .text
+double_float:
+ ldc1 $f2, d
+ ldc1 $22, d
+ l.d $f2, d
+ li.d $f2, 1.2
+ li.d $22, 1.2
+
+ sdc1 $f2, d
+ sdc1 $22, d
+ s.d $f2, d
+
+ trunc.w.d $f4,$f6,$4
+
+single_float:
+ lwc1 $f2, d
+ lwc1 $22, d
+ l.s $f2, d
+ li.s $f2, 1.2
+ li.s $22, 1.2
+
+ sdc1 $f2, d
+ sdc1 $22, d
+ s.d $f2, d
+
+ trunc.w.s $f4,$f6,$4
+
+d:
+ .word 0
+ .word 0
Index: gas/testsuite/gas/mips/mips-macro-ill-nofp.l
===================================================================
RCS file: gas/testsuite/gas/mips/mips-macro-ill-nofp.l
diff -N gas/testsuite/gas/mips/mips-macro-ill-nofp.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips-macro-ill-nofp.l 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,19 @@
+.*: Assembler messages:
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `lwc1 \$f2,d'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `lwc1 \$22,d'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `l.s \$f2,d'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f2,1.2'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `li.s \$22,1.2'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.s \$f4,\$f6,\$4'
Index: gas/testsuite/gas/mips/mips-macro-ill-sfp.s
===================================================================
RCS file: gas/testsuite/gas/mips/mips-macro-ill-sfp.s
diff -N gas/testsuite/gas/mips/mips-macro-ill-sfp.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips-macro-ill-sfp.s 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,19 @@
+# Macros that are disabled without double-precision fp insns.
+
+ .text
+double_float:
+ ldc1 $f2, d
+ ldc1 $22, d
+ l.d $f2, d
+ li.d $f2, 1.2
+ li.d $22, 1.2
+
+ sdc1 $f2, d
+ sdc1 $22, d
+ s.d $f2, d
+
+ trunc.w.d $f4,$f6,$4
+
+d:
+ .word 0
+ .word 0
Index: gas/testsuite/gas/mips/mips-macro-ill-sfp.l
===================================================================
RCS file: gas/testsuite/gas/mips/mips-macro-ill-sfp.l
diff -N gas/testsuite/gas/mips/mips-macro-ill-sfp.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips-macro-ill-sfp.l 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,10 @@
+.*: Assembler messages:
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
Index: gas/testsuite/gas/mips/mips-double-float-flag.s
===================================================================
RCS file: gas/testsuite/gas/mips/mips-double-float-flag.s
diff -N gas/testsuite/gas/mips/mips-double-float-flag.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips-double-float-flag.s 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,17 @@
+ .text
+foo:
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+
+ .set singlefloat
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+ .set push
+
+ .set doublefloat
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+
+ .set pop
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
Index: gas/testsuite/gas/mips/mips-double-float-flag.l
===================================================================
RCS file: gas/testsuite/gas/mips/mips-double-float-flag.l
diff -N gas/testsuite/gas/mips/mips-double-float-flag.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips-double-float-flag.l 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
Index: gas/testsuite/gas/mips/mips-hard-float-flag.s
===================================================================
RCS file: gas/testsuite/gas/mips/mips-hard-float-flag.s
diff -N gas/testsuite/gas/mips/mips-hard-float-flag.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips-hard-float-flag.s 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,17 @@
+ .text
+foo:
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+
+ .set softfloat
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+ .set push
+
+ .set hardfloat
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+
+ .set pop
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
Index: gas/testsuite/gas/mips/mips-hard-float-flag.l
===================================================================
RCS file: gas/testsuite/gas/mips/mips-hard-float-flag.l
diff -N gas/testsuite/gas/mips/mips-hard-float-flag.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips-hard-float-flag.l 28 Apr 2008 16:42:02 -0000
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.137
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -r1.137 mips.exp
--- gas/testsuite/gas/mips/mips.exp 6 Feb 2008 05:29:03 -0000 1.137
+++ gas/testsuite/gas/mips/mips.exp 28 Apr 2008 16:42:03 -0000
@@ -475,6 +475,9 @@ if { [istarget mips*-*-vxworks*] } {
if $elf { run_dump_test "lif-svr4pic" }
if $elf { run_dump_test "lif-xgot" }
run_dump_test_arches "mips4" [mips_arch_list_matching mips4]
+ run_dump_test_arches "mips4-fp" [mips_arch_list_matching mips4]
+ run_list_test_arches "mips4-fp" "-32 -msoft-float" \
+ [mips_arch_list_matching mips4]
run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
if $ilocks {
run_dump_test "mul-ilocks"
@@ -546,12 +549,20 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "mips32" [mips_arch_list_matching mips32]
run_dump_test_arches "mips32-sf32" [mips_arch_list_matching mips32]
+ run_list_test_arches "mips32-sf32" "-32 -msoft-float" \
+ [mips_arch_list_matching mips32]
run_dump_test_arches "mips32r2" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "mips32r2-fp32" \
+ [mips_arch_list_matching mips32r2]
+ run_list_test_arches "mips32r2-fp32" "-32 -msoft-float" \
+ [mips_arch_list_matching mips32r2]
run_list_test_arches "mips32r2-ill" "-32" \
- [mips_arch_list_matching mips32r2 gpr32]
+ [mips_arch_list_matching mips32r2 gpr32]
run_list_test_arches "mips32r2-ill-fp64" "-mabi=o64" \
- [mips_arch_list_matching mips32r2 gpr64]
+ [mips_arch_list_matching mips32r2 gpr64]
+ run_list_test_arches "mips32r2-ill-nofp" "-32 -msoft-float" \
+ [mips_arch_list_matching mips32r2]
run_dump_test_arches "mips64" [mips_arch_list_matching mips64]
@@ -795,4 +806,16 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "align2"
run_dump_test "align2-el"
run_dump_test "odd-float"
+
+ run_list_test_arches "mips-macro-ill-sfp" "-32 -msingle-float" \
+ [mips_arch_list_matching mips2]
+ run_list_test_arches "mips-macro-ill-nofp" "-32 -msoft-float" \
+ [mips_arch_list_matching mips2]
+
+ run_list_test_arches "mips-hard-float-flag" \
+ "-32 -msoft-float -mhard-float" \
+ [mips_arch_list_matching mips1]
+ run_list_test_arches "mips-double-float-flag" \
+ "-32 -msingle-float -mdouble-float" \
+ [mips_arch_list_matching mips1]
}