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[PATCH, MIPS] Octeon coprocessor 2 instructions
- From: Adam Nemet <anemet at sonic dot net>
- To: binutils at sourceware dot org
- Date: Mon, 2 Jun 2008 23:58:58 -0700
- Subject: [PATCH, MIPS] Octeon coprocessor 2 instructions
This patch adds the supported coprocessor 2 instructions. MIPS
implementations can omit cop2 insns on an instruction-by-instruction basis.
Similarly to soft-float I'd like to diagnose the unsupported variants for
Octeon (only dmfc2 and dmtc2 are implemented). This will hopefully be less
controversial since it does not effect the ABI and the coprocessor interface
is meant to be implementation-specific anyway.
I defined a new negative feature macro NO_ISA_COP in tc-mips.c which if true
for a CPU means that it does not implement all the coprocessor insns the ISA
provides. For such a CPU the coprocessor insns are only accepted if the
membership in the opcode table contains the CPU explicitely.
Coprocessor macros are nicely centralized so I just handle them in macro()
rather than annotating the opcode table with a new flag.
I updated the testsuite to split out cop2 insns from mip32, mips32r2 and
mips64 tests and disabled the new tests for Octeon. The octeon part is
verified in octeon and octeon-ill.
Tested with mips64octeon-linux-gnu on top of the other patches.
OK to install?
Adam
opcodes/
* mips-opc.c (CP): New macro.
(mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
dmtc2 Octeon instructions.
gas/
* config/tc-mips.c (NO_ISA_COP): New macro.
(COP_INSN): New macro.
(is_opcode_valid): Use them.
(macro) <ld_st>: Use them. Don't accept coprocessor load store
insns based on the ISA if CPU is NO_ISA_COP.
<copz>: Likewise for coprocessor operations.
gas/testsuite/
* gas/mips/mips32.s: Move out coprocessor2 insns from here ...
* gas/mips/mips32-cp2.s: ... to here.
* gas/mips/mips32.d: Update.
* gas/mips/mips32-cp2.d: New file.
* gas/mips/mips32r2.s: Move out coprocessor2 insns from here ...
* gas/mips/mips32r2-cp2.s: ... to here.
* gas/mips/mips32r2.d: Update.
* gas/mips/mips32r2-cp2.d: New file.
* gas/mips/mips64.s: Move out coprocessor2 insns from here ...
* gas/mips/mips64-cp2.s: ... to here.
* gas/mips/mips64.d: Update.
* gas/mips/mips64-cp2.d: New file.
* gas/mips/mips.exp: Run mips32-cp2, mips32r2-cp2 and mips64-cp
except for Octeon.
* gas/mips/octeon.s: Add supported coprocessor insns.
* gas/mips/octeon.d: Update.
* gas/mips/octeon-ill.s: Add unsupported coprocessor insns.
* gas/mips/octeon-ill.l: Update.
Index: src/opcodes/mips-opc.c
===================================================================
--- src.orig/opcodes/mips-opc.c 2008-06-01 23:47:51.000000000 -0700
+++ src/opcodes/mips-opc.c 2008-06-01 23:49:34.000000000 -0700
@@ -62,6 +62,7 @@
#define WR_C1 INSN_COP
#define WR_C2 INSN_COP
#define WR_C3 INSN_COP
+#define CP INSN_COP
#define WR_HI INSN_WRITE_HI
#define RD_HI INSN_READ_HI
@@ -577,8 +578,8 @@ const struct mips_opcode mips_builtin_op
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
-{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
-{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
+{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
+{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
@@ -613,14 +614,14 @@ const struct mips_opcode mips_builtin_op
{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
-{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
-{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
-{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
+{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3|IOCT },
+{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
+{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
-{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
-{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
+{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3|IOCT },
+{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
+{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
@@ -692,8 +693,8 @@ const struct mips_opcode mips_builtin_op
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
-{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
+{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
+{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 },
@@ -864,9 +865,9 @@ const struct mips_opcode mips_builtin_op
{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
-{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
-{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
-{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
+{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|IOCT },
+{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
+{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
@@ -939,9 +940,9 @@ const struct mips_opcode mips_builtin_op
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
-{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
-{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
-{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
+{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1|IOCT },
+{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
+{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
@@ -1491,8 +1492,10 @@ const struct mips_opcode mips_builtin_op
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
+{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
+{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT },
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
@@ -1958,10 +1961,10 @@ const struct mips_opcode mips_builtin_op
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
disassembler recognizes more specific versions first. */
-{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 },
+{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1 },
{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 },
-{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 },
-{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 },
+{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1 },
+{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1 },
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 },
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
Index: src/gas/config/tc-mips.c
===================================================================
--- src.orig/gas/config/tc-mips.c 2008-06-01 23:47:51.000000000 -0700
+++ src/gas/config/tc-mips.c 2008-06-02 22:38:04.000000000 -0700
@@ -447,6 +447,11 @@ static int mips_32bitmode = 0;
/* True if CPU has seq/sne and seqi/snei instructions. */
#define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
+/* True if CPU does not implement the all the coprocessor insns. For these
+ CPUs only those COP insns are accepted that are explicitly marked to be
+ available on the CPU. ISA membership for COP insns is ignored. */
+#define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
+
/* True if mflo and mfhi can be immediately followed by instructions
which write to the HI and LO registers.
@@ -504,7 +509,17 @@ static int mips_32bitmode = 0;
/* Is this a mfhi or mflo instruction? */
#define MF_HILO_INSN(PINFO) \
- ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
+ ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
+
+/* Returns true for a (non floating-point) coprocessor instruction. Reading
+ or writing the condition code is only possible on the coprocessors and
+ these insns are not marked with INSN_COP. Thus for these insns use the
+ condition-code flags unless this is the floating-point coprocessor. */
+#define COP_INSN(PINFO) \
+ (PINFO != INSN_MACRO \
+ && (((PINFO) & INSN_COP) \
+ || ((PINFO) & (INSN_READ_COND_CODE | INSN_WRITE_COND_CODE) \
+ && ((PINFO) & (FP_S | FP_D)) == 0)))
/* MIPS PIC level. */
@@ -1803,6 +1818,12 @@ is_opcode_valid (const struct mips_opcod
if (expansionp ? mips_opts.mips16 : file_ase_mips16)
isa |= INSN_MIPS16;
+ /* Don't accept instructions based on the ISA if the CPU does not implement
+ all the coprocessor insns. */
+ if (NO_ISA_COP (mips_opts.arch)
+ && COP_INSN (mo->pinfo))
+ isa = 0;
+
if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
return FALSE;
@@ -6312,6 +6333,15 @@ macro (struct mips_cl_insn *ip)
tempreg = AT;
used_at = 1;
ld_st:
+ if (coproc
+ && NO_ISA_COP (mips_opts.arch)
+ && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
+ {
+ as_bad (_("opcode not supported on this processor: %s"),
+ mips_cpu_info_from_arch (mips_opts.arch)->name);
+ break;
+ }
+
/* Itbl support may require additional care here. */
if (mask == M_LWC1_AB
|| mask == M_SWC1_AB
@@ -7180,6 +7210,14 @@ macro (struct mips_cl_insn *ip)
case M_COP3:
s = "c3";
copz:
+ if (NO_ISA_COP (mips_opts.arch)
+ && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
+ {
+ as_bad (_("opcode not supported on this processor: %s"),
+ mips_cpu_info_from_arch (mips_opts.arch)->name);
+ break;
+ }
+
/* For now we just do C (same as Cz). The parameter will be
stored in insn_opcode by mips_ip. */
macro_build (NULL, s, "C", ip->insn_opcode);
Index: src/gas/testsuite/gas/mips/mips32.s
===================================================================
--- src.orig/gas/testsuite/gas/mips/mips32.s 2008-06-01 23:45:16.000000000 -0700
+++ src/gas/testsuite/gas/mips/mips32.s 2008-06-01 23:49:35.000000000 -0700
@@ -21,29 +21,6 @@ text_label:
ssnop
- # unprivileged coprocessor instructions.
- # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
-
- bc2f text_label
- nop
- bc2fl text_label
- nop
- bc2t text_label
- nop
- bc2tl text_label
- nop
- # XXX other BCzCond encodings not currently expressable
- cfc2 $1, $2
- cop2 0x1234567 # disassembles as c2 ...
- ctc2 $2, $3
- mfc2 $3, $4
- mfc2 $4, $5, 0 # disassembles without sel
- mfc2 $5, $6, 7
- mtc2 $6, $7
- mtc2 $7, $8, 0 # disassembles without sel
- mtc2 $8, $9, 7
-
-
# privileged instructions
cache 5, ($1)
@@ -79,15 +56,5 @@ text_label:
sdbbp 0 # disassembles without code
sdbbp 0x56789
- # Cop2 branches with cond code number, like bc1t/f
- bc2f $cc0,text_label
- nop
- bc2fl $cc1,text_label
- nop
- bc2t $cc6,text_label
- nop
- bc2tl $cc7,text_label
- nop
-
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
Index: src/gas/testsuite/gas/mips/mips32-cp2.s
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ src/gas/testsuite/gas/mips/mips32-cp2.s 2008-06-01 23:49:35.000000000 -0700
@@ -0,0 +1,39 @@
+# source file to test assembly of mips32 cop2 instructions
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+ # unprivileged coprocessor instructions.
+ # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
+
+ bc2f text_label
+ nop
+ bc2fl text_label
+ nop
+ bc2t text_label
+ nop
+ bc2tl text_label
+ nop
+ # XXX other BCzCond encodings not currently expressable
+ cfc2 $1, $2
+ cop2 0x1234567 # disassembles as c2 ...
+ ctc2 $2, $3
+ mfc2 $3, $4
+ mfc2 $4, $5, 0 # disassembles without sel
+ mfc2 $5, $6, 7
+ mtc2 $6, $7
+ mtc2 $7, $8, 0 # disassembles without sel
+ mtc2 $8, $9, 7
+
+
+ # Cop2 branches with cond code number, like bc1t/f
+ bc2f $cc0,text_label
+ nop
+ bc2fl $cc1,text_label
+ nop
+ bc2t $cc6,text_label
+ nop
+ bc2tl $cc7,text_label
+ nop
Index: src/gas/testsuite/gas/mips/mips32.d
===================================================================
--- src.orig/gas/testsuite/gas/mips/mips32.d 2008-06-01 23:45:16.000000000 -0700
+++ src/gas/testsuite/gas/mips/mips32.d 2008-06-01 23:49:35.000000000 -0700
@@ -18,57 +18,32 @@ Disassembly of section .text:
0+0020 <[^>]*> ce247fff pref 0x4,32767\(s1\)
0+0024 <[^>]*> ce448000 pref 0x4,-32768\(s2\)
0+0028 <[^>]*> 00000040 ssnop
-0+002c <[^>]*> 4900fff4 bc2f 0+0000 <text_label>
-0+0030 <[^>]*> 00000000 nop
-0+0034 <[^>]*> 4902fff2 bc2fl 0+0000 <text_label>
-0+0038 <[^>]*> 00000000 nop
-0+003c <[^>]*> 4901fff0 bc2t 0+0000 <text_label>
-0+0040 <[^>]*> 00000000 nop
-0+0044 <[^>]*> 4903ffee bc2tl 0+0000 <text_label>
-0+0048 <[^>]*> 00000000 nop
-0+004c <[^>]*> 48411000 cfc2 at,\$2
-0+0050 <[^>]*> 4b234567 c2 0x1234567
-0+0054 <[^>]*> 48c21800 ctc2 v0,\$3
-0+0058 <[^>]*> 48032000 mfc2 v1,\$4
-0+005c <[^>]*> 48042800 mfc2 a0,\$5
-0+0060 <[^>]*> 48053007 mfc2 a1,\$6,7
-0+0064 <[^>]*> 48863800 mtc2 a2,\$7
-0+0068 <[^>]*> 48874000 mtc2 a3,\$8
-0+006c <[^>]*> 48884807 mtc2 t0,\$9,7
-0+0070 <[^>]*> bc250000 cache 0x5,0\(at\)
-0+0074 <[^>]*> bc457fff cache 0x5,32767\(v0\)
-0+0078 <[^>]*> bc658000 cache 0x5,-32768\(v1\)
-0+007c <[^>]*> 3c010001 lui at,0x1
-0+0080 <[^>]*> 00240821 addu at,at,a0
-0+0084 <[^>]*> bc258000 cache 0x5,-32768\(at\)
-0+0088 <[^>]*> 3c01ffff lui at,0xffff
-0+008c <[^>]*> 00250821 addu at,at,a1
-0+0090 <[^>]*> bc257fff cache 0x5,32767\(at\)
-0+0094 <[^>]*> 3c010001 lui at,0x1
-0+0098 <[^>]*> bc258000 cache 0x5,-32768\(at\)
-0+009c <[^>]*> 3c01ffff lui at,0xffff
-0+00a0 <[^>]*> bc257fff cache 0x5,32767\(at\)
-0+00a4 <[^>]*> 42000018 eret
-0+00a8 <[^>]*> 42000008 tlbp
-0+00ac <[^>]*> 42000001 tlbr
-0+00b0 <[^>]*> 42000002 tlbwi
-0+00b4 <[^>]*> 42000006 tlbwr
-0+00b8 <[^>]*> 42000020 wait
-0+00bc <[^>]*> 42000020 wait
-0+00c0 <[^>]*> 4359e260 wait 0x56789
-0+00c4 <[^>]*> 0000000d break
-0+00c8 <[^>]*> 0000000d break
-0+00cc <[^>]*> 0345000d break 0x345
-0+00d0 <[^>]*> 0048d14d break 0x48,0x345
-0+00d4 <[^>]*> 7000003f sdbbp
-0+00d8 <[^>]*> 7000003f sdbbp
-0+00dc <[^>]*> 7159e27f sdbbp 0x56789
-0+00e0 <[^>]*> 4900ffc7 bc2f 0+0000 <text_label>
-0+00e4 <[^>]*> 00000000 nop
-0+00e8 <[^>]*> 4906ffc5 bc2fl \$cc1,0+0000 <text_label>
-0+00ec <[^>]*> 00000000 nop
-0+00f0 <[^>]*> 4919ffc3 bc2t \$cc6,0+0000 <text_label>
-0+00f4 <[^>]*> 00000000 nop
-0+00f8 <[^>]*> 491fffc1 bc2tl \$cc7,0+0000 <text_label>
-0+00fc <[^>]*> 00000000 nop
+0+002c <[^>]*> bc250000 cache 0x5,0\(at\)
+0+0030 <[^>]*> bc457fff cache 0x5,32767\(v0\)
+0+0034 <[^>]*> bc658000 cache 0x5,-32768\(v1\)
+0+0038 <[^>]*> 3c010001 lui at,0x1
+0+003c <[^>]*> 00240821 addu at,at,a0
+0+0040 <[^>]*> bc258000 cache 0x5,-32768\(at\)
+0+0044 <[^>]*> 3c01ffff lui at,0xffff
+0+0048 <[^>]*> 00250821 addu at,at,a1
+0+004c <[^>]*> bc257fff cache 0x5,32767\(at\)
+0+0050 <[^>]*> 3c010001 lui at,0x1
+0+0054 <[^>]*> bc258000 cache 0x5,-32768\(at\)
+0+0058 <[^>]*> 3c01ffff lui at,0xffff
+0+005c <[^>]*> bc257fff cache 0x5,32767\(at\)
+0+0060 <[^>]*> 42000018 eret
+0+0064 <[^>]*> 42000008 tlbp
+0+0068 <[^>]*> 42000001 tlbr
+0+006c <[^>]*> 42000002 tlbwi
+0+0070 <[^>]*> 42000006 tlbwr
+0+0074 <[^>]*> 42000020 wait
+0+0078 <[^>]*> 42000020 wait
+0+007c <[^>]*> 4359e260 wait 0x56789
+0+0080 <[^>]*> 0000000d break
+0+0084 <[^>]*> 0000000d break
+0+0088 <[^>]*> 0345000d break 0x345
+0+008c <[^>]*> 0048d14d break 0x48,0x345
+0+0090 <[^>]*> 7000003f sdbbp
+0+0094 <[^>]*> 7000003f sdbbp
+0+0098 <[^>]*> 7159e27f sdbbp 0x56789
\.\.\.
Index: src/gas/testsuite/gas/mips/mips32-cp2.d
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ src/gas/testsuite/gas/mips/mips32-cp2.d 2008-06-02 22:49:00.000000000 -0700
@@ -0,0 +1,35 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 cop2 instructions
+#as: -32
+
+# Check MIPS32 cop2 instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 4900ffff bc2f 0+0000 <text_label>
+0+0004 <[^>]*> 00000000 nop
+0+0008 <[^>]*> 4902fffd bc2fl 0+0000 <text_label>
+0+000c <[^>]*> 00000000 nop
+0+0010 <[^>]*> 4901fffb bc2t 0+0000 <text_label>
+0+0014 <[^>]*> 00000000 nop
+0+0018 <[^>]*> 4903fff9 bc2tl 0+0000 <text_label>
+0+001c <[^>]*> 00000000 nop
+0+0020 <[^>]*> 48411000 cfc2 at,\$2
+0+0024 <[^>]*> 4b234567 c2 0x1234567
+0+0028 <[^>]*> 48c21800 ctc2 v0,\$3
+0+002c <[^>]*> 48032000 mfc2 v1,\$4
+0+0030 <[^>]*> 48042800 mfc2 a0,\$5
+0+0034 <[^>]*> 48053007 mfc2 a1,\$6,7
+0+0038 <[^>]*> 48863800 mtc2 a2,\$7
+0+003c <[^>]*> 48874000 mtc2 a3,\$8
+0+0040 <[^>]*> 48884807 mtc2 t0,\$9,7
+0+0044 <[^>]*> 4900ffee bc2f 0+0000 <text_label>
+0+0048 <[^>]*> 00000000 nop
+0+004c <[^>]*> 4906ffec bc2fl \$cc1,0+0000 <text_label>
+0+0050 <[^>]*> 00000000 nop
+0+0054 <[^>]*> 4919ffea bc2t \$cc6,0+0000 <text_label>
+0+0058 <[^>]*> 00000000 nop
+0+005c <[^>]*> 491fffe8 bc2tl \$cc7,0+0000 <text_label>
+0+0060 <[^>]*> 00000000 nop
+#pass
Index: src/gas/testsuite/gas/mips/mips32r2.s
===================================================================
--- src.orig/gas/testsuite/gas/mips/mips32r2.s 2008-06-02 22:55:45.000000000 -0700
+++ src/gas/testsuite/gas/mips/mips32r2.s 2008-06-02 22:55:55.000000000 -0700
@@ -63,10 +63,5 @@ text_label:
wrpgpr $10, $25
- # cp2 instructions
-
- mfhc2 $17, 0x5555
- mthc2 $17, 0x5555
-
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
Index: src/gas/testsuite/gas/mips/mips32r2-cp2.s
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ src/gas/testsuite/gas/mips/mips32r2-cp2.s 2008-06-01 23:49:35.000000000 -0700
@@ -0,0 +1,12 @@
+# source file to test assembly of mips32r2 cop2 instructions
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+ # cp2 instructions
+
+ mfhc2 $17, 0x5555
+ mthc2 $17, 0x5555
+
Index: src/gas/testsuite/gas/mips/mips32r2.d
===================================================================
--- src.orig/gas/testsuite/gas/mips/mips32r2.d 2008-06-01 23:45:16.000000000 -0700
+++ src/gas/testsuite/gas/mips/mips32r2.d 2008-06-01 23:49:35.000000000 -0700
@@ -40,6 +40,4 @@ Disassembly of section .text:
0+0078 <[^>]*> 416a6020 ei \$10
0+007c <[^>]*> 41595000 rdpgpr \$10,\$25
0+0080 <[^>]*> 41d95000 wrpgpr \$10,\$25
-0+0084 <[^>]*> 48715555 mfhc2 \$17,0x5555
-0+0088 <[^>]*> 48f15555 mthc2 \$17,0x5555
...
Index: src/gas/testsuite/gas/mips/mips32r2-cp2.d
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ src/gas/testsuite/gas/mips/mips32r2-cp2.d 2008-06-02 22:49:27.000000000 -0700
@@ -0,0 +1,12 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS32r2 cop2 instructions
+#as: -32
+
+# Check MIPS32 Release 2 (mips32r2) cop2 instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 48715555 mfhc2 \$17,0x5555
+0+0004 <[^>]*> 48f15555 mthc2 \$17,0x5555
+#pass
Index: src/gas/testsuite/gas/mips/mips64.s
===================================================================
--- src.orig/gas/testsuite/gas/mips/mips64.s 2008-06-01 23:45:16.000000000 -0700
+++ src/gas/testsuite/gas/mips/mips64.s 2008-06-01 23:49:35.000000000 -0700
@@ -10,13 +10,3 @@ text_label:
dclo $1, $2
dclz $3, $4
-
- # unprivileged coprocessor instructions.
- # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
-
- dmfc2 $3, $4
- dmfc2 $4, $5, 0 # disassembles without sel
- dmfc2 $5, $6, 7
- dmtc2 $6, $7
- dmtc2 $7, $8, 0 # disassembles without sel
- dmtc2 $8, $9, 7
Index: src/gas/testsuite/gas/mips/mips64-cp2.s
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ src/gas/testsuite/gas/mips/mips64-cp2.s 2008-06-01 23:49:35.000000000 -0700
@@ -0,0 +1,17 @@
+# source file to test assembly of mips64 cop2 instructions
+
+ .set noreorder
+ .set noat
+
+ .globl text_label .text
+text_label:
+
+ # unprivileged coprocessor instructions.
+ # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
+
+ dmfc2 $3, $4
+ dmfc2 $4, $5, 0 # disassembles without sel
+ dmfc2 $5, $6, 7
+ dmtc2 $6, $7
+ dmtc2 $7, $8, 0 # disassembles without sel
+ dmtc2 $8, $9, 7
Index: src/gas/testsuite/gas/mips/mips64.d
===================================================================
--- src.orig/gas/testsuite/gas/mips/mips64.d 2008-06-01 23:45:16.000000000 -0700
+++ src/gas/testsuite/gas/mips/mips64.d 2008-06-02 22:49:33.000000000 -0700
@@ -9,9 +9,4 @@
Disassembly of section .text:
0+0000 <[^>]*> 70410825 dclo at,v0
0+0004 <[^>]*> 70831824 dclz v1,a0
-0+0008 <[^>]*> 48232000 dmfc2 v1,\$4
-0+000c <[^>]*> 48242800 dmfc2 a0,\$5
-0+0010 <[^>]*> 48253007 dmfc2 a1,\$6,7
-0+0014 <[^>]*> 48a63800 dmtc2 a2,\$7
-0+0018 <[^>]*> 48a74000 dmtc2 a3,\$8
-0+001c <[^>]*> 48a84807 dmtc2 t0,\$9,7
+#pass
Index: src/gas/testsuite/gas/mips/mips64-cp2.d
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ src/gas/testsuite/gas/mips/mips64-cp2.d 2008-06-02 22:49:39.000000000 -0700
@@ -0,0 +1,16 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS64 cop2 instructions
+#as: -32
+
+# Check MIPS64 cop2 instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 48232000 dmfc2 v1,\$4
+0+0004 <[^>]*> 48242800 dmfc2 a0,\$5
+0+0008 <[^>]*> 48253007 dmfc2 a1,\$6,7
+0+000c <[^>]*> 48a63800 dmtc2 a2,\$7
+0+0010 <[^>]*> 48a74000 dmtc2 a3,\$8
+0+0014 <[^>]*> 48a84807 dmtc2 t0,\$9,7
+#pass
Index: src/gas/testsuite/gas/mips/mips.exp
===================================================================
--- src.orig/gas/testsuite/gas/mips/mips.exp 2008-06-01 23:45:16.000000000 -0700
+++ src/gas/testsuite/gas/mips/mips.exp 2008-06-02 23:04:43.000000000 -0700
@@ -551,8 +551,12 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "mips32-sf32" [mips_arch_list_matching mips32]
run_list_test_arches "mips32-sf32" "-32 -msoft-float" \
[mips_arch_list_matching mips32]
+ run_dump_test_arches "mips32-cp2" [mips_arch_list_matching mips32 \
+ !octeon]
run_dump_test_arches "mips32r2" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "mips32r2-cp2" [mips_arch_list_matching mips32r2 \
+ !octeon]
run_dump_test_arches "mips32r2-fp32" \
[mips_arch_list_matching mips32r2]
run_list_test_arches "mips32r2-fp32" "-32 -msoft-float" \
@@ -565,6 +569,8 @@ if { [istarget mips*-*-vxworks*] } {
[mips_arch_list_matching mips32r2]
run_dump_test_arches "mips64" [mips_arch_list_matching mips64]
+ run_dump_test_arches "mips64-cp2" [mips_arch_list_matching mips64 \
+ !octeon]
run_dump_test_arches "mips64r2" [mips_arch_list_matching mips64r2]
run_list_test_arches "mips64r2-ill" "" [mips_arch_list_matching mips64r2]
Index: src/gas/testsuite/gas/mips/octeon.s
===================================================================
--- src.orig/gas/testsuite/gas/mips/octeon.s 2008-06-01 23:47:51.000000000 -0700
+++ src/gas/testsuite/gas/mips/octeon.s 2008-06-01 23:55:35.000000000 -0700
@@ -36,6 +36,19 @@ foo:
exts $7,$4,54,9
exts $25,37,25
+ mfc0 $13,$25
+ mfc0 $13,$11,7
+ mtc0 $6,$2
+ mtc0 $21,$9,6
+ dmfc0 $3,$29
+ dmfc0 $11,$20,5
+ dmtc0 $23,$2
+ dmtc0 $7,$14,2
+ di
+ ei
+ dmfc2 $3,0x84
+ dmtc2 $8,0x4200
+
mtm0 $26
mtm1 $19
mtm2 $18
Index: src/gas/testsuite/gas/mips/octeon.d
===================================================================
--- src.orig/gas/testsuite/gas/mips/octeon.d 2008-06-01 23:49:00.000000000 -0700
+++ src/gas/testsuite/gas/mips/octeon.d 2008-06-01 23:49:35.000000000 -0700
@@ -35,6 +35,18 @@ Disassembly of section .text:
.*: 71efa2fb exts32 \$15,\$15,0xb,0x14
.*: 70874dbb exts32 \$7,\$4,0x16,0x9
.*: 7339c97b exts32 \$25,\$25,0x5,0x19
+.*: 400dc800 mfc0 \$13,\$25
+.*: 400d5807 mfc0 \$13,\$11,7
+.*: 40861000 mtc0 \$6,\$2
+.*: 40954806 mtc0 \$21,\$9,6
+.*: 4023e800 dmfc0 \$3,\$29
+.*: 402ba005 dmfc0 \$11,\$20,5
+.*: 40b71000 dmtc0 \$23,\$2
+.*: 40a77002 dmtc0 \$7,\$14,2
+.*: 41606000 di
+.*: 41606020 ei
+.*: 48230084 dmfc2 \$3,0x84
+.*: 48a84200 dmtc2 \$8,0x4200
.*: 73400008 mtm0 \$26
.*: 7260000c mtm1 \$19
.*: 7240000d mtm2 \$18
Index: src/gas/testsuite/gas/mips/octeon-ill.s
===================================================================
--- src.orig/gas/testsuite/gas/mips/octeon-ill.s 2008-06-01 23:47:51.000000000 -0700
+++ src/gas/testsuite/gas/mips/octeon-ill.s 2008-06-02 23:07:38.000000000 -0700
@@ -20,6 +20,35 @@ foo:
cins $24,$10,64,8
cins $21,$30,50,14
+ c2 1
+ bc2f foo
+ bc2fl foo
+ bc2t foo
+ bc2tl foo
+ cfc2 $25,$12
+ ctc2 $12,$2
+ ldc2 $10,0($25)
+ lwc2 $11,12($31)
+ mfc2 $24,$1
+ mfhc2 $17,$20
+ mtc2 $2,$21
+ mthc2 $13,$25
+ sdc2 $22,8($4)
+ swc2 $2,24($2)
+
+ cop2 23
+ ldc2 $8,foo
+ lwc2 $16,foo+4
+ sdc2 $10,0x12345678
+ swc2 $16,0x12345($15)
+
+ dmfc2 $2,0x10000
+ dmtc2 $2,0x12345
+ dmfc2 $9,$12
+ dmfc2 $4,$15,4
+ dmtc2 $16,$8
+ dmtc2 $22,$7,$4
+
exts $26,26,32
exts32 $7,$21,32,10
Index: src/gas/testsuite/gas/mips/octeon-ill.l
===================================================================
--- src.orig/gas/testsuite/gas/mips/octeon-ill.l 2008-06-01 23:47:51.000000000 -0700
+++ src/gas/testsuite/gas/mips/octeon-ill.l 2008-06-01 23:49:35.000000000 -0700
@@ -8,12 +8,38 @@
.*:18: Error: Improper size \(25\)
.*:20: Error: Improper position \(64\)
.*:21: Error: Improper size \(14\)
-.*:23: Error: Improper size \(32\)
-.*:25: Error: Improper position \(32\)
-.*:26: Error: Improper size \(29\)
-.*:28: Error: Improper position \(70\)
-.*:29: Error: Improper size \(25\)
-.*:31: Error: Improper immediate \(512\)
-.*:32: Error: Improper immediate \(-771\)
-.*:33: Error: Improper immediate \(615\)
-.*:34: Error: Improper immediate \(-513\)
+.*:23: Error: opcode not supported on this processor.*
+.*:24: Error: opcode not supported on this processor.*
+.*:25: Error: opcode not supported on this processor.*
+.*:26: Error: opcode not supported on this processor.*
+.*:27: Error: opcode not supported on this processor.*
+.*:28: Error: opcode not supported on this processor.*
+.*:29: Error: opcode not supported on this processor.*
+.*:30: Error: opcode not supported on this processor.*
+.*:31: Error: opcode not supported on this processor.*
+.*:32: Error: opcode not supported on this processor.*
+.*:33: Error: opcode not supported on this processor.*
+.*:34: Error: opcode not supported on this processor.*
+.*:35: Error: opcode not supported on this processor.*
+.*:36: Error: opcode not supported on this processor.*
+.*:37: Error: opcode not supported on this processor.*
+.*:39: Error: opcode not supported on this processor.*
+.*:40: Error: opcode not supported on this processor.*
+.*:41: Error: opcode not supported on this processor.*
+.*:42: Error: opcode not supported on this processor.*
+.*:43: Error: opcode not supported on this processor.*
+.*:45: Error: expression out of range
+.*:46: Error: expression out of range
+.*:47: Error: register value used as expression
+.*:48: Error: illegal operands `dmfc2'
+.*:49: Error: register value used as expression
+.*:50: Error: illegal operands `dmtc2'
+.*:52: Error: Improper size \(32\)
+.*:54: Error: Improper position \(32\)
+.*:55: Error: Improper size \(29\)
+.*:57: Error: Improper position \(70\)
+.*:58: Error: Improper size \(25\)
+.*:60: Error: Improper immediate \(512\)
+.*:61: Error: Improper immediate \(-771\)
+.*:62: Error: Improper immediate \(615\)
+.*:63: Error: Improper immediate \(-513\)