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Add MIPS32 "SYNC stype" instruction

From: "Fu, Chao-Ying" <fu at mips dot com>
To: <binutils at sourceware dot org>
Cc: "Robinson, James" <jrob at mips dot com>, "Lau, David" <davidlau at mips dot com>
Date: Thu, 24 Jul 2008 16:58:49 -0700
Subject: Add MIPS32 "SYNC stype" instruction
Hi,

  Here is one patch to add MIPS32 "sync" instruction that
has a 5-bit sync type.  One new test is added.
Because Octeon has sync instructions that map to this new sync,
I need to move up Octeon sync instructions to decode names correctly.

  Is this patch ok?  Thanks a lot!

Regards,
Chao-ying

                === gas Summary ===

# of expected passes            818
# of expected failures          1
../as-new 2.18.50.20080724

opcodes/ChangeLog
2008-07-24  Chao-ying Fu  <fu@mips.com>

	* mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
	before sync.
	* mips-dis.c (print_insn_args: Add case '1' to print 5-bit values.

include/opcode/ChangeLog
2008-07-24  Chao-ying Fu  <fu@mips.com>

	* mips.h: Doucument '1' for 5-bit sync type.

gas/ChangeLog
2008-07-24  Chao-ying Fu  <fu@mips.com>

	* config/tc-mips.c (validate_mips_insn): Add case '1'.
	(mips_ip): Add case '1' to process sync type.

gas/testsuite/ChangeLog
2008-07-24  Chao-ying Fu  <fu@mips.com>

        * gas/mips/mips32-sync.d, gas/mip/mips32-sync.s: New tests.
        * gas/mips/mips.exp: Run them.


Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.70
diff -u -p -r1.70 mips-opc.c
--- opcodes/mips-opc.c	7 Jul 2008 19:11:15 -0000	1.70
+++ opcodes/mips-opc.c	24 Jul 2008 23:31:36 -0000
@@ -1319,14 +1319,15 @@ const struct mips_opcode mips_builtin_op
 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000,	RD_t|RD_b,		0,		I2	}, /* same */
 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I2	}, /* as swr */
 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,	0,		I4_33	},
-{"sync",    "",		0x0000000f, 0xffffffff,	INSN_SYNC,		0,		I2|G1	},
-{"sync.p",  "",		0x0000040f, 0xffffffff,	INSN_SYNC,		0,		I2	},
-{"sync.l",  "",		0x0000000f, 0xffffffff,	INSN_SYNC,		0,		I2	},
-{"synci",   "o(b)",	0x041f0000, 0xfc1f0000,	SM|RD_b,		0,		I33	},
 {"synciobdma", "",	0x0000008f, 0xffffffff,	INSN_SYNC,		0,		IOCT	},
 {"syncs",   "",		0x0000018f, 0xffffffff,	INSN_SYNC,		0,		IOCT	},
 {"syncw",   "",		0x0000010f, 0xffffffff,	INSN_SYNC,		0,		IOCT	},
 {"syncws",  "",		0x0000014f, 0xffffffff,	INSN_SYNC,		0,		IOCT	},
+{"sync",    "",		0x0000000f, 0xffffffff,	INSN_SYNC,		0,		I2|G1	},
+{"sync",    "1",	0x0000000f, 0xfffff83f,	INSN_SYNC,		0,		I32	},
+{"sync.p",  "",		0x0000040f, 0xffffffff,	INSN_SYNC,		0,		I2	},
+{"sync.l",  "",		0x0000000f, 0xffffffff,	INSN_SYNC,		0,		I2	},
+{"synci",   "o(b)",	0x041f0000, 0xfc1f0000,	SM|RD_b,		0,		I33	},
 {"syscall", "",		0x0000000c, 0xffffffff,	TRAP,			0,		I1	},
 {"syscall", "B",	0x0000000c, 0xfc00003f,	TRAP,			0,		I1	},
 {"teqi",    "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.74
diff -u -p -r1.74 mips-dis.c
--- opcodes/mips-dis.c	10 Jul 2008 19:05:28 -0000	1.74
+++ opcodes/mips-dis.c	24 Jul 2008 23:31:37 -0000
@@ -1104,6 +1104,7 @@ print_insn_args (const char *d,
 	  break;
 
 	case '<':
+	case '1':
 	  (*info->fprintf_func) (info->stream, "0x%lx",
 				 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
 	  break;
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.59
diff -u -p -r1.59 mips.h
--- include/opcode/mips.h	12 Jun 2008 21:44:53 -0000	1.59
+++ include/opcode/mips.h	24 Jul 2008 23:31:37 -0000
@@ -262,6 +262,7 @@ struct mips_opcode
 
    Each of these characters corresponds to a mask field defined above.
 
+   "1" 5 bit sync type amount (OP_*_SHAMT)
    "<" 5 bit shift amount (OP_*_SHAMT)
    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
    "a" 26 bit target address (OP_*_TARGET)
@@ -401,7 +402,7 @@ struct mips_opcode
    "+"  Start of extension sequence.
 
    Characters used so far, for quick reference when adding more:
-   "234567890"
+   "1234567890"
    "%[]<>(),+:'@!$*&"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefghijklopqrstuvwxz"
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.391
diff -u -p -r1.391 tc-mips.c
--- gas/config/tc-mips.c	22 Jul 2008 10:44:50 -0000	1.391
+++ gas/config/tc-mips.c	24 Jul 2008 23:31:43 -0000
@@ -8412,6 +8412,7 @@ validate_mips_insn (const struct mips_op
       case '%': USE_BITS (OP_MASK_VECALIGN,	OP_SH_VECALIGN); break;
       case '[': break;
       case ']': break;
+      case '1':	USE_BITS (OP_MASK_SHAMT,	OP_SH_SHAMT);	break;
       case '2': USE_BITS (OP_MASK_BP,		OP_SH_BP);	break;
       case '3': USE_BITS (OP_MASK_SA3,  	OP_SH_SA3);	break;
       case '4': USE_BITS (OP_MASK_SA4,  	OP_SH_SA4);	break;
@@ -9198,6 +9199,7 @@ do_msbd:
 
 	    case 'k':		/* cache code */
 	    case 'h':		/* prefx code */
+	    case '1':		/* sync type */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > 31)
@@ -9206,8 +9208,10 @@ do_msbd:
 			 (unsigned long) imm_expr.X_add_number);
 	      if (*args == 'k')
 		INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
-	      else
+	      else if (*args == 'h')
 		INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
+	      else
+		INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.142
diff -u -p -r1.142 mips.exp
--- gas/testsuite/gas/mips/mips.exp	10 Jul 2008 19:05:29 -0000	1.142
+++ gas/testsuite/gas/mips/mips.exp	24 Jul 2008 23:31:43 -0000
@@ -829,4 +829,5 @@ if { [istarget mips*-*-vxworks*] } {
 					[mips_arch_list_matching mips1]
 
     run_dump_test "mips16-vis-1"
+    run_dump_test "mips32-sync"
 }
Index: gas/testsuite/gas/mips/mips32-sync.s
===================================================================
RCS file: gas/testsuite/gas/mips/mips32-sync.s
diff -N gas/testsuite/gas/mips/mips32-sync.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips32-sync.s	24 Jul 2008 23:31:43 -0000
@@ -0,0 +1,10 @@
+	.text
+foo:
+	.ent foo
+	sync
+	sync	0
+	sync	1
+	sync	2
+	sync	30
+	sync	31
+	.end foo
Index: gas/testsuite/gas/mips/mips32-sync.d
===================================================================
RCS file: gas/testsuite/gas/mips/mips32-sync.d
diff -N gas/testsuite/gas/mips/mips32-sync.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/mips32-sync.d	24 Jul 2008 23:31:43 -0000
@@ -0,0 +1,14 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32
+#name: MIPS32 sync instructions
+#as: -32 -mips32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <foo> 0000000f[ 	]*sync
+0+0004 <foo\+0x4> 0000000f[ 	]*sync
+0+0008 <foo\+0x8> 0000004f[ 	]*sync	0x1
+0+000c <foo\+0xc> 0000008f[ 	]*sync	0x2
+0+0010 <foo\+0x10> 0000078f[ 	]*sync	0x1e
+0+0014 <foo\+0x14> 000007cf[ 	]*sync	0x1f
+#pass
Follow-Ups:
- Re: Add MIPS32 "SYNC stype" instruction
  - From: Thiemo Seufer
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