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[PATCH] Lexra binutils
- From: Sergey Lapin <slapin at ossfans dot org>
- To: <binutils at sourceware dot org>
- Cc: Sergey Lapin <slapin at ossfans dot org>
- Date: Wed, 17 Sep 2008 15:54:12 +0400
- Subject: [PATCH] Lexra binutils
This patch is based on Lexra patches which were submitted to binutils
mainling list, rebased for current binutils and made it co-exist with
normal MIPS targets.
The base revision of binutils for this patch is 2.17.
This patch should not break anything (I have tested that, so I hope),
so it should be possible to commit it. But beforehand I'd like to have
some advice from binutils gurus about proper usage and proper review.
Usage:
mips-linux-uclibc-as -march=lexra -mtune=lexra somefile.s
Instead of "lexra" word you could also use "lx5280" if you like.
Theoretically, these flags should be used from gcc (as soon as I
look into Eugeny's patch and change it appropriately).
Waiting for your feedback.
S.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
---
bfd/bfd-in2.h | 1 +
bfd/cpu-mips.c | 4 ++-
gas/config/tc-mips.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++--
include/opcode/mips.h | 5 ++-
opcodes/mips-opc.c | 25 ++++++++-------
5 files changed, 98 insertions(+), 17 deletions(-)
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 64c022f..f8045c1 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1757,6 +1757,7 @@ enum bfd_architecture
#define bfd_mach_mips16 16
#define bfd_mach_mips5 5
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_lexra 0x4c58
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 5f4dcca..a83fbbd 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -86,6 +86,7 @@ enum
I_mipsisa64,
I_mipsisa64r2,
I_sb1,
+ I_lexra,
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -118,7 +119,8 @@ static const bfd_arch_info_type arch_info_struct[] =
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
+ N (32, 32, bfd_mach_mips_lexra, "mips:lexra", FALSE, 0),
};
/* The default architecture is mips:3000, but with a machine number of
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index c885205..e8c0de6 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -411,6 +411,7 @@ static int mips_32bitmode = 0;
|| mips_opts.arch == CPU_R12000 \
|| mips_opts.arch == CPU_RM7000 \
|| mips_opts.arch == CPU_VR5500 \
+ || mips_opts.arch == CPU_LX5280 \
)
/* Whether the processor uses hardware interlocks to protect reads
@@ -420,7 +421,8 @@ static int mips_32bitmode = 0;
level I. */
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
- || mips_opts.arch == CPU_R3900)
+ || mips_opts.arch == CPU_R3900 \
+ || mips_opts.arch == CPU_LX5280)
/* Whether the processor uses hardware interlocks to avoid delays
required by coprocessor instructions, and thus does not require
@@ -435,6 +437,7 @@ static int mips_32bitmode = 0;
&& mips_opts.isa != ISA_MIPS2 \
&& mips_opts.isa != ISA_MIPS3) \
|| mips_opts.arch == CPU_R4300 \
+ || mips_opts.arch == CPU_LX5280 \
)
/* Whether the processor uses hardware interlocks to protect reads
@@ -442,7 +445,11 @@ static int mips_32bitmode = 0;
thus does not require nops to be inserted. This applies to
instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
requires at MIPS ISA level I. */
-#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
+#define cop_mem_interlocks \
+ ((mips_opts.isa != ISA_MIPS1) \
+ || mips_opts.arch == CPU_LX5280 \
+ )
+
/* Is this a mfhi or mflo instruction? */
#define MF_HILO_INSN(PINFO) \
@@ -5719,10 +5726,20 @@ macro (struct mips_cl_insn *ip)
coproc = 1;
goto ld;
case M_LWL_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwl";
lr = 1;
goto ld;
case M_LWR_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwr";
lr = 1;
goto ld;
@@ -5803,9 +5820,19 @@ macro (struct mips_cl_insn *ip)
coproc = 1;
goto st;
case M_SWL_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swl";
goto st;
case M_SWR_AB:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swr";
goto st;
case M_SC_AB:
@@ -7375,11 +7402,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_ULD:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "ldl";
s2 = "ldr";
off = 7;
goto ulw;
case M_ULW:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwl";
s2 = "lwr";
off = 3;
@@ -7411,11 +7448,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_ULD_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "ldl";
s2 = "ldr";
off = 7;
goto ulwa;
case M_ULW_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "lwl";
s2 = "lwr";
off = 3;
@@ -7471,11 +7518,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_USD:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "sdl";
s2 = "sdr";
off = 7;
goto usw;
case M_USW:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swl";
s2 = "swr";
off = 3;
@@ -7493,11 +7550,21 @@ macro2 (struct mips_cl_insn *ip)
break;
case M_USD_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "sdl";
s2 = "sdr";
off = 7;
goto uswa;
case M_USW_A:
+ if (mips_opts.arch == CPU_LX5280)
+ {
+ as_bad (_("opcode not supported on this processor"));
+ break;
+ }
s = "swl";
s2 = "swr";
off = 3;
@@ -8003,12 +8070,15 @@ mips_ip (char *str, struct mips_cl_insn *ip)
else
ok = FALSE;
+ if (mips_opts.arch == CPU_LX5280 && (insn->membership & INSN_LXMISS) != 0)
+ ok = FALSE;
+
if (insn->pinfo != INSN_MACRO)
{
if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
ok = FALSE;
- }
+ }
if (! ok)
{
if (insn + 1 < &mips_opcodes[NUMOPCODES]
@@ -14300,6 +14370,10 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
/* Broadcom SB-1 CPU core */
{ "sb1", 0, ISA_MIPS64, CPU_SB1 },
+ /* Lexra core w/o patented instructions */
+ { "lx5280", 0, ISA_MIPS1, CPU_LX5280 },
+ { "lexra", 0, ISA_MIPS1, CPU_LX5280 },
+
/* End marker */
{ NULL, 0, 0, 0 }
};
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 4bec5ed..f0345a2 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -502,6 +502,8 @@ struct mips_opcode
#define INSN_5500 0x02000000
/* MT ASE */
#define INSN_MT 0x04000000
+/* Absent on Lexra */
+#define INSN_LXMISS 0x08000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -549,6 +551,7 @@ struct mips_opcode
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
+#define CPU_LX5280 0x4c58
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@@ -570,7 +573,7 @@ struct mips_opcode
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
- || 0) /* Please keep this term for easier source merging. */
+ || 0) /* Please keep this term for easier source merging. */ \
/* This is a list of macro expanded instructions.
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index cd92a9f..f5747a3 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -88,6 +88,7 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
#define I64 INSN_ISA64
#define I33 INSN_ISA32R2
#define I65 INSN_ISA64R2
+#define LXMISS INSN_LXMISS /* absent on Lexra */
/* MIPS64 MIPS-3D ASE support. */
#define I16 INSN_MIPS16
@@ -725,12 +726,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
-{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
-{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
+{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1|LXMISS},
+{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1|LXMISS},
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */
-{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
-{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
+{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1|LXMISS},
+{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1|LXMISS},
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */
{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
@@ -1169,12 +1170,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
-{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
-{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
+{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1|LXMISS},
+{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1|LXMISS},
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */
-{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
-{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
+{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1|LXMISS},
+{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1|LXMISS},
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 },
@@ -1232,14 +1233,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
-{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
-{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
+{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1|LXMISS},
+{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1|LXMISS},
{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
-{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
-{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
+{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1|LXMISS},
+{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1|LXMISS},
{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
--
1.5.6.5