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[PATCH, MIPS] Accept cfc1 on Octeon (without -msoft-float)
- From: Adam Nemet <anemet at caviumnetworks dot com>
- To: binutils at sourceware dot org
- Date: Mon, 3 Nov 2008 15:47:49 -0800
- Subject: [PATCH, MIPS] Accept cfc1 on Octeon (without -msoft-float)
Apparently I missed that cfc1 is marked both ISNS_COP and FP_S. So the
current logic to find non-fp COP instructions in INSN_COP returns true for
cfc1. As a result cfc1 is considered a COP insn and since it is not
explicitely enabled for Octeon, it gets refused.
The patch below adjust the logic in INSN_COP.
There is no MIPS1 FP test in the testsuite. I'm adding a very mimimal one
(only containing add.s and cfc1 ATM) that I used to test this patch.
Tested with mips64octeon-linux-gnu.
OK to install?
Adam
* tc-mips.c (COP_INSN): Change logic to always return false for FP
instructions.
* testsuite/gas/mips/mips1-fp.s, testsuite/gas/mips/mips1-fp.d,
testsuite/gas/mips/mips1-fp.l: New tests.
* testsuite/gas/mips/mips.exp: Run them.
Index: config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.394
diff -u -p -r1.394 tc-mips.c
--- config/tc-mips.c 8 Aug 2008 19:24:49 -0000 1.394
+++ config/tc-mips.c 3 Nov 2008 23:29:24 -0000
@@ -514,12 +514,11 @@ static int mips_32bitmode = 0;
/* Returns true for a (non floating-point) coprocessor instruction. Reading
or writing the condition code is only possible on the coprocessors and
these insns are not marked with INSN_COP. Thus for these insns use the
- condition-code flags unless this is the floating-point coprocessor. */
+ condition-code flags. */
#define COP_INSN(PINFO) \
(PINFO != INSN_MACRO \
- && (((PINFO) & INSN_COP) \
- || ((PINFO) & (INSN_READ_COND_CODE | INSN_WRITE_COND_CODE) \
- && ((PINFO) & (FP_S | FP_D)) == 0)))
+ && ((PINFO) & (FP_S | FP_D)) == 0 \
+ && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
/* MIPS PIC level. */
Index: testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.145
diff -u -p -r1.145 mips.exp
--- testsuite/gas/mips/mips.exp 6 Sep 2008 08:47:00 -0000 1.145
+++ testsuite/gas/mips/mips.exp 3 Nov 2008 23:29:24 -0000
@@ -398,6 +398,9 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "abs" [mips_arch_list_matching mips1]
run_dump_test_arches "add" [mips_arch_list_matching mips1]
run_dump_test_arches "and" [mips_arch_list_matching mips1]
+ run_dump_test_arches "mips1-fp" [mips_arch_list_matching mips1]
+ run_list_test_arches "mips1-fp" "-32 -msoft-float" \
+ [mips_arch_list_matching mips1]
run_dump_test "break20"
run_dump_test "trap20"
Index: testsuite/gas/mips/mips1-fp.s
===================================================================
RCS file: testsuite/gas/mips/mips1-fp.s
diff -N testsuite/gas/mips/mips1-fp.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/mips/mips1-fp.s 3 Nov 2008 23:29:24 -0000
@@ -0,0 +1,7 @@
+# Source file used to test -mips1 fp instructions.
+
+# This is not a complete list of mips1 FP instructions.
+
+foo:
+ add.s $f0,$f2,$f4
+ cfc1 $2,$0
Index: testsuite/gas/mips/mips1-fp.d
===================================================================
RCS file: testsuite/gas/mips/mips1-fp.d
diff -N testsuite/gas/mips/mips1-fp.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/mips/mips1-fp.d 3 Nov 2008 23:29:24 -0000
@@ -0,0 +1,12 @@
+#as: -32
+#objdump: -M reg-names=numeric -dr
+#name: MIPS1 FP instructions
+
+.*: file format .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <foo>:
+.*: 46041000 add.s \$f0,\$f2,\$f4
+.*: 44420000 cfc1 \$2,\$0
+#pass
Index: testsuite/gas/mips/mips1-fp.l
===================================================================
RCS file: testsuite/gas/mips/mips1-fp.l
diff -N testsuite/gas/mips/mips1-fp.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/mips/mips1-fp.l 3 Nov 2008 23:29:24 -0000
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f0,\$f2,\$f4'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `cfc1 \$2,\$0'