Initially our custom processor support only one unconditional branch
instruction 'bra' of 20 bit range (32 bit instruction).
Now we are planned to add 16 bit unconditional branch instruction 'bra'
of 8 bit range.
both shares same instruction name 'bra'.But it leading a problem for us.
For example:
bra Label
nop
nop
...
Label: nop
In first pass 'Label' address is treated as 0 so it is selecting 16 bit
instruction.
In second pass it finds that the 'Label' is out of 8 bit range and fails
to generate appropriate 32bit instruction opcode.