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[PATCH,committed] Fix
- From: Peter Bergner <bergner at vnet dot ibm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Alan Modra <amodra at bigpond dot net dot au>, Edmar Wienskoski-RA8797 <edmar at freescale dot com>
- Date: Thu, 19 Feb 2009 15:23:35 -0600
- Subject: [PATCH,committed] Fix
While working on the POWER7 ISA 2.06 changes, I came across this buglet
that really only affects the disassembler. I committed this as obvious.
Peter
gas/testsuite/
* gas/ppc/e500mc.d ("lfdepx", "stfdepx"): Fix tests to expect a
floating point register.
opcodes/
* ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first
operand to be a float point register (FRT/FRS).
Index: gas/testsuite/gas/ppc/e500mc.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/e500mc.d,v
retrieving revision 1.1
diff -u -p -r1.1 e500mc.d
--- gas/testsuite/gas/ppc/e500mc.d 14 Apr 2008 11:01:38 -0000 1.1
+++ gas/testsuite/gas/ppc/e500mc.d 19 Feb 2009 19:53:01 -0000
@@ -22,12 +22,12 @@ Disassembly of section \.text:
30: 7c 85 32 3e lhepx r4,r5,r6
34: 7c e8 48 3e lwepx r7,r8,r9
38: 7d 4b 60 3a ldepx r10,r11,r12
- 3c: 7d ae 7c be lfdepx r13,r14,r15
+ 3c: 7d ae 7c be lfdepx f13,r14,r15
40: 7e 11 91 be stbepx r16,r17,r18
44: 7e 74 ab 3e sthepx r19,r20,r21
48: 7e d7 c1 3e stwepx r22,r23,r24
4c: 7f 3a d9 3a stdepx r25,r26,r27
- 50: 7f 9d f5 be stfdepx r28,r29,r30
+ 50: 7f 9d f5 be stfdepx f28,r29,r30
54: 7c 01 14 06 lbdx r0,r1,r2
58: 7d 8d 74 46 lhdx r12,r13,r14
5c: 7c 64 2c 86 lwdx r3,r4,r5
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.115
diff -u -p -r1.115 ppc-opc.c
--- opcodes/ppc-opc.c 6 Feb 2009 01:50:54 -0000 1.115
+++ opcodes/ppc-opc.c 19 Feb 2009 19:53:03 -0000
@@ -4286,7 +4286,7 @@ const struct powerpc_opcode powerpc_opco
{"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}},
-{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, PPCNONE, {FRT, RB}},
{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
@@ -4373,7 +4373,7 @@ const struct powerpc_opcode powerpc_opco
{"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
+{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, PPCNONE, {RT, FRB}},
{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},