This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
PATCH: Check for lock without a lockable instruction
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: binutils at sourceware dot org
- Date: Thu, 12 Nov 2009 10:54:19 -0800
- Subject: PATCH: Check for lock without a lockable instruction
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
Hi,
The lock prefix is valid only on add, adc, and, btc, btr, bts, cmpxchg,
cmpxch8b, dec, inc, neg, not, or, sbb, sub, xor, xadd and xchg with
a memory operand. I am checking in this patch to check for it.
Thanks.
H.J.
---
gas/
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (LOCKREP_PREFIX): Removed.
(REP_PREFIX): New.
(LOCK_PREFIX): Likewise.
(PREFIX_GROUP): Likewise.
(REX_PREFIX): Updated.
(MAX_PREFIXES): Likewise.
(add_prefix): Updated. Return enum PREFIX_GROUP.
(md_assemble): Check for lock without a lockable instruction.
(parse_insn): Updated.
(output_insn): Likewise.
gas/testsuite/
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1,
x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1.
* gas/i386/lock-1-intel.d: New.
* gas/i386/lock-1.d: Likewise.
* gas/i386/lock-1.s: Likewise.
* gas/i386/lockbad-1.l: Likewise.
* gas/i386/lockbad-1.s: Likewise.
* gas/i386/x86-64-lock-1-intel.d: Likewise.
* gas/i386/x86-64-lock-1.d: Likewise.
* gas/i386/x86-64-lock-1.s: Likewise.
* gas/i386/x86-64-lockbad-1.l: Likewise.
* gas/i386/x86-64-lockbad-1.s: Likewise.
opcodes/
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add IsLockable.
* i386-opc.h (IsLockable): New.
(i386_opcode_modifier): Add islockable.
* i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr,
bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub,
xor, xadd and xchg.
* i386-tbl.h: Regenerated.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index e787215..4f80e98 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -59,14 +59,15 @@
WAIT_PREFIX must be the first prefix since FWAIT is really is an
instruction, and so must come before any prefixes.
The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
- LOCKREP_PREFIX. */
+ REP_PREFIX, LOCK_PREFIX. */
#define WAIT_PREFIX 0
#define SEG_PREFIX 1
#define ADDR_PREFIX 2
#define DATA_PREFIX 3
-#define LOCKREP_PREFIX 4
-#define REX_PREFIX 5 /* must come last. */
-#define MAX_PREFIXES 6 /* max prefixes per opcode */
+#define REP_PREFIX 4
+#define LOCK_PREFIX 5
+#define REX_PREFIX 6 /* must come last. */
+#define MAX_PREFIXES 7 /* max prefixes per opcode */
/* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%'
@@ -1783,13 +1784,26 @@ offset_in_range (offsetT val, int size)
return val & mask;
}
-/* Returns 0 if attempting to add a prefix where one from the same
- class already exists, 1 if non rep/repne added, 2 if rep/repne
- added. */
-static int
+enum PREFIX_GROUP
+{
+ PREFIX_EXIST = 0,
+ PREFIX_LOCK,
+ PREFIX_REP,
+ PREFIX_OTHER
+};
+
+/* Returns
+ a. PREFIX_EXIST if attempting to add a prefix where one from the
+ same class already exists.
+ b. PREFIX_LOCK if lock prefix is added.
+ c. PREFIX_REP if rep/repne prefix is added.
+ d. PREFIX_OTHER if other prefix is added.
+ */
+
+static enum PREFIX_GROUP
add_prefix (unsigned int prefix)
{
- int ret = 1;
+ enum PREFIX_GROUP ret = PREFIX_OTHER;
unsigned int q;
if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
@@ -1798,7 +1812,7 @@ add_prefix (unsigned int prefix)
if ((i.prefix[REX_PREFIX] & prefix & REX_W)
|| ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
&& (prefix & (REX_R | REX_X | REX_B))))
- ret = 0;
+ ret = PREFIX_EXIST;
q = REX_PREFIX;
}
else
@@ -1819,10 +1833,13 @@ add_prefix (unsigned int prefix)
case REPNE_PREFIX_OPCODE:
case REPE_PREFIX_OPCODE:
- ret = 2;
- /* fall thru */
+ q = REP_PREFIX;
+ ret = PREFIX_REP;
+ break;
+
case LOCK_PREFIX_OPCODE:
- q = LOCKREP_PREFIX;
+ q = LOCK_PREFIX;
+ ret = PREFIX_LOCK;
break;
case FWAIT_OPCODE:
@@ -1838,7 +1855,7 @@ add_prefix (unsigned int prefix)
break;
}
if (i.prefix[q] != 0)
- ret = 0;
+ ret = PREFIX_EXIST;
}
if (ret)
@@ -2915,6 +2932,15 @@ md_assemble (char *line)
if (!add_prefix (FWAIT_OPCODE))
return;
+ /* Check for lock without a lockable instruction. */
+ if (i.prefix[LOCK_PREFIX]
+ && (!i.tm.opcode_modifier.islockable
+ || i.mem_operands == 0))
+ {
+ as_bad (_("expecting lockable instruction after `lock'"));
+ return;
+ }
+
/* Check string instruction segment overrides. */
if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
{
@@ -3111,11 +3137,13 @@ parse_insn (char *line, char *mnemonic)
/* Add prefix, checking for repeated prefixes. */
switch (add_prefix (current_templates->start->base_opcode))
{
- case 0:
+ case PREFIX_EXIST:
return NULL;
- case 2:
+ case PREFIX_REP:
expecting_string_instruction = current_templates->start->name;
break;
+ default:
+ break;
}
/* Skip past PREFIX_SEPARATOR and reset token_start. */
token_start = ++l;
@@ -5636,7 +5664,7 @@ output_insn (void)
{
check_prefix:
if (prefix != REPE_PREFIX_OPCODE
- || (i.prefix[LOCKREP_PREFIX]
+ || (i.prefix[REP_PREFIX]
!= REPE_PREFIX_OPCODE))
add_prefix (prefix);
}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 52b57b6..bcdeec5 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -63,6 +63,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "ssse3"
run_dump_test "rep"
run_dump_test "rep-suffix"
+ run_dump_test "lock-1"
+ run_dump_test "lock-1-intel"
+ run_list_test "lockbad-1" "-al"
run_dump_test "fp"
run_dump_test "nops"
run_dump_test "nops16-1"
@@ -251,6 +254,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-ssse3"
run_dump_test "x86-64-rep"
run_dump_test "x86-64-rep-suffix"
+ run_dump_test "x86-64-lock-1"
+ run_dump_test "x86-64-lock-1-intel"
+ run_list_test "x86-64-lockbad-1" "-al"
run_dump_test "x86-64-cbw"
run_dump_test "x86-64-cbw-intel"
run_dump_test "x86-64-io"
diff --git a/gas/testsuite/gas/i386/lock-1-intel.d b/gas/testsuite/gas/i386/lock-1-intel.d
new file mode 100644
index 0000000..9897a92
--- /dev/null
+++ b/gas/testsuite/gas/i386/lock-1-intel.d
@@ -0,0 +1,69 @@
+#objdump: -dwMintel
+#name: i386 lockable insns (Intel disassembly)
+#source: lock-1.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: f0 03 03 lock add eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 03 64 lock add DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 13 03 lock adc eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 13 64 lock adc DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 23 03 lock and eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 23 64 lock and DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f bb 03 lock btc DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 3b 64 lock btc DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f b3 03 lock btr DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 33 64 lock btr DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f ab 03 lock bts DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 f7 13 lock not DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 0b 03 lock or eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 0b 64 lock or DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 1b 03 lock sbb eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 1b 64 lock sbb DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 2b 03 lock sub eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 2b 64 lock sub DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f c1 03 lock xadd DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 87 03 lock xchg DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 87 03 lock xchg DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 33 03 lock xor eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 33 64 lock xor DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 03 03 lock add eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 03 64 lock add DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 13 03 lock adc eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 13 64 lock adc DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 23 03 lock and eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 23 64 lock and DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f bb 03 lock btc DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 3b 64 lock btc DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f b3 03 lock btr DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 33 64 lock btr DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f ab 03 lock bts DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 f7 13 lock not DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 0b 03 lock or eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 0b 64 lock or DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 1b 03 lock sbb eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 1b 64 lock sbb DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 2b 03 lock sub eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 2b 64 lock sub DWORD PTR \[ebx\],0x64
+[ ]*[a-f0-9]+: f0 0f c1 03 lock xadd DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 87 03 lock xchg DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 87 03 lock xchg DWORD PTR \[ebx\],eax
+[ ]*[a-f0-9]+: f0 33 03 lock xor eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: f0 83 33 64 lock xor DWORD PTR \[ebx\],0x64
+#pass
diff --git a/gas/testsuite/gas/i386/lock-1.d b/gas/testsuite/gas/i386/lock-1.d
new file mode 100644
index 0000000..a9ab747
--- /dev/null
+++ b/gas/testsuite/gas/i386/lock-1.d
@@ -0,0 +1,68 @@
+#objdump: -dw
+#name: i386 lockable insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: f0 03 03 lock add \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 03 64 lock addl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 13 03 lock adc \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 13 64 lock adcl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 23 03 lock and \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 23 64 lock andl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f bb 03 lock btc %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f ba 3b 64 lock btcl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f b3 03 lock btr %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f ba 33 64 lock btrl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f ab 03 lock bts %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%ebx\)
+[ ]*[a-f0-9]+: f0 ff 0b lock decl \(%ebx\)
+[ ]*[a-f0-9]+: f0 ff 03 lock incl \(%ebx\)
+[ ]*[a-f0-9]+: f0 f7 1b lock negl \(%ebx\)
+[ ]*[a-f0-9]+: f0 f7 13 lock notl \(%ebx\)
+[ ]*[a-f0-9]+: f0 0b 03 lock or \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 0b 64 lock orl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 1b 03 lock sbb \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 1b 64 lock sbbl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 2b 03 lock sub \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 2b 64 lock subl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f c1 03 lock xadd %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 87 03 lock xchg %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 87 03 lock xchg %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 33 03 lock xor \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 33 64 lock xorl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 03 03 lock add \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 03 64 lock addl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 13 03 lock adc \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 13 64 lock adcl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 23 03 lock and \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 23 64 lock andl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f bb 03 lock btc %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f ba 3b 64 lock btcl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f b3 03 lock btr %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f ba 33 64 lock btrl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f ab 03 lock bts %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%ebx\)
+[ ]*[a-f0-9]+: f0 ff 0b lock decl \(%ebx\)
+[ ]*[a-f0-9]+: f0 ff 03 lock incl \(%ebx\)
+[ ]*[a-f0-9]+: f0 f7 1b lock negl \(%ebx\)
+[ ]*[a-f0-9]+: f0 f7 13 lock notl \(%ebx\)
+[ ]*[a-f0-9]+: f0 0b 03 lock or \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 0b 64 lock orl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 1b 03 lock sbb \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 1b 64 lock sbbl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 2b 03 lock sub \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 2b 64 lock subl \$0x64,\(%ebx\)
+[ ]*[a-f0-9]+: f0 0f c1 03 lock xadd %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 87 03 lock xchg %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 87 03 lock xchg %eax,\(%ebx\)
+[ ]*[a-f0-9]+: f0 33 03 lock xor \(%ebx\),%eax
+[ ]*[a-f0-9]+: f0 83 33 64 lock xorl \$0x64,\(%ebx\)
+#pass
diff --git a/gas/testsuite/gas/i386/lock-1.s b/gas/testsuite/gas/i386/lock-1.s
new file mode 100644
index 0000000..11991f7
--- /dev/null
+++ b/gas/testsuite/gas/i386/lock-1.s
@@ -0,0 +1,64 @@
+# Lockable Instructions
+
+ .text
+foo:
+ lock add (%ebx), %eax
+ lock add $0x64, (%ebx)
+ lock adc (%ebx), %eax
+ lock adc $0x64, (%ebx)
+ lock and (%ebx), %eax
+ lock and $0x64, (%ebx)
+ lock btc %eax, (%ebx)
+ lock btc $0x64, (%ebx)
+ lock btr %eax, (%ebx)
+ lock btr $0x64, (%ebx)
+ lock bts %eax, (%ebx)
+ lock bts $0x64, (%ebx)
+ lock cmpxchg %eax,(%ebx)
+ lock cmpxchg8b (%ebx)
+ lock decl (%ebx)
+ lock incl (%ebx)
+ lock negl (%ebx)
+ lock notl (%ebx)
+ lock or (%ebx), %eax
+ lock or $0x64, (%ebx)
+ lock sbb (%ebx), %eax
+ lock sbb $0x64, (%ebx)
+ lock sub (%ebx), %eax
+ lock sub $0x64, (%ebx)
+ lock xadd %eax, (%ebx)
+ lock xchg (%ebx), %eax
+ lock xchg %eax, (%ebx)
+ lock xor (%ebx), %eax
+ lock xor $0x64, (%ebx)
+
+ .intel_syntax noprefix
+ lock add eax,DWORD PTR [ebx]
+ lock add DWORD PTR [ebx],0x64
+ lock adc eax,DWORD PTR [ebx]
+ lock adc DWORD PTR [ebx],0x64
+ lock and eax,DWORD PTR [ebx]
+ lock and DWORD PTR [ebx],0x64
+ lock btc DWORD PTR [ebx],eax
+ lock btc DWORD PTR [ebx],0x64
+ lock btr DWORD PTR [ebx],eax
+ lock btr DWORD PTR [ebx],0x64
+ lock bts DWORD PTR [ebx],eax
+ lock bts DWORD PTR [ebx],0x64
+ lock cmpxchg DWORD PTR [ebx],eax
+ lock cmpxchg8b QWORD PTR [ebx]
+ lock dec DWORD PTR [ebx]
+ lock inc DWORD PTR [ebx]
+ lock neg DWORD PTR [ebx]
+ lock not DWORD PTR [ebx]
+ lock or eax,DWORD PTR [ebx]
+ lock or DWORD PTR [ebx],0x64
+ lock sbb eax,DWORD PTR [ebx]
+ lock sbb DWORD PTR [ebx],0x64
+ lock sub eax,DWORD PTR [ebx]
+ lock sub DWORD PTR [ebx],0x64
+ lock xadd DWORD PTR [ebx],eax
+ lock xchg DWORD PTR [ebx],eax
+ lock xchg DWORD PTR [ebx],eax
+ lock xor eax,DWORD PTR [ebx]
+ lock xor DWORD PTR [ebx],0x64
diff --git a/gas/testsuite/gas/i386/lockbad-1.l b/gas/testsuite/gas/i386/lockbad-1.l
new file mode 100644
index 0000000..19ea049
--- /dev/null
+++ b/gas/testsuite/gas/i386/lockbad-1.l
@@ -0,0 +1,135 @@
+.*: Assembler messages:
+.*:5: Error: .*
+.*:6: Error: .*
+.*:8: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:14: Error: .*
+.*:15: Error: .*
+.*:16: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:22: Error: .*
+.*:23: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:30: Error: .*
+.*:31: Error: .*
+.*:32: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:35: Error: .*
+.*:38: Error: .*
+.*:39: Error: .*
+.*:41: Error: .*
+.*:42: Error: .*
+.*:43: Error: .*
+.*:44: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:49: Error: .*
+.*:50: Error: .*
+.*:51: Error: .*
+.*:52: Error: .*
+.*:53: Error: .*
+.*:54: Error: .*
+.*:55: Error: .*
+.*:56: Error: .*
+.*:57: Error: .*
+.*:58: Error: .*
+.*:59: Error: .*
+.*:60: Error: .*
+.*:61: Error: .*
+.*:62: Error: .*
+.*:63: Error: .*
+.*:64: Error: .*
+.*:65: Error: .*
+.*:66: Error: .*
+.*:67: Error: .*
+.*:68: Error: .*
+GAS LISTING .*
+
+
+[ ]*1[ ]+\# Unlockable Instructions
+[ ]*2[ ]+
+[ ]*3[ ]+\.text
+[ ]*4[ ]+foo:
+[ ]*5[ ]+lock mov %ecx, %eax
+[ ]*6[ ]+lock mov \(%ebx\), %eax
+[ ]*7[ ]+
+[ ]*8[ ]+lock add %ebx, %eax
+[ ]*9[ ]+lock add \$0x64, %ebx
+[ ]*10[ ]+lock adc %ebx, %eax
+[ ]*11[ ]+lock adc \$0x64, %ebx
+[ ]*12[ ]+lock and %ebx, %eax
+[ ]*13[ ]+lock and \$0x64, %ebx
+[ ]*14[ ]+lock btc %eax, %ebx
+[ ]*15[ ]+lock btc \$0x64, %ebx
+[ ]*16[ ]+lock btr %eax, %ebx
+[ ]*17[ ]+lock btr \$0x64, %ebx
+[ ]*18[ ]+lock bts %eax, %ebx
+[ ]*19[ ]+lock bts \$0x64, %ebx
+[ ]*20[ ]+lock cmpxchg %eax,%ebx
+[ ]*21[ ]+lock decl %ebx
+[ ]*22[ ]+lock incl %ebx
+[ ]*23[ ]+lock negl %ebx
+[ ]*24[ ]+lock notl %ebx
+[ ]*25[ ]+lock or %ebx, %eax
+[ ]*26[ ]+lock or \$0x64, %ebx
+[ ]*27[ ]+lock sbb %ebx, %eax
+[ ]*28[ ]+lock sbb \$0x64, %ebx
+[ ]*29[ ]+lock sub %ebx, %eax
+[ ]*30[ ]+lock sub \$0x64, %ebx
+[ ]*31[ ]+lock xadd %eax, %ebx
+[ ]*32[ ]+lock xchg %ebx, %eax
+[ ]*33[ ]+lock xchg %eax, %ebx
+[ ]*34[ ]+lock xor %ebx, %eax
+[ ]*35[ ]+lock xor \$0x64, %ebx
+[ ]*36[ ]+
+[ ]*37[ ]+\.intel_syntax noprefix
+[ ]*38[ ]+lock mov eax,ebx
+[ ]*39[ ]+lock mov eax,DWORD PTR \[ebx\]
+[ ]*40[ ]+
+[ ]*41[ ]+lock add eax,ebx
+[ ]*42[ ]+lock add ebx,0x64
+[ ]*43[ ]+lock adc eax,ebx
+[ ]*44[ ]+lock adc ebx,0x64
+[ ]*45[ ]+lock and eax,ebx
+[ ]*46[ ]+lock and ebx,0x64
+[ ]*47[ ]+lock btc ebx,eax
+[ ]*48[ ]+lock btc ebx,0x64
+[ ]*49[ ]+lock btr ebx,eax
+[ ]*50[ ]+lock btr ebx,0x64
+[ ]*51[ ]+lock bts ebx,eax
+[ ]*52[ ]+lock bts ebx,0x64
+[ ]*53[ ]+lock cmpxchg ebx,eax
+[ ]*54[ ]+lock dec ebx
+[ ]*55[ ]+lock inc ebx
+[ ]*56[ ]+lock neg ebx
+[ ]*57[ ]+lock not ebx
+ GAS LISTING .*
+
+
+[ ]*58[ ]+lock or eax,ebx
+[ ]*59[ ]+lock or ebx,0x64
+[ ]*60[ ]+lock sbb eax,ebx
+[ ]*61[ ]+lock sbb ebx,0x64
+[ ]*62[ ]+lock sub eax,ebx
+[ ]*63[ ]+lock sub ebx,0x64
+[ ]*64[ ]+lock xadd ebx,eax
+[ ]*65[ ]+lock xchg ebx,eax
+[ ]*66[ ]+lock xchg ebx,eax
+[ ]*67[ ]+lock xor eax,ebx
+[ ]*68[ ]+lock xor ebx,0x64
diff --git a/gas/testsuite/gas/i386/lockbad-1.s b/gas/testsuite/gas/i386/lockbad-1.s
new file mode 100644
index 0000000..dbb5b5c
--- /dev/null
+++ b/gas/testsuite/gas/i386/lockbad-1.s
@@ -0,0 +1,68 @@
+# Unlockable Instructions
+
+ .text
+foo:
+ lock mov %ecx, %eax
+ lock mov (%ebx), %eax
+
+ lock add %ebx, %eax
+ lock add $0x64, %ebx
+ lock adc %ebx, %eax
+ lock adc $0x64, %ebx
+ lock and %ebx, %eax
+ lock and $0x64, %ebx
+ lock btc %eax, %ebx
+ lock btc $0x64, %ebx
+ lock btr %eax, %ebx
+ lock btr $0x64, %ebx
+ lock bts %eax, %ebx
+ lock bts $0x64, %ebx
+ lock cmpxchg %eax,%ebx
+ lock decl %ebx
+ lock incl %ebx
+ lock negl %ebx
+ lock notl %ebx
+ lock or %ebx, %eax
+ lock or $0x64, %ebx
+ lock sbb %ebx, %eax
+ lock sbb $0x64, %ebx
+ lock sub %ebx, %eax
+ lock sub $0x64, %ebx
+ lock xadd %eax, %ebx
+ lock xchg %ebx, %eax
+ lock xchg %eax, %ebx
+ lock xor %ebx, %eax
+ lock xor $0x64, %ebx
+
+ .intel_syntax noprefix
+ lock mov eax,ebx
+ lock mov eax,DWORD PTR [ebx]
+
+ lock add eax,ebx
+ lock add ebx,0x64
+ lock adc eax,ebx
+ lock adc ebx,0x64
+ lock and eax,ebx
+ lock and ebx,0x64
+ lock btc ebx,eax
+ lock btc ebx,0x64
+ lock btr ebx,eax
+ lock btr ebx,0x64
+ lock bts ebx,eax
+ lock bts ebx,0x64
+ lock cmpxchg ebx,eax
+ lock dec ebx
+ lock inc ebx
+ lock neg ebx
+ lock not ebx
+ lock or eax,ebx
+ lock or ebx,0x64
+ lock sbb eax,ebx
+ lock sbb ebx,0x64
+ lock sub eax,ebx
+ lock sub ebx,0x64
+ lock xadd ebx,eax
+ lock xchg ebx,eax
+ lock xchg ebx,eax
+ lock xor eax,ebx
+ lock xor ebx,0x64
diff --git a/gas/testsuite/gas/i386/x86-64-lock-1-intel.d b/gas/testsuite/gas/i386/x86-64-lock-1-intel.d
new file mode 100644
index 0000000..5cc0c08
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lock-1-intel.d
@@ -0,0 +1,69 @@
+#objdump: -dwMintel
+#name: x86-64 lockable insns (Intel disassembly)
+#source: x86-64-lock-1.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: f0 03 03 lock add eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 03 64 lock add DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 13 03 lock adc eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 13 64 lock adc DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 23 03 lock and eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 23 64 lock and DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f bb 03 lock btc DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 3b 64 lock btc DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f b3 03 lock btr DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 33 64 lock btr DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f ab 03 lock bts DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 f7 13 lock not DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 0b 03 lock or eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 0b 64 lock or DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 1b 03 lock sbb eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 1b 64 lock sbb DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 2b 03 lock sub eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 2b 64 lock sub DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f c1 03 lock xadd DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 87 03 lock xchg DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 87 03 lock xchg DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 33 03 lock xor eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 33 64 lock xor DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 03 03 lock add eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 03 64 lock add DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 13 03 lock adc eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 13 64 lock adc DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 23 03 lock and eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 23 64 lock and DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f bb 03 lock btc DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 3b 64 lock btc DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f b3 03 lock btr DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 33 64 lock btr DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f ab 03 lock bts DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 f7 13 lock not DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 0b 03 lock or eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 0b 64 lock or DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 1b 03 lock sbb eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 1b 64 lock sbb DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 2b 03 lock sub eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 2b 64 lock sub DWORD PTR \[rbx\],0x64
+[ ]*[a-f0-9]+: f0 0f c1 03 lock xadd DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 87 03 lock xchg DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 87 03 lock xchg DWORD PTR \[rbx\],eax
+[ ]*[a-f0-9]+: f0 33 03 lock xor eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: f0 83 33 64 lock xor DWORD PTR \[rbx\],0x64
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-lock-1.d b/gas/testsuite/gas/i386/x86-64-lock-1.d
new file mode 100644
index 0000000..112f289
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lock-1.d
@@ -0,0 +1,68 @@
+#objdump: -dw
+#name: x86-64 lockable insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: f0 03 03 lock add \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 03 64 lock addl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 13 03 lock adc \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 13 64 lock adcl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 23 03 lock and \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 23 64 lock andl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f bb 03 lock btc %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f ba 3b 64 lock btcl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f b3 03 lock btr %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f ba 33 64 lock btrl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f ab 03 lock bts %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%rbx\)
+[ ]*[a-f0-9]+: f0 ff 0b lock decl \(%rbx\)
+[ ]*[a-f0-9]+: f0 ff 03 lock incl \(%rbx\)
+[ ]*[a-f0-9]+: f0 f7 1b lock negl \(%rbx\)
+[ ]*[a-f0-9]+: f0 f7 13 lock notl \(%rbx\)
+[ ]*[a-f0-9]+: f0 0b 03 lock or \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 0b 64 lock orl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 1b 03 lock sbb \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 1b 64 lock sbbl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 2b 03 lock sub \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 2b 64 lock subl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f c1 03 lock xadd %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 87 03 lock xchg %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 87 03 lock xchg %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 33 03 lock xor \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 33 64 lock xorl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 03 03 lock add \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 03 64 lock addl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 13 03 lock adc \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 13 64 lock adcl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 23 03 lock and \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 23 64 lock andl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f bb 03 lock btc %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f ba 3b 64 lock btcl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f b3 03 lock btr %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f ba 33 64 lock btrl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f ab 03 lock bts %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%rbx\)
+[ ]*[a-f0-9]+: f0 ff 0b lock decl \(%rbx\)
+[ ]*[a-f0-9]+: f0 ff 03 lock incl \(%rbx\)
+[ ]*[a-f0-9]+: f0 f7 1b lock negl \(%rbx\)
+[ ]*[a-f0-9]+: f0 f7 13 lock notl \(%rbx\)
+[ ]*[a-f0-9]+: f0 0b 03 lock or \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 0b 64 lock orl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 1b 03 lock sbb \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 1b 64 lock sbbl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 2b 03 lock sub \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 2b 64 lock subl \$0x64,\(%rbx\)
+[ ]*[a-f0-9]+: f0 0f c1 03 lock xadd %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 87 03 lock xchg %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 87 03 lock xchg %eax,\(%rbx\)
+[ ]*[a-f0-9]+: f0 33 03 lock xor \(%rbx\),%eax
+[ ]*[a-f0-9]+: f0 83 33 64 lock xorl \$0x64,\(%rbx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-lock-1.s b/gas/testsuite/gas/i386/x86-64-lock-1.s
new file mode 100644
index 0000000..5f21dce
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lock-1.s
@@ -0,0 +1,64 @@
+# 64bit lockable Instructions
+
+ .text
+foo:
+ lock add (%rbx), %eax
+ lock add $0x64, (%rbx)
+ lock adc (%rbx), %eax
+ lock adc $0x64, (%rbx)
+ lock and (%rbx), %eax
+ lock and $0x64, (%rbx)
+ lock btc %eax, (%rbx)
+ lock btc $0x64, (%rbx)
+ lock btr %eax, (%rbx)
+ lock btr $0x64, (%rbx)
+ lock bts %eax, (%rbx)
+ lock bts $0x64, (%rbx)
+ lock cmpxchg %eax,(%rbx)
+ lock cmpxchg8b (%rbx)
+ lock decl (%rbx)
+ lock incl (%rbx)
+ lock negl (%rbx)
+ lock notl (%rbx)
+ lock or (%rbx), %eax
+ lock or $0x64, (%rbx)
+ lock sbb (%rbx), %eax
+ lock sbb $0x64, (%rbx)
+ lock sub (%rbx), %eax
+ lock sub $0x64, (%rbx)
+ lock xadd %eax, (%rbx)
+ lock xchg (%rbx), %eax
+ lock xchg %eax, (%rbx)
+ lock xor (%rbx), %eax
+ lock xor $0x64, (%rbx)
+
+ .intel_syntax noprefix
+ lock add eax,DWORD PTR [rbx]
+ lock add DWORD PTR [rbx],0x64
+ lock adc eax,DWORD PTR [rbx]
+ lock adc DWORD PTR [rbx],0x64
+ lock and eax,DWORD PTR [rbx]
+ lock and DWORD PTR [rbx],0x64
+ lock btc DWORD PTR [rbx],eax
+ lock btc DWORD PTR [rbx],0x64
+ lock btr DWORD PTR [rbx],eax
+ lock btr DWORD PTR [rbx],0x64
+ lock bts DWORD PTR [rbx],eax
+ lock bts DWORD PTR [rbx],0x64
+ lock cmpxchg DWORD PTR [rbx],eax
+ lock cmpxchg8b QWORD PTR [rbx]
+ lock dec DWORD PTR [rbx]
+ lock inc DWORD PTR [rbx]
+ lock neg DWORD PTR [rbx]
+ lock not DWORD PTR [rbx]
+ lock or eax,DWORD PTR [rbx]
+ lock or DWORD PTR [rbx],0x64
+ lock sbb eax,DWORD PTR [rbx]
+ lock sbb DWORD PTR [rbx],0x64
+ lock sub eax,DWORD PTR [rbx]
+ lock sub DWORD PTR [rbx],0x64
+ lock xadd DWORD PTR [rbx],eax
+ lock xchg DWORD PTR [rbx],eax
+ lock xchg DWORD PTR [rbx],eax
+ lock xor eax,DWORD PTR [rbx]
+ lock xor DWORD PTR [rbx],0x64
diff --git a/gas/testsuite/gas/i386/x86-64-lockbad-1.l b/gas/testsuite/gas/i386/x86-64-lockbad-1.l
new file mode 100644
index 0000000..9753e14
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lockbad-1.l
@@ -0,0 +1,135 @@
+.*: Assembler messages:
+.*:5: Error: .*
+.*:6: Error: .*
+.*:8: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:14: Error: .*
+.*:15: Error: .*
+.*:16: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:22: Error: .*
+.*:23: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:30: Error: .*
+.*:31: Error: .*
+.*:32: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:35: Error: .*
+.*:38: Error: .*
+.*:39: Error: .*
+.*:41: Error: .*
+.*:42: Error: .*
+.*:43: Error: .*
+.*:44: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:49: Error: .*
+.*:50: Error: .*
+.*:51: Error: .*
+.*:52: Error: .*
+.*:53: Error: .*
+.*:54: Error: .*
+.*:55: Error: .*
+.*:56: Error: .*
+.*:57: Error: .*
+.*:58: Error: .*
+.*:59: Error: .*
+.*:60: Error: .*
+.*:61: Error: .*
+.*:62: Error: .*
+.*:63: Error: .*
+.*:64: Error: .*
+.*:65: Error: .*
+.*:66: Error: .*
+.*:67: Error: .*
+.*:68: Error: .*
+GAS LISTING .*
+
+
+[ ]*1[ ]+\# 64bit unlockable Instructions
+[ ]*2[ ]+
+[ ]*3[ ]+\.text
+[ ]*4[ ]+foo:
+[ ]*5[ ]+lock mov %ecx, %eax
+[ ]*6[ ]+lock mov \(%rbx\), %eax
+[ ]*7[ ]+
+[ ]*8[ ]+lock add %ebx, %eax
+[ ]*9[ ]+lock add \$0x64, %ebx
+[ ]*10[ ]+lock adc %ebx, %eax
+[ ]*11[ ]+lock adc \$0x64, %ebx
+[ ]*12[ ]+lock and %ebx, %eax
+[ ]*13[ ]+lock and \$0x64, %ebx
+[ ]*14[ ]+lock btc %eax, %ebx
+[ ]*15[ ]+lock btc \$0x64, %ebx
+[ ]*16[ ]+lock btr %eax, %ebx
+[ ]*17[ ]+lock btr \$0x64, %ebx
+[ ]*18[ ]+lock bts %eax, %ebx
+[ ]*19[ ]+lock bts \$0x64, %ebx
+[ ]*20[ ]+lock cmpxchg %eax,%ebx
+[ ]*21[ ]+lock decl %ebx
+[ ]*22[ ]+lock incl %ebx
+[ ]*23[ ]+lock negl %ebx
+[ ]*24[ ]+lock notl %ebx
+[ ]*25[ ]+lock or %ebx, %eax
+[ ]*26[ ]+lock or \$0x64, %ebx
+[ ]*27[ ]+lock sbb %ebx, %eax
+[ ]*28[ ]+lock sbb \$0x64, %ebx
+[ ]*29[ ]+lock sub %ebx, %eax
+[ ]*30[ ]+lock sub \$0x64, %ebx
+[ ]*31[ ]+lock xadd %eax, %ebx
+[ ]*32[ ]+lock xchg %ebx, %eax
+[ ]*33[ ]+lock xchg %eax, %ebx
+[ ]*34[ ]+lock xor %ebx, %eax
+[ ]*35[ ]+lock xor \$0x64, %ebx
+[ ]*36[ ]+
+[ ]*37[ ]+\.intel_syntax noprefix
+[ ]*38[ ]+lock mov eax,ebx
+[ ]*39[ ]+lock mov eax,DWORD PTR \[rbx\]
+[ ]*40[ ]+
+[ ]*41[ ]+lock add eax,ebx
+[ ]*42[ ]+lock add ebx,0x64
+[ ]*43[ ]+lock adc eax,ebx
+[ ]*44[ ]+lock adc ebx,0x64
+[ ]*45[ ]+lock and eax,ebx
+[ ]*46[ ]+lock and ebx,0x64
+[ ]*47[ ]+lock btc ebx,eax
+[ ]*48[ ]+lock btc ebx,0x64
+[ ]*49[ ]+lock btr ebx,eax
+[ ]*50[ ]+lock btr ebx,0x64
+[ ]*51[ ]+lock bts ebx,eax
+[ ]*52[ ]+lock bts ebx,0x64
+[ ]*53[ ]+lock cmpxchg ebx,eax
+[ ]*54[ ]+lock dec ebx
+[ ]*55[ ]+lock inc ebx
+[ ]*56[ ]+lock neg ebx
+[ ]*57[ ]+lock not ebx
+ GAS LISTING .*
+
+
+[ ]*58[ ]+lock or eax,ebx
+[ ]*59[ ]+lock or ebx,0x64
+[ ]*60[ ]+lock sbb eax,ebx
+[ ]*61[ ]+lock sbb ebx,0x64
+[ ]*62[ ]+lock sub eax,ebx
+[ ]*63[ ]+lock sub ebx,0x64
+[ ]*64[ ]+lock xadd ebx,eax
+[ ]*65[ ]+lock xchg ebx,eax
+[ ]*66[ ]+lock xchg ebx,eax
+[ ]*67[ ]+lock xor eax,ebx
+[ ]*68[ ]+lock xor ebx,0x64
diff --git a/gas/testsuite/gas/i386/x86-64-lockbad-1.s b/gas/testsuite/gas/i386/x86-64-lockbad-1.s
new file mode 100644
index 0000000..6a20a0c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lockbad-1.s
@@ -0,0 +1,68 @@
+# 64bit unlockable Instructions
+
+ .text
+foo:
+ lock mov %ecx, %eax
+ lock mov (%rbx), %eax
+
+ lock add %ebx, %eax
+ lock add $0x64, %ebx
+ lock adc %ebx, %eax
+ lock adc $0x64, %ebx
+ lock and %ebx, %eax
+ lock and $0x64, %ebx
+ lock btc %eax, %ebx
+ lock btc $0x64, %ebx
+ lock btr %eax, %ebx
+ lock btr $0x64, %ebx
+ lock bts %eax, %ebx
+ lock bts $0x64, %ebx
+ lock cmpxchg %eax,%ebx
+ lock decl %ebx
+ lock incl %ebx
+ lock negl %ebx
+ lock notl %ebx
+ lock or %ebx, %eax
+ lock or $0x64, %ebx
+ lock sbb %ebx, %eax
+ lock sbb $0x64, %ebx
+ lock sub %ebx, %eax
+ lock sub $0x64, %ebx
+ lock xadd %eax, %ebx
+ lock xchg %ebx, %eax
+ lock xchg %eax, %ebx
+ lock xor %ebx, %eax
+ lock xor $0x64, %ebx
+
+ .intel_syntax noprefix
+ lock mov eax,ebx
+ lock mov eax,DWORD PTR [rbx]
+
+ lock add eax,ebx
+ lock add ebx,0x64
+ lock adc eax,ebx
+ lock adc ebx,0x64
+ lock and eax,ebx
+ lock and ebx,0x64
+ lock btc ebx,eax
+ lock btc ebx,0x64
+ lock btr ebx,eax
+ lock btr ebx,0x64
+ lock bts ebx,eax
+ lock bts ebx,0x64
+ lock cmpxchg ebx,eax
+ lock dec ebx
+ lock inc ebx
+ lock neg ebx
+ lock not ebx
+ lock or eax,ebx
+ lock or ebx,0x64
+ lock sbb eax,ebx
+ lock sbb ebx,0x64
+ lock sub eax,ebx
+ lock sub ebx,0x64
+ lock xadd ebx,eax
+ lock xchg ebx,eax
+ lock xchg ebx,eax
+ lock xor eax,ebx
+ lock xor ebx,0x64
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index d877f83..3ddd4b6 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -337,6 +337,7 @@ static bitfield opcode_modifiers[] =
BITFIELD (No_ldSuf),
BITFIELD (FWait),
BITFIELD (IsString),
+ BITFIELD (IsLockable),
BITFIELD (RegKludge),
BITFIELD (FirstXmm0),
BITFIELD (Implicit1stXmm0),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index f8de8cd..cee1303 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -240,6 +240,8 @@ enum
FWait,
/* quick test for string instructions */
IsString,
+ /* quick test for lockable instructions */
+ IsLockable,
/* fake an extra reg operand for clr, imul and special register
processing for some instructions. */
RegKludge,
@@ -340,6 +342,7 @@ typedef struct i386_opcode_modifier
unsigned int no_ldsuf:1;
unsigned int fwait:1;
unsigned int isstring:1;
+ unsigned int islockable:1;
unsigned int regkludge:1;
unsigned int firstxmm0:1;
unsigned int implicit1stxmm0:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 2253ffa..8883029 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -126,10 +126,10 @@ popa, 0, 0x61, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_l
// xchg commutes: we allow both operand orders.
// In the 64bit code, xchg rax, rax is reused for new nop instruction.
-xchg, 2, 0x90, None, 1, 0, ShortForm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
-xchg, 2, 0x90, None, 1, 0, ShortForm|No_bSuf|No_sSuf|No_ldSuf, { Acc|Word|Dword|Qword, Reg16|Reg32|Reg64 }
-xchg, 2, 0x86, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-xchg, 2, 0x86, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 }
+xchg, 2, 0x90, None, 1, 0, ShortForm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
+xchg, 2, 0x90, None, 1, 0, ShortForm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Acc|Word|Dword|Qword, Reg16|Reg32|Reg64 }
+xchg, 2, 0x86, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+xchg, 2, 0x86, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 }
// In/out from ports.
in, 2, 0xe4, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Acc|Byte|Word|Dword }
@@ -168,26 +168,26 @@ std, 0, 0xfd, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0
sti, 0, 0xfb, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
// Arithmetic.
-add, 2, 0x0, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-add, 2, 0x83, 0x0, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-add, 2, 0x4, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-add, 2, 0x80, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+add, 2, 0x0, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+add, 2, 0x83, 0x0, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+add, 2, 0x4, None, 1, 0, W|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+add, 2, 0x80, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-inc, 1, 0x40, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
-inc, 1, 0xfe, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+inc, 1, 0x40, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|IsLockable, { Reg16|Reg32 }
+inc, 1, 0xfe, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-sub, 2, 0x28, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-sub, 2, 0x83, 0x5, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-sub, 2, 0x2c, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-sub, 2, 0x80, 0x5, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+sub, 2, 0x28, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+sub, 2, 0x83, 0x5, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+sub, 2, 0x2c, None, 1, 0, W|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+sub, 2, 0x80, 0x5, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-dec, 1, 0x48, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
-dec, 1, 0xfe, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+dec, 1, 0x48, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|IsLockable, { Reg16|Reg32 }
+dec, 1, 0xfe, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-sbb, 2, 0x18, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-sbb, 2, 0x83, 0x3, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-sbb, 2, 0x1c, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-sbb, 2, 0x80, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+sbb, 2, 0x18, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+sbb, 2, 0x83, 0x3, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+sbb, 2, 0x1c, None, 1, 0, W|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+sbb, 2, 0x80, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
cmp, 2, 0x38, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
cmp, 2, 0x83, 0x7, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
@@ -199,31 +199,31 @@ test, 2, 0x84, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Byte|Word|Dword|Qword|Uns
test, 2, 0xa8, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
test, 2, 0xf6, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-and, 2, 0x20, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-and, 2, 0x83, 0x4, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-and, 2, 0x24, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-and, 2, 0x80, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+and, 2, 0x20, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+and, 2, 0x83, 0x4, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+and, 2, 0x24, None, 1, 0, W|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+and, 2, 0x80, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-or, 2, 0x8, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-or, 2, 0x83, 0x1, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-or, 2, 0xc, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-or, 2, 0x80, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+or, 2, 0x8, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+or, 2, 0x83, 0x1, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+or, 2, 0xc, None, 1, 0, W|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+or, 2, 0x80, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-xor, 2, 0x30, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-xor, 2, 0x83, 0x6, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-xor, 2, 0x34, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-xor, 2, 0x80, 0x6, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+xor, 2, 0x30, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+xor, 2, 0x83, 0x6, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+xor, 2, 0x34, None, 1, 0, W|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+xor, 2, 0x80, 0x6, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
// clr with 1 operand is really xor with 2 operands.
clr, 1, 0x30, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge, { Reg8|Reg16|Reg32|Reg64 }
-adc, 2, 0x10, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-adc, 2, 0x83, 0x2, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-adc, 2, 0x14, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-adc, 2, 0x80, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+adc, 2, 0x10, None, 1, 0, D|W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+adc, 2, 0x83, 0x2, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+adc, 2, 0x14, None, 1, 0, W|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+adc, 2, 0x80, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-neg, 1, 0xf6, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-not, 1, 0xf6, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+neg, 1, 0xf6, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+not, 1, 0xf6, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
aaa, 0, 0x37, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
aas, 0, 0x3f, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
@@ -479,12 +479,12 @@ bsf, 2, 0xfbc, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Re
bsr, 2, 0xfbd, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
bt, 2, 0xfa3, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
bt, 2, 0xfba, 0x4, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-btc, 2, 0xfbb, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-btc, 2, 0xfba, 0x7, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-btr, 2, 0xfb3, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-btr, 2, 0xfba, 0x6, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-bts, 2, 0xfab, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-bts, 2, 0xfba, 0x5, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+btc, 2, 0xfbb, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+btc, 2, 0xfba, 0x7, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+btr, 2, 0xfb3, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+btr, 2, 0xfba, 0x6, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+bts, 2, 0xfab, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+bts, 2, 0xfba, 0x5, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
// Interrupts & op. sys insns.
// See gas/config/tc-i386.c for conversion of 'int $3' into the special
@@ -829,8 +829,8 @@ rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
// 486 extensions.
bswap, 1, 0xfc8, None, 2, Cpu486, ShortForm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64 }
-xadd, 2, 0xfc0, None, 2, Cpu486, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-cmpxchg, 2, 0xfb0, None, 2, Cpu486, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+xadd, 2, 0xfc0, None, 2, Cpu486, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+cmpxchg, 2, 0xfb0, None, 2, Cpu486, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
invd, 0, 0xf08, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
wbinvd, 0, 0xf09, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
invlpg, 1, 0xf01, 0x7, 2, Cpu486, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
@@ -842,7 +842,7 @@ cpuid, 0, 0xfa2, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
wrmsr, 0, 0xf30, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
rdtsc, 0, 0xf31, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
rdmsr, 0, 0xf32, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-cmpxchg8b, 1, 0xfc7, 0x1, 2, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+cmpxchg8b, 1, 0xfc7, 0x1, 2, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|IsLockable, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
// Pentium II/Pentium Pro extensions.
sysenter, 0, 0xf34, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }